asm/arch-mx25/imx-regs.h

27 	u32 cgr0;	/* Clock Gating Control 0 */
33 	u32 dcvr0;	/* DPTC Comparator Value 0 */
37 	u32 ltr0;	/* Load Tracking 0 */
41 	u32 ltbr0;	/* Load Tracking Buffer 0 */
43 	u32 pcmr0;	/* Power Management Control 0 */
47 	u32 lpimr0;	/* Low Power Interrupt Mask 0 */
53 	u32 ctl0; 	/* control 0 */
54 	u32 cfg0; 	/* configuration 0 */
104 	u32 res1[0x1f1];
106 		u32 fuse_regs[0x20];
107 		u32 fuse_rsvd[0xe0];
114 	u32 fuse16_25[0xa];
119 	u32 fuse0_21[0x16];
200 	u32 cscr0u;	/* Chip Select 0 Upper Register */
201 	u32 cscr0l;	/* Chip Select 0 Lower Register */
202 	u32 cscr0a;	/* Chip Select 0 Addition Register */
230 	u32 wcfg0;	/* Watermark Configuration Register 0 */
239 	u32 scfg0;	/* Snooping Configuration Register 0 */
242 	u32 ssr0;	/* Snooping Status Register 0 */
289 #define IMX_AIPS1_BASE		(0x43F00000)
290 #define IMX_MAX_BASE		(0x43F04000)
291 #define IMX_CLKCTL_BASE		(0x43F08000)
292 #define IMX_ETB_SLOT4_BASE	(0x43F0C000)
293 #define IMX_ETB_SLOT5_BASE	(0x43F10000)
294 #define IMX_ECT_CTIO_BASE	(0x43F18000)
295 #define I2C1_BASE_ADDR		(0x43F80000)
296 #define I2C3_BASE_ADDR		(0x43F84000)
297 #define IMX_CAN1_BASE		(0x43F88000)
298 #define IMX_CAN2_BASE		(0x43F8C000)
299 #define UART1_BASE		(0x43F90000)
300 #define UART2_BASE		(0x43F94000)
301 #define I2C2_BASE_ADDR		(0x43F98000)
302 #define IMX_OWIRE_BASE		(0x43F9C000)
303 #define IMX_CSPI1_BASE		(0x43FA4000)
304 #define IMX_KPP_BASE		(0x43FA8000)
305 #define IMX_IOPADMUX_BASE	(0x43FAC000)
307 #define IMX_IOPADCTL_BASE	(0x43FAC22C)
308 #define IMX_IOPADGRPCTL_BASE	(0x43FAC418)
309 #define IMX_IOPADINPUTSEL_BASE	(0x43FAC460)
310 #define IMX_AUDMUX_BASE		(0x43FB0000)
311 #define IMX_ECT_IP1_BASE	(0x43FB8000)
312 #define IMX_ECT_IP2_BASE	(0x43FBC000)
315 #define IMX_SPBA_BASE		(0x50000000)
316 #define IMX_CSPI3_BASE		(0x50004000)
317 #define UART4_BASE		(0x50008000)
318 #define UART3_BASE		(0x5000C000)
319 #define IMX_CSPI2_BASE		(0x50010000)
320 #define IMX_SSI2_BASE		(0x50014000)
321 #define IMX_ESAI_BASE		(0x50018000)
322 #define IMX_ATA_DMA_BASE	(0x50020000)
323 #define IMX_SIM1_BASE		(0x50024000)
324 #define IMX_SIM2_BASE		(0x50028000)
325 #define UART5_BASE		(0x5002C000)
326 #define IMX_TSC_BASE		(0x50030000)
327 #define IMX_SSI1_BASE		(0x50034000)
328 #define IMX_FEC_BASE		(0x50038000)
329 #define IMX_SPBA_CTRL_BASE	(0x5003C000)
332 #define IMX_AIPS2_BASE		(0x53F00000)
333 #define IMX_CCM_BASE		(0x53F80000)
334 #define IMX_GPT4_BASE		(0x53F84000)
335 #define IMX_GPT3_BASE		(0x53F88000)
336 #define IMX_GPT2_BASE		(0x53F8C000)
337 #define IMX_GPT1_BASE		(0x53F90000)
338 #define IMX_EPIT1_BASE		(0x53F94000)
339 #define IMX_EPIT2_BASE		(0x53F98000)
340 #define IMX_GPIO4_BASE		(0x53F9C000)
341 #define IMX_PWM2_BASE		(0x53FA0000)
342 #define IMX_GPIO3_BASE		(0x53FA4000)
343 #define IMX_PWM3_BASE		(0x53FA8000)
344 #define IMX_SCC_BASE		(0x53FAC000)
345 #define IMX_SCM_BASE		(0x53FAE000)
346 #define IMX_SMN_BASE		(0x53FAF000)
347 #define IMX_RNGD_BASE		(0x53FB0000)
348 #define IMX_MMC_SDHC1_BASE	(0x53FB4000)
349 #define IMX_MMC_SDHC2_BASE	(0x53FB8000)
350 #define IMX_LCDC_BASE		(0x53FBC000)
351 #define IMX_SLCDC_BASE		(0x53FC0000)
352 #define IMX_PWM4_BASE		(0x53FC8000)
353 #define IMX_GPIO1_BASE		(0x53FCC000)
354 #define IMX_GPIO2_BASE		(0x53FD0000)
355 #define IMX_SDMA_BASE		(0x53FD4000)
356 #define IMX_WDT_BASE		(0x53FDC000)
358 #define IMX_PWM1_BASE		(0x53FE0000)
359 #define IMX_RTIC_BASE		(0x53FEC000)
360 #define IMX_IIM_BASE		(0x53FF0000)
362 #define IMX_USB_BASE		(0x53FF4000)
365  * port 1's registers start at 0x53FF4200. The correct base address for
366  * port 1 is 0x53FF4400. The kernel uses 0x53FF4400 as well.
368 #define IMX_USB_PORT_OFFSET	0x400
369 #define IMX_CSI_BASE		(0x53FF8000)
370 #define IMX_DRYICE_BASE		(0x53FFC000)
372 #define IMX_ARM926_ROMPATCH	(0x60000000)
373 #define IMX_ARM926_ASIC		(0x68000000)
376 #define IMX_RAM_BASE		(0x78000000)
380 #define IMX_SDRAM_BANK0_BASE	(0x80000000)
381 #define IMX_SDRAM_BANK1_BASE	(0x90000000)
383 #define IMX_WEIM_CS0		(0xA0000000)
384 #define IMX_WEIM_CS1		(0xA8000000)
385 #define IMX_WEIM_CS2		(0xB0000000)
386 #define IMX_WEIM_CS3		(0xB2000000)
387 #define IMX_WEIM_CS4		(0xB4000000)
388 #define IMX_ESDRAMC_BASE	(0xB8001000)
389 #define IMX_WEIM_CTRL_BASE	(0xB8002000)
390 #define IMX_M3IF_CTRL_BASE	(0xB8003000)
391 #define IMX_EMI_CTRL_BASE	(0xB8004000)
394 #define IMX_NFC_BASE		(0xBB000000)
399 #define CCM_PLL_MFI_MASK	0xf
400 #define CCM_PLL_MFN_SHIFT	0
401 #define CCM_PLL_MFN_MASK	0x3ff
403 #define CCM_PLL_MFD_MASK	0x3ff
405 #define CCM_PLL_PD_MASK		0xf
414 #define CCM_PERCLK_MASK		0x3f
421 #define ESDCTL_PRCT(x)		(((x) & 0x3f) << 0)
426 #define ESDCTL_DSIZ_16_UPPER	(0 << 16)
429 #define ESDCTL_COL8		(0 << 20)
432 #define ESDCTL_ROW11		(0 << 24)
438 #define ESDCTL_SMODE_NORMAL	(0 << 28)
445 #define ESDCFG_TRC(x)		(((x) & 0xf) << 0)
446 #define ESDCFG_TRCD(x)		(((x) & 0x7) << 4)
447 #define ESDCFG_TCAS(x)		(((x) & 0x3) << 8)
448 #define ESDCFG_TRRD(x)		(((x) & 0x3) << 10)
449 #define ESDCFG_TRAS(x)		(((x) & 0x7) << 12)
451 #define ESDCFG_TMRD(x)		(((x) & 0x3) << 16)
452 #define ESDCFG_TRP(x)		(((x) & 0x3) << 18)
454 #define ESDCFG_TXP(x)		(((x) & 0x3) << 21)
471 #define WCR_WDE 		0x04
472 #define WSR_UNLOCK1		0x5555
473 #define WSR_UNLOCK2		0xAAAA
476 #define MAX_MGPCR_AULB(x)	(((x) & 0x7) << 0)
479 #define M3IF_CTL_MRRP(x)	(((x) & 0xff) << 0)
487 		(cnc) << 14 | (wsc) << 8 | (ew) << 7 | (wws) << 4 | (edc) << 0)
493 		(psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0)
500 		(age) << 2 | (cnc2) << 1 | (fce) << 0)
512 #define MXC_CSPICTRL_EN		(1 << 0)
520 #define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
521 #define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
522 #define MXC_CSPICTRL_DATARATE(x)	(((x) & 0x7) << 16)
525 #define MXC_CSPICTRL_MAXBITS	0xfff