Lines Matching +full:0 +full:xb8002000
16 #define IRAM_BASE_ADDR 0x10000000 /* internal ram */
17 #define IRAM_SIZE 0x00020000 /* 128 KB */
19 #define LOW_LEVEL_SRAM_STACK 0x1001E000
24 #define AIPS1_BASE_ADDR 0x43F00000
26 #define MAX_BASE_ADDR 0x43F04000
27 #define EVTMON_BASE_ADDR 0x43F08000
28 #define CLKCTL_BASE_ADDR 0x43F0C000
29 #define I2C1_BASE_ADDR 0x43F80000
30 #define I2C3_BASE_ADDR 0x43F84000
31 #define ATA_BASE_ADDR 0x43F8C000
32 #define UART1_BASE 0x43F90000
33 #define UART2_BASE 0x43F94000
34 #define I2C2_BASE_ADDR 0x43F98000
35 #define CSPI1_BASE_ADDR 0x43FA4000
36 #define IOMUXC_BASE_ADDR 0x43FAC000
41 #define SPBA_BASE_ADDR 0x50000000
42 #define UART3_BASE 0x5000C000
43 #define CSPI2_BASE_ADDR 0x50010000
44 #define ATA_DMA_BASE_ADDR 0x50020000
45 #define FEC_BASE_ADDR 0x50038000
46 #define SPBA_CTRL_BASE_ADDR 0x5003C000
51 #define AIPS2_BASE_ADDR 0x53F00000
53 #define CCM_BASE_ADDR 0x53F80000
54 #define GPT1_BASE_ADDR 0x53F90000
55 #define EPIT1_BASE_ADDR 0x53F94000
56 #define EPIT2_BASE_ADDR 0x53F98000
57 #define GPIO3_BASE_ADDR 0x53FA4000
58 #define MMC_SDHC1_BASE_ADDR 0x53FB4000
59 #define MMC_SDHC2_BASE_ADDR 0x53FB8000
60 #define MMC_SDHC3_BASE_ADDR 0x53FBC000
61 #define IPU_CTRL_BASE_ADDR 0x53FC0000
62 #define GPIO1_BASE_ADDR 0x53FCC000
63 #define GPIO2_BASE_ADDR 0x53FD0000
64 #define SDMA_BASE_ADDR 0x53FD4000
65 #define RTC_BASE_ADDR 0x53FD8000
66 #define WDOG1_BASE_ADDR 0x53FDC000
67 #define PWM_BASE_ADDR 0x53FE0000
68 #define RTIC_BASE_ADDR 0x53FEC000
69 #define IIM_BASE_ADDR 0x53FF0000
70 #define IMX_USB_BASE 0x53FF4000
71 #define IMX_USB_PORT_OFFSET 0x400
78 #define ROMPATCH_BASE_ADDR 0x60000000
79 #define AVIC_BASE_ADDR 0x68000000
84 #define EXT_MEM_CTRL_BASE 0xB8000000
85 #define ESDCTL_BASE_ADDR 0xB8001000
86 #define WEIM_BASE_ADDR 0xB8002000
88 #define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10)
89 #define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20)
90 #define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30)
91 #define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40)
92 #define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50)
93 #define M3IF_BASE_ADDR 0xB8003000
94 #define EMI_BASE_ADDR 0xB8004000
96 #define NFC_BASE_ADDR 0xBB000000
101 #define IPU_MEM_BASE_ADDR 0x70000000
102 #define CSD0_BASE_ADDR 0x80000000
103 #define CSD1_BASE_ADDR 0x90000000
104 #define CS0_BASE_ADDR 0xA0000000
105 #define CS1_BASE_ADDR 0xA8000000
106 #define CS2_BASE_ADDR 0xB0000000
107 #define CS3_BASE_ADDR 0xB2000000
108 #define CS4_BASE_ADDR 0xB4000000
109 #define CS5_BASE_ADDR 0xB6000000
114 #define AVIC_NIMASK 0x04
115 #define AVIC_INTTYPEH 0x18
116 #define AVIC_INTTYPEL 0x1C
119 #define L2CC_BASE_ADDR 0x30000000
121 #define L2_CACHE_CTL_REG 0x100
122 #define L2_CACHE_AUX_CTL_REG 0x104
123 #define L2_CACHE_SYNC_REG 0x730
124 #define L2_CACHE_INV_LINE_REG 0x770
125 #define L2_CACHE_INV_WAY_REG 0x77C
126 #define L2_CACHE_CLEAN_LINE_REG 0x7B0
127 #define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0
128 #define L2_CACHE_DBG_CTL_REG 0xF40
130 #define CLKMODE_AUTO 0
133 #define PLL_PD(x) (((x) & 0xf) << 26)
134 #define PLL_MFD(x) (((x) & 0x3ff) << 16)
135 #define PLL_MFI(x) (((x) & 0xf) << 10)
136 #define PLL_MFN(x) (((x) & 0x3ff) << 0)
148 #define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
149 #define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
151 #define CSCR_U(x) (WEIM_CTRL_CS#x + 0)
155 #define IIM_SREV 0x24
156 #define ROMPATCH_REV 0x40
168 #define IPU_CONF_CSI_EN (1<<0)
174 #define MXC_CSPICTRL_EN (1 << 0)
182 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
183 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
184 #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
187 #define MXC_CSPICTRL_MAXBITS 0xfff
192 0x43fa4000, \
193 0x50010000,
198 #define CHIP_REV_1_0 0x10
199 #define CHIP_REV_2_0 0x20
201 #define BOARD_REV_1_0 0x0
202 #define BOARD_REV_2_0 0x1
210 u32 pdr0; /* Post divider 0 */
220 u32 cgr0; /* Clock Gating Control 0 */
225 u32 dcvr0; /* DPTC Comparator 0 */
226 u32 dcvr1; /* DPTC Comparator 0 */
227 u32 dcvr2; /* DPTC Comparator 0 */
228 u32 dcvr3; /* DPTC Comparator 0 */
229 u32 ltr0; /* Load Tracking 0 */
233 u32 ltbr0; /* Load Tracking Buffer 0 */
253 u32 res1[0x1f1];
255 u32 fuse_regs[0x20];
256 u32 fuse_rsvd[0xe0];
263 u32 fuse16_31[0x10];
267 u32 fuse0_21[0x16];