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/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dcmd_errata.c25 void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000; in check_erratum_a4849()
30 0x50, 0x54, 0x58, 0x90, 0x94, 0x98 in check_erratum_a4849()
35 0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac in check_erratum_a4849()
38 uint32_t x108; /* The value that should be at offset 0x108 */ in check_erratum_a4849() local
40 for (i = 0; i < ARRAY_SIZE(offsets); i++) { in check_erratum_a4849()
48 x108 = 0x12; in check_erratum_a4849()
53 * For P4080, the erratum document says that the value at offset 0x108 in check_erratum_a4849()
54 * should be 0x12 on rev2, or 0x1c on rev3. in check_erratum_a4849()
57 x108 = 0x12; in check_erratum_a4849()
59 x108 = 0x1c; in check_erratum_a4849()
[all …]
/openbmc/linux/arch/arm/mach-orion5x/
H A Dbridge-regs.h9 #define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100)
11 #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)
13 #define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)
14 #define RSTOUTn_MASK_PHYS (ORION5X_BRIDGE_PHYS_BASE + 0x108)
16 #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
18 #define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110)
20 #define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
22 #define BRIDGE_INT_TIMER1_CLR (~0x0004)
24 #define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200)
26 #define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204)
[all …]
/openbmc/linux/arch/mips/include/asm/
H A Dhpet.h9 #define HPET_ID 0x000
10 #define HPET_PERIOD 0x004
11 #define HPET_CFG 0x010
12 #define HPET_STATUS 0x020
13 #define HPET_COUNTER 0x0f0
15 #define HPET_Tn_CFG(n) (0x100 + 0x20 * n)
16 #define HPET_Tn_CMP(n) (0x108 + 0x20 * n)
17 #define HPET_Tn_ROUTE(n) (0x110 + 0x20 * n)
19 #define HPET_T0_IRS 0x001
20 #define HPET_T1_IRS 0x002
[all …]
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx8ulp.c64 0xa8, 0xac, 0xc8, 0xcc, 0xd0,
65 0xd4, 0xd8, 0xdc, 0xe0, 0xe4,
66 0xe8, 0xec, 0xf0
70 0x4, 0x8, 0xc, 0x10, 0x14,
71 0x18, 0x1c, 0x20, 0x24, 0x34,
72 0x38, 0x3c, 0x40, 0x44, 0x48,
73 0x4c, 0x54
77 0xa0, 0xa4, 0xa8, 0xac, 0xb0,
78 0xb4, 0xbc, 0xc0, 0xc8, 0xcc,
79 0xd0, 0xf0, 0xf4, 0xf8
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Domap-secure.h16 #define API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR 0xFFFFFFFE
17 #define API_HAL_RET_VALUE_SERVICE_UNKNWON 0xFFFFFFFF
20 #define API_HAL_RET_VALUE_OK 0x00
21 #define API_HAL_RET_VALUE_FAIL 0x01
24 #define FLAG_START_CRITICAL 0x4
25 #define FLAG_IRQFIQ_MASK 0x3
26 #define FLAG_IRQ_ENABLE 0x2
27 #define FLAG_FIQ_ENABLE 0x1
28 #define NO_FLAG 0x0
33 #define OMAP3_SAVE_SECURE_RAM_SZ 0x803F
[all …]
/openbmc/linux/arch/x86/include/asm/
H A Dhpet.h11 #define HPET_ID 0x000
12 #define HPET_PERIOD 0x004
13 #define HPET_CFG 0x010
14 #define HPET_STATUS 0x020
15 #define HPET_COUNTER 0x0f0
17 #define HPET_Tn_CFG(n) (0x100 + 0x20 * n)
18 #define HPET_Tn_CMP(n) (0x108 + 0x20 * n)
19 #define HPET_Tn_ROUTE(n) (0x110 + 0x20 * n)
21 #define HPET_T0_CFG 0x100
22 #define HPET_T0_CMP 0x108
[all …]
/openbmc/linux/drivers/media/pci/cx18/
H A Dcx18-av-audio.c60 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in set_audclk_freq()
61 * AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x20 in set_audclk_freq()
63 cx18_av_write4(cx, 0x108, 0x200d040f); in set_audclk_freq()
65 /* VID_PLL Fraction = 0x2be2fe */ in set_audclk_freq()
66 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
67 cx18_av_write4(cx, 0x10c, 0x002be2fe); in set_audclk_freq()
69 /* AUX_PLL Fraction = 0x176740c */ in set_audclk_freq()
70 /* xtal * 0xd.bb3a060/0x20 = 32000 * 384: 393 MHz p-pd*/ in set_audclk_freq()
71 cx18_av_write4(cx, 0x110, 0x0176740c); in set_audclk_freq()
74 /* 0x1.f77f = (4 * xtal/8*2/455) / 32000 */ in set_audclk_freq()
[all …]
/openbmc/openbmc/meta-google/dynamic-layers/nuvoton-layer/recipes-bsp/images/npcm7xx-igps/
H A D0001-Set-FIU0_DRD_CFG-and-FIU_Clk_divider-for-gbmc-hoth.patch21 <offset>0x108</offset>
22 <size>0x4</size>
24 - <content format='32bit'>0x030011BB</content> <!-- content the user should fill -->
25 + <content format='32bit'>0x0300100B</content> <!-- content the user should fill -->
30 <offset>0x10C</offset>
31 <size>0x1</size>
43 <offset>0x108</offset> <!-- offset in the header -->
44 <size>0x4</size> <!-- size in the header -->
46 - <content format='32bit'>0x030111BC</content> <!-- content the user should fill 0x0…
47 + <content format='32bit'>0x0300100B</content> <!-- content the user should fill 0x0…
/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-pcie-qhp.h10 #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14
11 #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20
12 #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24
13 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28
14 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c
15 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34
16 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38
17 #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54
18 #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58
19 #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c
[all …]
H A Dphy-qcom-qmp-qserdes-txrx.h10 #define QSERDES_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_TX_BIST_INVERT 0x004
12 #define QSERDES_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_TX_CMN_CONTROL_ONE 0x00c
14 #define QSERDES_TX_CMN_CONTROL_TWO 0x010
15 #define QSERDES_TX_CMN_CONTROL_THREE 0x014
16 #define QSERDES_TX_TX_EMP_POST1_LVL 0x018
17 #define QSERDES_TX_TX_POST2_EMPH 0x01c
18 #define QSERDES_TX_TX_BOOST_LVL_UP_DN 0x020
19 #define QSERDES_TX_HP_PD_ENABLES 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v4.h10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v5.h11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
12 #define QSERDES_V5_TX_BIST_INVERT 0x004
13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014
17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
20 #define QSERDES_V5_TX_TX_BAND 0x024
[all …]
H A Dphy-qcom-qmp-pcs-pcie-v4_20.h9 #define QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
10 #define QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
11 #define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0
12 #define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0
13 #define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4
14 #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc
15 #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
16 #define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824
17 #define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828
H A Dphy-qcom-qmp-pcs-pcie-v6_20.h10 #define QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2 0x00c
11 #define QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG 0x018
12 #define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE 0x01c
13 #define QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS 0x090
14 #define QPHY_PCIE_V6_20_PCS_EQ_CONFIG1 0x0a0
15 #define QPHY_PCIE_V6_20_PCS_EQ_CONFIG5 0x108
16 #define QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN 0x15c
17 #define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1 0x17c
18 #define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3 0x184
19 #define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5 0x18c
[all …]
H A Dphy-qcom-qmp-pcs-pcie-v5_20.h10 #define QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2 0x00c
11 #define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
12 #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084
13 #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
14 #define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0
15 #define QPHY_V5_20_PCS_PCIE_PRESET_P10_POST 0x0e0
16 #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc
17 #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
18 #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c
19 #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184
[all …]
/openbmc/linux/drivers/media/i2c/cx25840/
H A Dcx25840-audio.c39 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in cx25840_set_audclk_freq()
40 * AUX_PLL Integer = 0x06, AUX PLL Post Divider = 0x10 in cx25840_set_audclk_freq()
42 cx25840_write4(client, 0x108, 0x1006040f); in cx25840_set_audclk_freq()
45 * VID_PLL Fraction (register 0x10c) = 0x2be2fe in cx25840_set_audclk_freq()
46 * 28636360 * 0xf.15f17f0/4 = 108 MHz in cx25840_set_audclk_freq()
51 * AUX_PLL Fraction = 0x1bb39ee in cx25840_set_audclk_freq()
52 * 28636363 * 0x6.dd9cf70/0x10 = 32000 * 384 in cx25840_set_audclk_freq()
57 cx25840_write4(client, 0x110, 0x01bb39ee); in cx25840_set_audclk_freq()
61 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider in cx25840_set_audclk_freq()
63 cx25840_write(client, 0x127, 0x50); in cx25840_set_audclk_freq()
[all …]
/openbmc/linux/drivers/clk/renesas/
H A Dclk-sh73a0.c23 #define CPG_FRQCRA 0x00
24 #define CPG_FRQCRB 0x04
25 #define CPG_SD0CKCR 0x74
26 #define CPG_SD1CKCR 0x78
27 #define CPG_SD2CKCR 0x7c
28 #define CPG_PLLECR 0xd0
29 #define CPG_PLL0CR 0xd8
30 #define CPG_PLL1CR 0x28
31 #define CPG_PLL2CR 0x2c
32 #define CPG_PLL3CR 0xdc
[all …]
/openbmc/qemu/hw/misc/
H A Darm_l2x0.c30 #define CACHE_ID 0x410000c8
69 offset &= 0xfff; in l2x0_priv_read()
70 if (offset >= 0x730 && offset < 0x800) { in l2x0_priv_read()
71 return 0; /* cache ops complete */ in l2x0_priv_read()
74 case 0: in l2x0_priv_read()
76 case 0x4: in l2x0_priv_read()
81 case 0x100: in l2x0_priv_read()
83 case 0x104: in l2x0_priv_read()
85 case 0x108: in l2x0_priv_read()
87 case 0x10C: in l2x0_priv_read()
[all …]
/openbmc/linux/arch/arm/mach-s3c/
H A Dregs-sys-s3c64xx.h16 #define S3C64XX_AHB_CON0 S3C_SYSREG(0x100)
17 #define S3C64XX_AHB_CON1 S3C_SYSREG(0x104)
18 #define S3C64XX_AHB_CON2 S3C_SYSREG(0x108)
20 #define S3C64XX_SDMA_SEL S3C_SYSREG(0x110)
22 #define S3C64XX_OTHERS S3C_SYSREG(0x900)
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91_pdc.h10 u32 rpr; /* 0x100 Receive Pointer Register */
11 u32 rcr; /* 0x104 Receive Counter Register */
12 u32 tpr; /* 0x108 Transmit Pointer Register */
13 u32 tcr; /* 0x10C Transmit Counter Register */
14 u32 pnpr; /* 0x110 Receive Next Pointer Register */
15 u32 pncr; /* 0x114 Receive Next Counter Register */
16 u32 tnpr; /* 0x118 Transmit Next Pointer Register */
17 u32 tncr; /* 0x11C Transmit Next Counter Register */
18 u32 ptcr; /* 0x120 Transfer Control Register */
19 u32 ptsr; /* 0x124 Transfer Status Register */
/openbmc/qemu/include/hw/i2c/
H A Dmicrobit_i2c.h18 #define NRF51_TWI_TASK_STARTRX 0x000
19 #define NRF51_TWI_TASK_STARTTX 0x008
20 #define NRF51_TWI_TASK_STOP 0x014
21 #define NRF51_TWI_EVENT_STOPPED 0x104
22 #define NRF51_TWI_EVENT_RXDREADY 0x108
23 #define NRF51_TWI_EVENT_TXDSENT 0x11c
24 #define NRF51_TWI_REG_ENABLE 0x500
25 #define NRF51_TWI_REG_RXD 0x518
26 #define NRF51_TWI_REG_TXD 0x51c
27 #define NRF51_TWI_REG_ADDRESS 0x588
/openbmc/linux/tools/perf/pmu-events/arch/arm64/ampere/emag/
H A Dpipeline.json4 "EventCode": "0x108",
10 "EventCode": "0x109",
16 "EventCode": "0x10a",
22 "EventCode": "0x10b",
28 "EventCode": "0x10c",
34 "EventCode": "0x10d",
40 "EventCode": "0x10e",
46 "EventCode": "0x10f",
/openbmc/u-boot/arch/arc/cpu/arcv1/
H A Divt.S10 j _start /* 0 - 0x000 */
11 j memory_error /* 1 - 0x008 */
12 j instruction_error /* 2 - 0x010 */
16 j interrupt_handler /* 3:31 - 0x018:0xF8 */
19 j EV_MachineCheck /* 0x100, Fatal Machine check (0x20) */
20 j EV_TLBMissI /* 0x108, Intruction TLB miss (0x21) */
21 j EV_TLBMissD /* 0x110, Data TLB miss (0x22) */
22 j EV_TLBProtV /* 0x118, Protection Violation (0x23)
24 j EV_PrivilegeV /* 0x120, Privilege Violation (0x24) */
25 j EV_Trap /* 0x128, Trap exception (0x25) */
[all …]
/openbmc/linux/drivers/mmc/host/
H A Dsdhci_f_sdh30.h11 #define F_SDH30_AHB_CONFIG 0x100
18 #define F_SDH30_AHB_INCR_4 BIT(0)
20 #define F_SDH30_TUNING_SETTING 0x108
23 #define F_SDH30_IO_CONTROL2 0x114
27 #define F_SDH30_ESD_CONTROL 0x124
32 #define F_SDH30_TEST 0x158
/openbmc/linux/drivers/media/platform/amphion/
H A Dvpu_imx8q.c20 #define IMX8Q_CSR_CM0Px_ADDR_OFFSET 0x00000000
21 #define IMX8Q_CSR_CM0Px_CPUWAIT 0x00000004
27 #define VPU_DISABLE_BITS 0x7
29 #define VPU_ENCODER_MASK 0x1
30 #define VPU_DECODER_MASK 0x3UL
31 #define VPU_DECODER_H264_MASK 0x2UL
32 #define VPU_DECODER_HEVC_MASK 0x1UL
46 vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_CLOCK_ENABLE_SET, 0x1f); in vpu_imx8q_setup_dec()
47 vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_RESET_SET, 0xffffffff); in vpu_imx8q_setup_dec()
49 return 0; in vpu_imx8q_setup_dec()
[all …]

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