125ad4a4cSDmitry Baryshkov /* SPDX-License-Identifier: GPL-2.0 */ 225ad4a4cSDmitry Baryshkov /* 325ad4a4cSDmitry Baryshkov * Copyright (c) 2017, The Linux Foundation. All rights reserved. 425ad4a4cSDmitry Baryshkov */ 525ad4a4cSDmitry Baryshkov 625ad4a4cSDmitry Baryshkov #ifndef QCOM_PHY_QMP_PCS_PCIE_V5_20_H_ 725ad4a4cSDmitry Baryshkov #define QCOM_PHY_QMP_PCS_PCIE_V5_20_H_ 825ad4a4cSDmitry Baryshkov 925ad4a4cSDmitry Baryshkov /* Only for QMP V5_20 PHY - PCIe PCS registers */ 10*a05b6d51SMrinmay Sarkar #define QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2 0x00c 1125ad4a4cSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c 12f5682f13SDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084 1325ad4a4cSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 1425ad4a4cSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0 159ddcd920SManivannan Sadhasivam #define QPHY_V5_20_PCS_PCIE_PRESET_P10_POST 0x0e0 1692bd868fSRohit Agarwal #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc 1725ad4a4cSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 1825ad4a4cSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c 1925ad4a4cSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184 2092bd868fSRohit Agarwal #define QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2 0xa24 2192bd868fSRohit Agarwal #define QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2 0xa28 2225ad4a4cSDmitry Baryshkov 2325ad4a4cSDmitry Baryshkov #endif 24