Searched defs:pll_regs (Results 1 – 11 of 11) sorted by relevance
114 struct pll_regs { struct115 u32 cscr; /* Clock Source Control Register */116 u32 mpctl0; /* MCU PLL Control Register 0 */117 u32 mpctl1; /* MCU PLL Control Register 1 */118 u32 spctl0; /* System PLL Control Register 0 */119 u32 spctl1; /* System PLL Control Register 1 */120 u32 osc26mctl; /* Oscillator 26M Register */121 u32 pcdr0; /* Peripheral Clock Divider Register 0 */122 u32 pcdr1; /* Peripheral Clock Divider Register 1 */123 u32 pccr0; /* Peripheral Clock Control Register 0 */[all …]
1065 static const u32 pll_regs[] = { variable
1316 static const u32 pll_regs[] = { variable
1160 static const u32 pll_regs[] = { variable
107 void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE, in ar934x_pll_init() local
46 uint8_t pll_regs[6]; member
1256 uint8_t pll_regs[5]; in adau1373_set_pll() local
140 const struct cpu_dfs_regs *pll_regs; member
347 __be16 pll_regs[] = { in ar0521_pll_config() local
936 struct sensor_register pll_regs[] = { in ov2659_set_pixel_clock() local
3071 u8 pll_regs[16]; in atyfb_setup_sparc() local