| /openbmc/u-boot/board/micronas/vct/vctv/ |
| H A D | reg_ebi.h | 16 #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) argument
18 #define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) argument
20 #define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS) argument
22 #define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS) argument
24 #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) argument
26 #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) argument
28 #define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS) argument
30 #define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) argument
32 #define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) argument
34 #define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) argument
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| H A D | reg_gpio.h | 14 #define GPIO_SWPORTA_DR(base) ((base) + GPIO_SWPORTA_DR_OFFS) argument
16 #define GPIO_SWPORTA_DDR(base) ((base) + GPIO_SWPORTA_DDR_OFFS) argument
18 #define GPIO_EXT_PORTA(base) ((base) + GPIO_EXT_PORTA_OFFS) argument
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| /openbmc/u-boot/board/micronas/vct/vcth2/ |
| H A D | reg_ebi.h | 16 #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) argument
18 #define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) argument
20 #define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS) argument
22 #define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS) argument
24 #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) argument
26 #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) argument
28 #define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS) argument
30 #define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) argument
32 #define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) argument
34 #define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) argument
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| /openbmc/u-boot/board/micronas/vct/vcth/ |
| H A D | reg_ebi.h | 16 #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) argument
18 #define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) argument
20 #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) argument
22 #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) argument
24 #define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) argument
26 #define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) argument
28 #define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) argument
30 #define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS) argument
32 #define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS) argument
34 #define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS) argument
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| H A D | reg_fwsram.h | 21 #define FWSRAM_SR_ADDR_OFFSET(base) ((base) + FWSRAM_SR_ADDR_OFFSET_OFFS) argument
23 #define FWSRAM_TOP_BOOT_LOG(base) ((base) + FWSRAM_TOP_BOOT_LOG_OFFS) argument
25 #define FWSRAM_TOP_ROM_KBIST(base) ((base) + FWSRAM_TOP_ROM_KBIST_OFFS) argument
27 #define FWSRAM_TOP_CID1_H(base) ((base) + FWSRAM_TOP_CID1_H_OFFS) argument
29 #define FWSRAM_TOP_CID1_L(base) ((base) + FWSRAM_TOP_CID1_L_OFFS) argument
31 #define FWSRAM_TOP_CID2_H(base) ((base) + FWSRAM_TOP_CID2_H_OFFS) argument
33 #define FWSRAM_TOP_CID2_L(base) ((base) + FWSRAM_TOP_CID2_L_OFFS) argument
35 #define FWSRAM_TOP_TDO_CFG(base) ((base) + FWSRAM_TOP_TDO_CFG_OFFS) argument
37 #define FWSRAM_TOP_GPIO2_0_CFG(base) ((base) + FWSRAM_TOP_GPIO2_0_CFG_OFFS) argument
39 #define FWSRAM_TOP_GPIO2_1_CFG(base) ((base) + FWSRAM_TOP_GPIO2_1_CFG_OFFS) argument
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| H A D | reg_scc.h | 56 #define SCC_ENABLE(base) ((base) + SCC_ENABLE_OFFS) argument
58 #define SCC_RESET(base) ((base) + SCC_RESET_OFFS) argument
60 #define SCC_VCID(base) ((base) + SCC_VCID_OFFS) argument
62 #define SCC_MCI_CFG(base) ((base) + SCC_MCI_CFG_OFFS) argument
64 #define SCC_PACKET_CFG1(base) ((base) + SCC_PACKET_CFG1_OFFS) argument
66 #define SCC_PACKET_CFG2(base) ((base) + SCC_PACKET_CFG2_OFFS) argument
68 #define SCC_PACKET_CFG3(base) ((base) + SCC_PACKET_CFG3_OFFS) argument
70 #define SCC_DMA_CFG(base) ((base) + SCC_DMA_CFG_OFFS) argument
72 #define SCC_CMD(base) ((base) + SCC_CMD_OFFS) argument
74 #define SCC_PRIO(base) ((base) + SCC_PRIO_OFFS) argument
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| H A D | reg_usbh.h | 11 #define USBH_CAPLENGTH(base) ((base) + USBH_CAPLENGTH_OFFS) argument
13 #define USBH_USBCMD(base) ((base) + USBH_USBCMD_OFFS) argument
15 #define USBH_BURSTSIZE(base) ((base) + USBH_BURSTSIZE_OFFS) argument
17 #define USBH_USBMODE(base) ((base) + USBH_USBMODE_OFFS) argument
19 #define USBH_USBHMISC(base) ((base) + USBH_USBHMISC_OFFS) argument
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| H A D | reg_dcgu.h | 11 #define DCGU_CLK_EN1(base) ((base) + DCGU_CLK_EN1_OFFS) argument
13 #define DCGU_CLK_EN2(base) ((base) + DCGU_CLK_EN2_OFFS) argument
15 #define DCGU_RESET_UNIT1(base) ((base) + DCGU_RESET_UNIT1_OFFS) argument
17 #define DCGU_USBPHY_STAT(base) ((base) + DCGU_USBPHY_STAT_OFFS) argument
19 #define DCGU_EN_WDT_RESET(base) ((base) + DCGU_EN_WDT_RESET_OFFS) argument
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| H A D | reg_gpio.h | 14 #define GPIO_SWPORTA_DR(base) ((base) + GPIO_SWPORTA_DR_OFFS) argument
16 #define GPIO_SWPORTA_DDR(base) ((base) + GPIO_SWPORTA_DDR_OFFS) argument
18 #define GPIO_EXT_PORTA(base) ((base) + GPIO_EXT_PORTA_OFFS) argument
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| /openbmc/u-boot/arch/arm/mach-keystone/ |
| H A D | ddr3.c | 24 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) in ddr3_init_ddrphy()
101 void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg) in ddr3_init_ddremif()
112 int ddr3_ecc_support_rmw(u32 base) in ddr3_ecc_support_rmw()
124 static void ddr3_ecc_config(u32 base, u32 value) in ddr3_ecc_config()
148 static void ddr3_reset_data(u32 base, u32 ddr3_size) in ddr3_reset_data()
238 static void ddr3_ecc_init_range(u32 base) in ddr3_ecc_init_range()
251 void ddr3_enable_ecc(u32 base, int test) in ddr3_enable_ecc()
271 void ddr3_disable_ecc(u32 base) in ddr3_disable_ecc()
277 static void cic_init(u32 base) in cic_init()
290 static void cic_map_cic_to_gic(u32 base, u32 chan_num, u32 irq_num) in cic_map_cic_to_gic()
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| /openbmc/u-boot/drivers/serial/ |
| H A D | serial_mvebu_a3700.c | 12 void __iomem *base; member
36 void __iomem *base = plat->base; in mvebu_serial_putc() local
49 void __iomem *base = plat->base; in mvebu_serial_getc() local
60 void __iomem *base = plat->base; in mvebu_serial_pending() local
71 void __iomem *base = plat->base; in mvebu_serial_setbrg() local
91 void __iomem *base = plat->base; in mvebu_serial_probe() local
140 void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; in _debug_uart_init() local
164 void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; in _debug_uart_putc() local
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| H A D | serial_stm32.c | 17 static void _stm32_serial_setbrg(fdt_addr_t base, in _stm32_serial_setbrg()
103 fdt_addr_t base = plat->base; in stm32_serial_getc() local
121 static int _stm32_serial_putc(fdt_addr_t base, in _stm32_serial_putc()
146 fdt_addr_t base = plat->base; in stm32_serial_pending() local
156 static void _stm32_serial_init(fdt_addr_t base, in _stm32_serial_init()
265 fdt_addr_t base = CONFIG_DEBUG_UART_BASE; in _debug_uart_init() local
277 fdt_addr_t base = CONFIG_DEBUG_UART_BASE; in _debug_uart_putc() local
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| /openbmc/qemu/hw/m68k/ |
| H A D | bootinfo.h | 15 #define BOOTINFO0(base, id) \ argument
23 #define BOOTINFO1(base, id, value) \ argument
33 #define BOOTINFO2(base, id, value1, value2) \ argument
45 #define BOOTINFOSTR(base, id, string) \ argument
60 #define BOOTINFODATA(base, id, data, len) \ argument
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| /openbmc/u-boot/drivers/bios_emulator/ |
| H A D | biosemui.h | 67 #define readb_le(base) *((u8*)(base)) argument
68 #define readw_le(base) ((u16)readb_le(base) | ((u16)readb_le((base) + 1) << 8)) argument
69 #define readl_le(base) ((u32)readb_le((base) + 0) | ((u32)readb_le((base) + 1) << 8) | \ argument
71 #define writeb_le(base, v) *((u8*)(base)) = (v) argument
72 #define writew_le(base, v) writeb_le(base + 0, (v >> 0) & 0xff), \ argument
74 #define writel_le(base, v) writeb_le(base + 0, (v >> 0) & 0xff), \ argument
79 #define readb_le(base) *((u8*)(base)) argument
80 #define readw_le(base) *((u16*)(base)) argument
81 #define readl_le(base) *((u32*)(base)) argument
82 #define writeb_le(base, v) *((u8*)(base)) = (v) argument
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| /openbmc/u-boot/lib/ |
| H A D | strto.c | 17 static const char *_parse_integer_fixup_radix(const char *s, unsigned int *base) in _parse_integer_fixup_radix()
34 unsigned int base) in simple_strtoul()
53 int strict_strtoul(const char *cp, unsigned int base, unsigned long *res) in strict_strtoul()
77 long simple_strtol(const char *cp, char **endp, unsigned int base) in simple_strtol()
85 unsigned long ustrtoul(const char *cp, char **endp, unsigned int base) in ustrtoul()
106 unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base) in ustrtoull()
128 unsigned int base) in simple_strtoull()
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| /openbmc/u-boot/arch/arm/mach-omap2/ |
| H A D | emif-common.c | 23 void set_lpmode_selfrefresh(u32 base) in set_lpmode_selfrefresh()
45 inline u32 emif_num(u32 base) in emif_num()
55 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr) in get_mr()
76 static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val) in set_mr()
85 void emif_reset_phy(u32 base) in emif_reset_phy()
95 static void do_lpddr2_init(u32 base, u32 cs) in do_lpddr2_init()
126 static void lpddr2_init(u32 base, const struct emif_regs *regs) in lpddr2_init()
160 __weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs) in do_ext_phy_settings()
164 void emif_update_timings(u32 base, const struct emif_regs *regs) in emif_update_timings()
201 static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs) in omap5_ddr3_leveling()
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| /openbmc/webui-vue/tests/unit/ |
| H A D | i18n.locale-alias.spec.js | 7 const base = require('@/locales/en-US.json'); constant
15 const base = require('@/locales/en-US.json'); constant
23 const base = require('@/locales/ka-GE.json'); constant
31 const base = require('@/locales/ka-GE.json'); constant
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| /openbmc/u-boot/arch/arm/mach-uniphier/clk/ |
| H A D | pll-base-ld20.c | 34 void __iomem *base; in uniphier_ld20_sscpll_init() local
70 void __iomem *base; in uniphier_ld20_sscpll_ssc_en() local
88 void __iomem *base; in uniphier_ld20_sscpll_set_regi() local
107 void __iomem *base; in uniphier_ld20_vpll27_init() local
133 void __iomem *base; in uniphier_ld20_dspll_init() local
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| /openbmc/u-boot/drivers/i2c/ |
| H A D | fsl_i2c.c | 119 static uint set_i2c_bus_speed(const struct fsl_i2c_base *base, in set_i2c_bus_speed()
212 static int fsl_i2c_fixup(const struct fsl_i2c_base *base) in fsl_i2c_fixup()
260 static void __i2c_init(const struct fsl_i2c_base *base, int speed, int in __i2c_init()
293 static int i2c_wait4bus(const struct fsl_i2c_base *base) in i2c_wait4bus()
306 static int i2c_wait(const struct fsl_i2c_base *base, int write) in i2c_wait()
343 static int i2c_write_addr(const struct fsl_i2c_base *base, u8 dev, in i2c_write_addr()
358 static int __i2c_write_data(const struct fsl_i2c_base *base, u8 *data, in __i2c_write_data()
373 static int __i2c_read_data(const struct fsl_i2c_base *base, u8 *data, in __i2c_read_data()
404 static int __i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, in __i2c_read()
451 static int __i2c_write(const struct fsl_i2c_base *base, u8 chip_addr, in __i2c_write()
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| /openbmc/qemu/tests/qtest/ |
| H A D | aspeed-hace-utils.c | 156 static void write_regs(QTestState *s, uint32_t base, uint64_t src, in write_regs()
167 void aspeed_test_md5(const char *machine, const uint32_t base, in aspeed_test_md5()
202 void aspeed_test_sha256(const char *machine, const uint32_t base, in aspeed_test_sha256()
236 void aspeed_test_sha384(const char *machine, const uint32_t base, in aspeed_test_sha384()
270 void aspeed_test_sha512(const char *machine, const uint32_t base, in aspeed_test_sha512()
304 void aspeed_test_sha256_sg(const char *machine, const uint32_t base, in aspeed_test_sha256_sg()
355 void aspeed_test_sha384_sg(const char *machine, const uint32_t base, in aspeed_test_sha384_sg()
406 void aspeed_test_sha512_sg(const char *machine, const uint32_t base, in aspeed_test_sha512_sg()
457 void aspeed_test_sha256_accum(const char *machine, const uint32_t base, in aspeed_test_sha256_accum()
498 void aspeed_test_sha384_accum(const char *machine, const uint32_t base, in aspeed_test_sha384_accum()
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| /openbmc/u-boot/arch/arm/cpu/armv7/kona-common/ |
| H A D | clk-stubs.c | 12 int __weak clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep) in clk_sdio_enable()
17 int __weak clk_bsc_enable(void *base, u32 rate, u32 *actual_ratep) in clk_bsc_enable()
22 int __weak clk_usb_otg_enable(void *base) in clk_usb_otg_enable()
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| /openbmc/u-boot/drivers/net/ |
| H A D | ne2000_base.c | 107 u8* base; in dp83902a_init() local
147 u8 *base = dp->base; in dp83902a_stop() local
168 u8 *base = dp->base; in dp83902a_start() local
219 u8 *base = dp->base; in dp83902a_start_xmit() local
247 u8 *base = dp->base; in dp83902a_send() local
377 u8 *base = dp->base; in dp83902a_RxEvent() local
449 u8 *base = dp->base; in dp83902a_recv() local
514 u8 *base = dp->base; in dp83902a_TxEvent() local
551 u8 *base = dp->base; in dp83902a_ClearCounters() local
568 u8 *base = dp->base; in dp83902a_Overflow() local
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| /openbmc/u-boot/drivers/dma/ |
| H A D | ti-edma3.c | 39 u32 base; member
54 void qedma3_start(u32 base, struct edma3_channel_config *cfg) in qedma3_start()
91 void edma3_set_dest(u32 base, int slot, u32 dst, enum edma3_address_mode mode, in edma3_set_dest()
122 void edma3_set_dest_index(u32 base, unsigned slot, int bidx, int cidx) in edma3_set_dest_index()
142 void edma3_set_dest_addr(u32 base, int slot, u32 dst) in edma3_set_dest_addr()
162 void edma3_set_src(u32 base, int slot, u32 src, enum edma3_address_mode mode, in edma3_set_src()
193 void edma3_set_src_index(u32 base, unsigned slot, int bidx, int cidx) in edma3_set_src_index()
213 void edma3_set_src_addr(u32 base, int slot, u32 src) in edma3_set_src_addr()
251 void edma3_set_transfer_params(u32 base, int slot, int acnt, in edma3_set_transfer_params()
288 void edma3_write_slot(u32 base, int slot, struct edma3_slot_layout *param) in edma3_write_slot()
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| /openbmc/qemu/target/i386/tcg/ |
| H A D | mpx_helper.c | 36 static uint64_t lookup_bte64(CPUX86State *env, uint64_t base, uintptr_t ra) in lookup_bte64()
56 static uint32_t lookup_bte32(CPUX86State *env, uint32_t base, uintptr_t ra) in lookup_bte32()
76 uint64_t helper_bndldx64(CPUX86State *env, target_ulong base, target_ulong ptr) in helper_bndldx64()
93 uint64_t helper_bndldx32(CPUX86State *env, target_ulong base, target_ulong ptr) in helper_bndldx32()
109 void helper_bndstx64(CPUX86State *env, target_ulong base, target_ulong ptr, in helper_bndstx64()
121 void helper_bndstx32(CPUX86State *env, target_ulong base, target_ulong ptr, in helper_bndstx32()
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| /openbmc/u-boot/arch/arm/mach-mvebu/ |
| H A D | mbus.c | 108 int win, int *enabled, u64 *base, in mvebu_mbus_read_window()
174 phys_addr_t base, size_t size, in mvebu_mbus_window_conflicts()
213 phys_addr_t base, size_t size) in mvebu_mbus_find_window()
237 int win, phys_addr_t base, size_t size, in mvebu_mbus_setup_window()
265 phys_addr_t base, size_t size, in mvebu_mbus_alloc_window()
326 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); in mvebu_mbus_default_setup_cpu_target() local
375 phys_addr_t base, size_t size, in mvebu_mbus_add_window_remap_by_id()
390 phys_addr_t base, size_t size) in mvebu_mbus_add_window_by_id()
396 int mvebu_mbus_del_window(phys_addr_t base, size_t size) in mvebu_mbus_del_window()
409 phys_addr_t *base) in mvebu_mbus_get_lowest_base()
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