| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | clk-mt8167-apmixedsys.c | 22 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
42 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
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| H A D | clk-mt2712-apmixedsys.c | 21 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
44 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
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| H A D | clk-mt7622-apmixedsys.c | 20 #define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\ argument
41 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
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| H A D | clk-mt8365-apmixedsys.c | 19 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
45 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
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| H A D | clk-mt6795-topckgen.c | 21 #define TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ argument
26 #define TOP_MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ argument
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| H A D | clk-mt8173-apmixedsys.c | 24 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
44 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
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| H A D | clk-mt8173-topckgen.c | 22 #define TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ argument
27 #define TOP_MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ argument
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| H A D | clk-mt8192-apmixedsys.c | 35 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ argument
63 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ argument
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| /openbmc/linux/drivers/clk/sunxi-ng/ |
| H A D | ccu_nkm.h | 39 _gate, _lock, _flags) \ argument
60 _gate, _lock, _flags) \ argument
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| H A D | ccu_phase.h | 20 #define SUNXI_CCU_PHASE(_struct, _name, _parent, _reg, _shift, _width, _flags) \ argument
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| /openbmc/linux/include/linux/ |
| H A D | sh_clk.h | 117 #define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _status_reg, _flags) \ argument
151 #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \ argument
175 #define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \ argument
188 #define SH_CLK_DIV6(_parent, _reg, _flags) \ argument
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| H A D | clk-provider.h | 1406 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ argument
1415 #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \ argument
1429 #define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \ argument
1438 #define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \ argument
1449 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ argument
1458 #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \ argument
1467 #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \ argument
1476 #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \ argument
1486 _div, _mult, _flags) \ argument
1497 _div, _mult, _flags) \ argument
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| /openbmc/linux/drivers/gpu/drm/ |
| H A D | drm_ioctl.c | 554 #define DRM_IOCTL_DEF(ioctl, _func, _flags) \ argument
563 #define DRM_LEGACY_IOCTL_DEF(ioctl, _func, _flags) DRM_IOCTL_DEF(ioctl, _func, _flags) argument
565 #define DRM_LEGACY_IOCTL_DEF(ioctl, _func, _flags) DRM_IOCTL_DEF(ioctl, drm_invalid_op, _flags) argument
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| /openbmc/linux/drivers/net/wireless/silabs/wfx/ |
| H A D | main.c | 43 #define RATETAB_ENT(_rate, _rateid, _flags) { \ argument
64 #define CHAN2G(_channel, _freq, _flags) { \ argument
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| /openbmc/u-boot/include/test/ |
| H A D | compression.h | 13 #define COMPRESSION_TEST(_name, _flags) \ argument
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| H A D | lib.h | 12 #define LIB_TEST(_name, _flags) UNIT_TEST(_name, _flags, lib_test) argument
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| H A D | env.h | 13 #define ENV_TEST(_name, _flags) UNIT_TEST(_name, _flags, env_test) argument
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| H A D | overlay.h | 13 #define OVERLAY_TEST(_name, _flags) UNIT_TEST(_name, _flags, overlay_test) argument
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| /openbmc/linux/drivers/clk/actions/ |
| H A D | owl-fixed-factor.h | 16 #define OWL_FIX_FACT(_struct, _name, _parent, _mul, _div, _flags) \ argument
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| /openbmc/linux/drivers/clk/microchip/ |
| H A D | clk-mpfs-ccc.c | 101 #define CLK_CCC_PLL(_id, _parents, _shift, _width, _flags, _offset) { \ argument
124 #define CLK_CCC_OUT(_id, _shift, _width, _flags, _offset) { \ argument
187 #define CLK_HW_INIT_PARENTS_DATA_FIXED_SIZE(_name, _parents, _ops, _flags) \ argument
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| /openbmc/phosphor-logging/extensions/openpower-pels/ |
| H A D | pce_identity.hpp | 107 uint8_t _flags; member in openpower::pels::src::PCEIdentity
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| H A D | mru.hpp | 136 uint8_t _flags; member in openpower::pels::src::MRU
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| /openbmc/openpower-hw-diags/attn/pel/ |
| H A D | primary_src.hpp | 118 uint8_t _flags = 0; member in attn::pel::PrimarySrc
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| /openbmc/linux/drivers/net/ethernet/fungible/funcore/ |
| H A D | fun_hci.h | 39 #define FUN_ADMIN_REQ_COMMON_INIT(_op, _len8, _flags, _suboff8, _cid) \ argument
157 #define FUN_ADMIN_SIMPLE_SUBOP_INIT(_subop, _flags, _data) \ argument
254 _subop, _flags, _id, _epsqid, _entry_size_log2, _nentries, _address, \ argument
274 #define FUN_ADMIN_EPCQ_MODIFY_REQ_INIT(_subop, _flags, _id, _headroom) \ argument
329 _subop, _flags, _id, _epcqid, _entry_size_log2, _nentries, _address, \ argument
533 #define FUN_SUBOP_SGL_INIT(_subop, _flags, _nsgl, _sgl_len, _sgl_data) \ argument
557 #define FUN_DATAOP_HDR_INIT(_nsgl, _flags, _ngather, _nscatter, _total_len) \ argument
624 #define FUN_ADMIN_PORT_CREATE_REQ_INIT(_subop, _flags, _id) \ argument
630 #define FUN_ADMIN_PORT_WRITE_REQ_INIT(_subop, _flags, _id) \ argument
636 #define FUN_ADMIN_PORT_READ_REQ_INIT(_subop, _flags, _id) \ argument
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| /openbmc/linux/drivers/clk/ |
| H A D | clk-stm32mp1.c | 1166 #define GATE(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\ argument
1180 #define FIXED_FACTOR(_id, _name, _parent, _flags, _mult, _div)\ argument
1193 #define DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\ argument
1210 #define DIV(_id, _name, _parent, _flags, _offset, _shift, _width, _div_flags)\ argument
1214 #define MUX(_id, _name, _parents, _flags, _offset, _shift, _width, _mux_flags)\ argument
1230 #define PLL(_id, _name, _parents, _flags, _offset_p, _offset_mux)\ argument
1244 #define STM32_CKTIM(_name, _parent, _flags, _offset_apbdiv, _offset_timpre)\ argument
1262 #define STM32_GATE(_id, _name, _parent, _flags, _gate)\ argument
1272 #define STM32_GATE_PDATA(_id, _name, _parent, _flags, _gate)\ argument
1307 #define GATE_MP1(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\ argument
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