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Searched refs:zqcr (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c283 clrsetbits_le32(&mctl_ctl->zqcr, 0xffff, in mctl_h3_zq_calibration_quirk()
311 &mctl_ctl->zqcr); in mctl_h3_zq_calibration_quirk()
512 clrsetbits_le32(&mctl_ctl->zqcr, 0xffffff, CONFIG_DRAM_ZQ); in mctl_channel_init()
518 clrsetbits_le32(&mctl_ctl->zqcr, 0xffffff, CONFIG_DRAM_ZQ); in mctl_channel_init()
576 setbits_le32(&mctl_ctl->zqcr, ZQCR_PWRDOWN); in mctl_channel_init()
H A Ddram_sun50i_h6.c588 clrsetbits_le32(&mctl_phy->zq[0].zqcr, 0x700, val); in mctl_channel_init()
/openbmc/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3188.c713 int zqcr; in sdram_init() local
766 zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT | in sdram_init()
769 writel(zqcr, &publ->zq1cr[0]); in sdram_init()
770 writel(zqcr, &publ->zq0cr[0]); in sdram_init()
H A Dsdram_rk3288.c784 int zqcr; in sdram_init() local
865 zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT | in sdram_init()
868 writel(zqcr, &publ->zq1cr[0]); in sdram_init()
869 writel(zqcr, &publ->zq0cr[0]); in sdram_init()
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddram_sunxi_dw.h119 u32 zqcr; /* 0x140 ZQ control register */ member
H A Ddram_sun50i_h6.h227 u32 zqcr; /* 0x00 only the first one valid */ member