Home
last modified time | relevance | path

Searched refs:write_aux_reg (Results 1 – 16 of 16) sorted by relevance

/openbmc/u-boot/arch/arc/lib/
H A Dcache.c287 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); in __slc_entire_op()
292 write_aux_reg(ARC_AUX_SLC_FLUSH, 0x1); in __slc_entire_op()
315 write_aux_reg(ARC_AUX_SLC_RGN_END1, 0); in slc_upper_region_init()
348 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); in __slc_rgn_op()
362 write_aux_reg(ARC_AUX_SLC_RGN_END, end); in __slc_rgn_op()
401 write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, in arc_ioc_setup()
501 write_aux_reg(ARC_AUX_IC_IVIC, 1); in __ic_entire_invalidate()
577 write_aux_reg(ARC_AUX_DC_PTAG, paddr); in __dcache_line_loop()
579 write_aux_reg(aux_cmd, paddr); in __dcache_line_loop()
596 write_aux_reg(ARC_AUX_DC_CTRL, ctrl); in __before_dc_op()
[all …]
/openbmc/linux/arch/arc/mm/
H A Dtlb.c31 write_aux_reg(ARC_REG_TLBPD1, 0); in __tlb_entry_erase()
34 write_aux_reg(ARC_REG_TLBPD1HI, 0); in __tlb_entry_erase()
36 write_aux_reg(ARC_REG_TLBPD0, 0); in __tlb_entry_erase()
96 write_aux_reg(ARC_REG_TLBPD1, pd1); in tlb_entry_insert()
116 write_aux_reg(ARC_REG_TLBPD0, pd0); in tlb_entry_insert()
119 write_aux_reg(ARC_REG_TLBPD1, pd1); in tlb_entry_insert()
144 write_aux_reg(ARC_REG_TLBPD1, 0); in local_flush_tlb_all()
147 write_aux_reg(ARC_REG_TLBPD1HI, 0); in local_flush_tlb_all()
149 write_aux_reg(ARC_REG_TLBPD0, 0); in local_flush_tlb_all()
720 write_aux_reg(ARC_REG_TLBINDEX, in do_tlb_overlap_fault()
[all …]
H A Dcache.c221 write_aux_reg(aux_tag, paddr); in __cache_line_loop_v3()
235 write_aux_reg(aux_tag, paddr); in __cache_line_loop_v3()
239 write_aux_reg(aux_cmd, vaddr); in __cache_line_loop_v3()
292 write_aux_reg(aux_cmd, paddr); in __cache_line_loop_v4()
339 write_aux_reg(s, paddr); in __cache_line_loop_v4()
396 write_aux_reg(ctl, val); in __before_dc_op()
435 write_aux_reg(aux, 0x1); in __dc_entire_op()
492 write_aux_reg(ARC_REG_IC_IVIC, 1); in __ic_entire_inv()
583 write_aux_reg(ARC_REG_SLC_CTRL, ctrl); in slc_op_rgn()
647 write_aux_reg(cmd, paddr); in slc_op_line()
[all …]
/openbmc/linux/arch/arc/kernel/
H A Dintc-arcv2.c80 write_aux_reg(AUX_IRQ_SELECT, i); in arc_init_IRQ()
81 write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO); in arc_init_IRQ()
89 write_aux_reg(AUX_IRQ_ENABLE, 0); in arc_init_IRQ()
101 write_aux_reg(AUX_IRQ_SELECT, data->hwirq); in arcv2_irq_mask()
102 write_aux_reg(AUX_IRQ_ENABLE, 0); in arcv2_irq_mask()
107 write_aux_reg(AUX_IRQ_SELECT, data->hwirq); in arcv2_irq_unmask()
108 write_aux_reg(AUX_IRQ_ENABLE, 1); in arcv2_irq_unmask()
114 write_aux_reg(AUX_IRQ_SELECT, data->hwirq); in arcv2_irq_enable()
115 write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO); in arcv2_irq_enable()
122 write_aux_reg(AUX_IRQ_ENABLE, 1); in arcv2_irq_enable()
H A Dperf_event.c271 write_aux_reg(ARC_REG_PCT_INDEX, idx); in arc_pmu_read_counter()
435 write_aux_reg(ARC_REG_PCT_INDEX, idx); in arc_pmu_event_set_period()
468 write_aux_reg(ARC_REG_PCT_INT_CTRL, in arc_pmu_start()
488 write_aux_reg(ARC_REG_PCT_INT_CTRL, in arc_pmu_stop()
541 write_aux_reg(ARC_REG_PCT_INT_CNTL, in arc_pmu_add()
543 write_aux_reg(ARC_REG_PCT_INT_CNTH, in arc_pmu_add()
547 write_aux_reg(ARC_REG_PCT_CONFIG, 0); in arc_pmu_add()
548 write_aux_reg(ARC_REG_PCT_COUNTL, 0); in arc_pmu_add()
549 write_aux_reg(ARC_REG_PCT_COUNTH, 0); in arc_pmu_add()
592 write_aux_reg(ARC_REG_PCT_INT_CTRL, in arc_pmu_intr()
[all …]
H A Dfpu.c63 write_aux_reg(ARC_REG_FPU_CTRL, 0x100); in fpu_init_task()
66 write_aux_reg(ARC_REG_FPU_STATUS, fwe); in fpu_init_task()
78 write_aux_reg(ARC_REG_FPU_CTRL, restore->ctrl); in fpu_save_restore()
79 write_aux_reg(ARC_REG_FPU_STATUS, (fwe | restore->status)); in fpu_save_restore()
H A Dintc-compact.c35 write_aux_reg(AUX_IRQ_LEV, level_mask); in arc_init_IRQ()
49 write_aux_reg(AUX_IENABLE, ienb); in arc_init_IRQ()
70 write_aux_reg(AUX_IENABLE, ienb); in arc_irq_mask()
79 write_aux_reg(AUX_IENABLE, ienb); in arc_irq_unmask()
/openbmc/u-boot/drivers/timer/
H A Darc_timer.c75 write_aux_reg(ARC_AUX_TIMER0_CTRL, NH_MODE); in arc_timer_probe()
77 write_aux_reg(ARC_AUX_TIMER0_LIMIT, 0xffffffff); in arc_timer_probe()
79 write_aux_reg(ARC_AUX_TIMER0_CNT, 0); in arc_timer_probe()
83 write_aux_reg(ARC_AUX_TIMER1_CTRL, NH_MODE); in arc_timer_probe()
85 write_aux_reg(ARC_AUX_TIMER1_LIMIT, 0xffffffff); in arc_timer_probe()
87 write_aux_reg(ARC_AUX_TIMER1_CNT, 0); in arc_timer_probe()
/openbmc/linux/drivers/clocksource/
H A Darc_timer.c182 write_aux_reg(AUX_RTC_CTRL, 1); in arc_cs_setup_rtc()
226 write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMERN_MAX); in arc_cs_setup_timer1()
227 write_aux_reg(ARC_REG_TIMER1_CNT, 0); in arc_cs_setup_timer1()
228 write_aux_reg(ARC_REG_TIMER1_CTRL, ARC_TIMER_CTRL_NH); in arc_cs_setup_timer1()
245 write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles); in arc_timer_event_setup()
246 write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */ in arc_timer_event_setup()
248 write_aux_reg(ARC_REG_TIMER0_CTRL, ARC_TIMER_CTRL_IE | ARC_TIMER_CTRL_NH); in arc_timer_event_setup()
297 write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | ARC_TIMER_CTRL_NH); in timer_irq_handler()
/openbmc/linux/include/soc/arc/
H A Daux.h14 #define write_aux_reg(r, v) __builtin_arc_sr((unsigned int)(v), r) macro
27 static inline void write_aux_reg(u32 r, u32 v) in write_aux_reg() function
51 write_aux_reg(reg, tmp); \
H A Dmcip.h119 write_aux_reg(ARC_REG_MCIP_WDATA, data); in __mcip_cmd_data()
/openbmc/linux/arch/arc/include/asm/
H A Dirqflags-arcv2.h83 write_aux_reg(AUX_IRQ_ACT, irqact & ~0xffff); in arch_local_irq_enable()
134 write_aux_reg(AUX_IRQ_HINT, irq); in arc_softirq_trigger()
139 write_aux_reg(AUX_IRQ_HINT, 0); in arc_softirq_clear()
H A Dmmu-arcv2.h82 write_aux_reg(ARC_REG_PID, asid | MMU_ENABLE); in mmu_setup_asid()
89 write_aux_reg(ARC_REG_SCRATCH_DATA0, (unsigned int)pgd); in mmu_setup_pgd()
/openbmc/u-boot/arch/arc/include/asm/
H A Darcregs.h112 #define write_aux_reg(reg_immed, val) \ macro
/openbmc/u-boot/board/synopsys/hsdk/
H A Dhsdk.c196 write_aux_reg(ARC_AUX_ICCM_BASE, val << APERTURE_SHIFT); in init_slave_cpu_func()
201 write_aux_reg(ARC_AUX_DCCM_BASE, val << APERTURE_SHIFT); in init_slave_cpu_func()
219 write_aux_reg(ARC_AUX_NON_VOLATILE_LIMIT, val); in init_cluster_nvlim()
220 write_aux_reg(AUX_AUX_CACHE_LIMIT, val); in init_cluster_nvlim()
/openbmc/u-boot/board/synopsys/iot_devkit/
H A Diot_devkit.c126 write_aux_reg(DEBUG_UART_BASE + DEBUG_UART_DLF_OFFSET, 1); in mach_cpu_init()