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Searched refs:wmask (Results 1 – 25 of 56) sorted by relevance

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/openbmc/qemu/hw/cxl/
H A Dcxl-component-utils.c378 uint8_t *wmask = pdev->wmask; in cxl_component_create_dvsec() local
398 wmask[offset + offsetof(CXLDVSECDevice, ctrl)] = 0xFD; in cxl_component_create_dvsec()
399 wmask[offset + offsetof(CXLDVSECDevice, ctrl) + 1] = 0x4F; in cxl_component_create_dvsec()
401 wmask[offset + offsetof(CXLDVSECDevice, ctrl2)] = 0x0F; in cxl_component_create_dvsec()
403 wmask[offset + offsetof(CXLDVSECDevice, lock)] = 0x01; in cxl_component_create_dvsec()
419 wmask[offset + offsetof(CXLDVSECPortExt, control)] = 0x0F; in cxl_component_create_dvsec()
420 wmask[offset + offsetof(CXLDVSECPortExt, control) + 1] = 0x40; in cxl_component_create_dvsec()
421 wmask[offset + offsetof(CXLDVSECPortExt, alt_bus_base)] = 0xFF; in cxl_component_create_dvsec()
450 wmask[offset + offsetof(CXLDVSECPortGPF, phase1_ctrl)] = 0x0F; in cxl_component_create_dvsec()
452 wmask[offset + offsetof(CXLDVSECPortGPF, phase2_ctrl)] = 0x0F; in cxl_component_create_dvsec()
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/openbmc/qemu/hw/pci/
H A Dpcie_sriov.c33 uint8_t *wmask; in pcie_sriov_pf_init() local
65 wmask = dev->wmask + offset; in pcie_sriov_pf_init()
66 pci_set_word(wmask + PCI_SRIOV_CTRL, in pcie_sriov_pf_init()
68 pci_set_word(wmask + PCI_SRIOV_NUM_VF, 0xffff); in pcie_sriov_pf_init()
69 pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, 0x553); in pcie_sriov_pf_init()
85 uint64_t wmask; in pcie_sriov_pf_init_vf_bar() local
93 wmask = ~(size - 1); in pcie_sriov_pf_init_vf_bar()
99 pci_set_quad(dev->wmask + addr, wmask); in pcie_sriov_pf_init_vf_bar()
102 pci_set_long(dev->wmask + addr, wmask & 0xffffffff); in pcie_sriov_pf_init_vf_bar()
280 uint8_t *wmask = dev->wmask + dev->exp.sriov_cap; in pcie_sriov_pf_add_sup_pgsize() local
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H A Dshpc.c454 uint8_t wmask = shpc->wmask[a]; in shpc_write() local
456 assert(!(wmask & w1cmask)); in shpc_write()
457 shpc->config[a] = (shpc->config[a] & ~wmask) | (val & wmask); in shpc_write()
516 pci_set_byte(d->wmask + config_offset + SHPC_CAP_DWORD_SELECT, 0xff); in shpc_cap_add_config()
670 shpc->wmask = g_malloc0(SHPC_SIZEOF(d)); in shpc_init()
677 pci_set_byte(shpc->wmask + SHPC_CMD_CODE, 0xff); in shpc_init()
678 pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX); in shpc_init()
679 pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX); in shpc_init()
680 pci_set_long(shpc->wmask + SHPC_SERR_INT, in shpc_init()
689 pci_set_byte(shpc->wmask + in shpc_init()
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H A Dpci.c869 dev->wmask[PCI_INTERRUPT_LINE] = 0xff; in pci_init_wmask()
870 pci_set_word(dev->wmask + PCI_COMMAND, in pci_init_wmask()
1020 g_free(pci_dev->wmask); in pci_config_free()
1310 uint64_t wmask; in pci_register_bar() local
1333 wmask = ~(size - 1); in pci_register_bar()
1336 wmask |= PCI_ROM_ADDRESS_ENABLE; in pci_register_bar()
1344 pci_set_quad(pci_dev->wmask + addr, wmask); in pci_register_bar()
1347 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); in pci_register_bar()
1604 uint8_t wmask = d->wmask[addr + i]; in pci_default_write_config() local
1606 assert(!(wmask & w1cmask)); in pci_default_write_config()
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H A Dpcie.c217 pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0); in pcie_cap_init()
333 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL, in pcie_cap_deverr_init()
352 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_LNKCTL, in pcie_cap_lnkctl_init()
667 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, in pcie_cap_slot_init()
677 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, in pcie_cap_slot_init()
689 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, in pcie_cap_slot_init()
898 pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL, in pcie_cap_root_init()
943 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2, in pcie_cap_arifwd_init()
1049 memset(dev->wmask + offset, 0, size); in pcie_add_capability()
1140 pci_set_word(dev->wmask + dev->exp.ats_cap + PCI_ATS_CTRL, 0x800f); in pcie_ats_init()
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H A Dmsi.c237 pci_set_word(dev->wmask + msi_flags_off(dev), in msi_init()
239 pci_set_long(dev->wmask + msi_address_lo_off(dev), in msi_init()
242 pci_set_long(dev->wmask + msi_address_hi_off(dev), 0xffffffff); in msi_init()
244 pci_set_word(dev->wmask + msi_data_off(dev, msi64bit), 0xffff); in msi_init()
248 pci_set_long(dev->wmask + msi_mask_off(dev, msi64bit), in msi_init()
H A Dpcie_aer.c119 pci_set_long(dev->wmask + offset + PCI_ERR_UNCOR_MASK, in pcie_aer_init()
125 pci_set_long(dev->wmask + offset + PCI_ERR_UNCOR_SEVER, in pcie_aer_init()
133 pci_set_long(dev->wmask + offset + PCI_ERR_COR_MASK, in pcie_aer_init()
141 pci_set_long(dev->wmask + offset + PCI_ERR_CAP, in pcie_aer_init()
147 pci_set_long(dev->wmask + offset + PCI_ERR_CAP, in pcie_aer_init()
157 pci_word_test_and_set_mask(dev->wmask + PCI_BRIDGE_CONTROL, in pcie_aer_init()
748 pci_set_long(dev->wmask + pos + PCI_ERR_ROOT_COMMAND, in pcie_aer_root_init()
H A Dslotid_cap.c40 d->wmask[cap + PCI_SID_CHASSIS_NR] = 0xff; in slotid_cap_init()
/openbmc/linux/arch/x86/platform/intel-quark/
H A Dimr.c70 u32 wmask; member
95 imr->wmask == IMR_WRITE_ACCESS_ALL && in imr_is_enabled()
127 return iosf_mbi_read(QRK_MBI_UNIT_MM, MBI_REG_READ, reg++, &imr->wmask); in imr_read()
161 ret = iosf_mbi_write(QRK_MBI_UNIT_MM, MBI_REG_WRITE, reg++, imr->wmask); in imr_write()
221 &base, &end, size, imr.rmask, imr.wmask, in imr_dbgfs_state_show()
299 unsigned int rmask, unsigned int wmask) in imr_add_range() argument
327 imr.wmask = wmask; in imr_add_range()
364 reg, &base, &end, raw_size, rmask, wmask); in imr_add_range()
370 imr.wmask = wmask; in imr_add_range()
382 imr.wmask = IMR_WRITE_ACCESS_ALL; in imr_add_range()
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/openbmc/qemu/hw/audio/
H A Dintel-hda.c638 .wmask = 0x0103,
698 .wmask = 0xff,
711 .wmask = 0x03,
718 .wmask = 0x01,
750 .wmask = 0xff,
756 .wmask = 0x07,
762 .wmask = 0x05,
931 if (!reg->wmask) { in intel_hda_reg_write()
967 wmask &= reg->wmask; in intel_hda_reg_write()
968 *addr &= ~wmask; in intel_hda_reg_write()
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/openbmc/linux/arch/powerpc/platforms/powernv/
H A Dsmp.c166 unsigned long srr1, unexpected_mask, wmask; in pnv_cpu_offline_self() local
178 wmask = SRR1_WAKEMASK; in pnv_cpu_offline_self()
180 wmask = SRR1_WAKEMASK_P8; in pnv_cpu_offline_self()
242 if (((srr1 & wmask) == SRR1_WAKEEE) || in pnv_cpu_offline_self()
243 ((srr1 & wmask) == SRR1_WAKEHVI)) { in pnv_cpu_offline_self()
245 } else if ((srr1 & wmask) == SRR1_WAKEHDBELL) { in pnv_cpu_offline_self()
248 } else if ((srr1 & wmask) == SRR1_WAKERESET) { in pnv_cpu_offline_self()
/openbmc/qemu/hw/pci-bridge/
H A Dsimba.c63 pci_set_word(dev->wmask + PCI_IO_BASE_UPPER16, 0xffff); in simba_pci_bridge_realize()
64 pci_set_word(dev->wmask + PCI_IO_LIMIT_UPPER16, 0xffff); in simba_pci_bridge_realize()
H A Dgen_pcie_root_port.c107 pci_word_test_and_clear_mask(d->wmask + PCI_COMMAND, in gen_rp_realize()
109 d->wmask[PCI_IO_BASE] = 0; in gen_rp_realize()
110 d->wmask[PCI_IO_LIMIT] = 0; in gen_rp_realize()
H A Dcxl_root_port.c170 pci_word_test_and_clear_mask(pci_dev->wmask + PCI_COMMAND, in cxl_rp_realize()
172 pci_dev->wmask[PCI_IO_BASE] = 0; in cxl_rp_realize()
173 pci_dev->wmask[PCI_IO_LIMIT] = 0; in cxl_rp_realize()
/openbmc/qemu/hw/pci-host/
H A Dq35.c352 pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK; in mch_update_smram()
353 pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK; in mch_update_smram()
436 pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] = in mch_update_smbase_smram()
446 if (pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] == 0xff) { in mch_update_smbase_smram()
453 pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] &= in mch_update_smbase_smram()
554 d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK; in mch_reset()
555 d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK; in mch_reset()
563 d->wmask[MCH_HOST_BRIDGE_F_SMBASE] = 0xff; in mch_reset()
/openbmc/linux/arch/alpha/kernel/
H A Dcore_t2.c88 unsigned long wmask; member
392 t2_saved_config.window[0].wmask = *(vulp)T2_WMASK1; in t2_save_configuration()
395 t2_saved_config.window[1].wmask = *(vulp)T2_WMASK2; in t2_save_configuration()
489 *(vulp)T2_WMASK1 = t2_saved_config.window[0].wmask; in t2_kill_arch()
492 *(vulp)T2_WMASK2 = t2_saved_config.window[1].wmask; in t2_kill_arch()
H A Dcore_wildfire.c122 pci->pci_window[0].wmask.csr = (hose->sg_isa->size - 1) & 0xfff00000; in wildfire_init_hose()
126 pci->pci_window[1].wmask.csr = (0x40000000 -1) & 0xfff00000; in wildfire_init_hose()
130 pci->pci_window[2].wmask.csr = (0x40000000 -1) & 0xfff00000; in wildfire_init_hose()
134 pci->pci_window[3].wmask.csr = (hose->sg_pci->size - 1) & 0xfff00000; in wildfire_init_hose()
468 pci->pci_window[i].wmask.csr, in wildfire_dump_pci_regs()
/openbmc/linux/arch/xtensa/kernel/
H A Dsignal.c68 if (regs->wmask == 1) in flush_window_regs_user()
74 base = (XCHAL_NUM_AREGS / 4) - (regs->wmask >> 4); in flush_window_regs_user()
78 if ((regs->wmask & 2) == 0) in flush_window_regs_user()
119 regs->wmask = 1; in flush_window_regs_user()
199 regs->wmask = 1; in restore_sigcontext()
H A Dprocess.c319 int len = childregs->wmask & ~0xf; in copy_thread()
326 childregs->wmask = 1; in copy_thread()
/openbmc/qemu/hw/isa/
H A Dlpc_ich9.c532 uint16_t wmask; in ich9_lpc_pmcon_update() local
535 wmask = pci_get_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1); in ich9_lpc_pmcon_update()
536 wmask &= ~ICH9_LPC_GEN_PMCON_1_SMI_LOCK; in ich9_lpc_pmcon_update()
537 pci_set_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1, wmask); in ich9_lpc_pmcon_update()
718 pci_set_long(d->wmask + ICH9_LPC_PMBASE, in ich9_lpc_realize()
720 pci_set_byte(d->wmask + ICH9_LPC_PMBASE, in ich9_lpc_realize()
/openbmc/linux/arch/x86/include/asm/
H A Dimr.h52 unsigned int rmask, unsigned int wmask);
/openbmc/qemu/hw/ide/
H A Dcmd646.c266 dev->wmask[CFR] = 0x0; in pci_cmd646_ide_realize()
268 dev->wmask[ARTTIM23] = 0x0; in pci_cmd646_ide_realize()
270 dev->wmask[MRDMODE] = 0x0; in pci_cmd646_ide_realize()
/openbmc/qemu/linux-user/xtensa/
H A Dtarget_syscall.h22 xtensa_reg_t wmask; /* 28 */ member
/openbmc/linux/arch/xtensa/include/asm/
H A Dptrace.h60 unsigned long wmask; /* 28 */ member
/openbmc/u-boot/arch/xtensa/include/asm/
H A Dptrace.h91 unsigned long wmask; /* 28 */ member

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