1315a1350SMichael S. Tsirkin /*
2315a1350SMichael S. Tsirkin * QEMU PCI bus manager
3315a1350SMichael S. Tsirkin *
4315a1350SMichael S. Tsirkin * Copyright (c) 2004 Fabrice Bellard
5315a1350SMichael S. Tsirkin *
6315a1350SMichael S. Tsirkin * Permission is hereby granted, free of charge, to any person obtaining a copy
7315a1350SMichael S. Tsirkin * of this software and associated documentation files (the "Software"), to deal
8315a1350SMichael S. Tsirkin * in the Software without restriction, including without limitation the rights
9315a1350SMichael S. Tsirkin * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10315a1350SMichael S. Tsirkin * copies of the Software, and to permit persons to whom the Software is
11315a1350SMichael S. Tsirkin * furnished to do so, subject to the following conditions:
12315a1350SMichael S. Tsirkin *
13315a1350SMichael S. Tsirkin * The above copyright notice and this permission notice shall be included in
14315a1350SMichael S. Tsirkin * all copies or substantial portions of the Software.
15315a1350SMichael S. Tsirkin *
16315a1350SMichael S. Tsirkin * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17315a1350SMichael S. Tsirkin * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18315a1350SMichael S. Tsirkin * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19315a1350SMichael S. Tsirkin * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20315a1350SMichael S. Tsirkin * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21315a1350SMichael S. Tsirkin * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22315a1350SMichael S. Tsirkin * THE SOFTWARE.
23315a1350SMichael S. Tsirkin */
24e688df6bSMarkus Armbruster
2597d5408fSPeter Maydell #include "qemu/osdep.h"
262c65db5eSPaolo Bonzini #include "qemu/datadir.h"
277c16b5bbSPaolo Bonzini #include "qemu/units.h"
2864552b6bSMarkus Armbruster #include "hw/irq.h"
29c759b24fSMichael S. Tsirkin #include "hw/pci/pci.h"
30c759b24fSMichael S. Tsirkin #include "hw/pci/pci_bridge.h"
3106aac7bdSMichael S. Tsirkin #include "hw/pci/pci_bus.h"
32568f0690SDavid Gibson #include "hw/pci/pci_host.h"
33a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h"
34ce35e229SEduardo Habkost #include "hw/qdev-properties-system.h"
35ca77ee28SMarkus Armbruster #include "migration/qemu-file-types.h"
36d6454270SMarkus Armbruster #include "migration/vmstate.h"
371422e32dSPaolo Bonzini #include "net/net.h"
38b58c5c2dSMarkus Armbruster #include "sysemu/numa.h"
398eb85fb5SVladimir Sementsov-Ogievskiy #include "sysemu/runstate.h"
4046517dd4SMarkus Armbruster #include "sysemu/sysemu.h"
41c759b24fSMichael S. Tsirkin #include "hw/loader.h"
42d49b6836SMarkus Armbruster #include "qemu/error-report.h"
431de7afc9SPaolo Bonzini #include "qemu/range.h"
447828d750SDon Koch #include "trace.h"
45c759b24fSMichael S. Tsirkin #include "hw/pci/msi.h"
46c759b24fSMichael S. Tsirkin #include "hw/pci/msix.h"
475e954943SIgor Mammedov #include "hw/hotplug.h"
48e4024630SLaurent Vivier #include "hw/boards.h"
49e688df6bSMarkus Armbruster #include "qapi/error.h"
50f348b6d1SVeronia Bahaa #include "qemu/cutils.h"
51987b73b3SMarkus Armbruster #include "pci-internal.h"
52315a1350SMichael S. Tsirkin
536096cf78SDavid Woodhouse #include "hw/xen/xen.h"
546096cf78SDavid Woodhouse #include "hw/i386/kvm/xen_evtchn.h"
556096cf78SDavid Woodhouse
56315a1350SMichael S. Tsirkin //#define DEBUG_PCI
57315a1350SMichael S. Tsirkin #ifdef DEBUG_PCI
58315a1350SMichael S. Tsirkin # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
59315a1350SMichael S. Tsirkin #else
60315a1350SMichael S. Tsirkin # define PCI_DPRINTF(format, ...) do { } while (0)
61315a1350SMichael S. Tsirkin #endif
62315a1350SMichael S. Tsirkin
6388c725c7SCornelia Huck bool pci_available = true;
6488c725c7SCornelia Huck
65315a1350SMichael S. Tsirkin static char *pcibus_get_dev_path(DeviceState *dev);
66315a1350SMichael S. Tsirkin static char *pcibus_get_fw_dev_path(DeviceState *dev);
67ad80e367SPeter Maydell static void pcibus_reset_hold(Object *obj, ResetType type);
68ca92eb5dSAni Sinha static bool pcie_has_upstream_port(PCIDevice *dev);
69315a1350SMichael S. Tsirkin
70315a1350SMichael S. Tsirkin static Property pci_props[] = {
71315a1350SMichael S. Tsirkin DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
72315a1350SMichael S. Tsirkin DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
736a67577dSAkihiko Odaki DEFINE_PROP_UINT32("romsize", PCIDevice, romsize, UINT32_MAX),
74315a1350SMichael S. Tsirkin DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
75315a1350SMichael S. Tsirkin DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
76315a1350SMichael S. Tsirkin QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
776b449540SMichael S. Tsirkin DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present,
786b449540SMichael S. Tsirkin QEMU_PCIE_LNKSTA_DLLLA_BITNR, true),
79f03d8ea3SMarcel Apfelbaum DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present,
80f03d8ea3SMarcel Apfelbaum QEMU_PCIE_EXTCAP_INIT_BITNR, true),
814f5b6a05SJens Freimann DEFINE_PROP_STRING("failover_pair_id", PCIDevice,
824f5b6a05SJens Freimann failover_pair_id),
83b32bd763SIgor Mammedov DEFINE_PROP_UINT32("acpi-index", PCIDevice, acpi_index, 0),
845ed3dabeSLeonardo Bras DEFINE_PROP_BIT("x-pcie-err-unc-mask", PCIDevice, cap_present,
855ed3dabeSLeonardo Bras QEMU_PCIE_ERR_UNC_MASK_BITNR, true),
867c228c5fSAkihiko Odaki DEFINE_PROP_BIT("x-pcie-ari-nextfn-1", PCIDevice, cap_present,
877c228c5fSAkihiko Odaki QEMU_PCIE_ARI_NEXTFN_1_BITNR, false),
88315a1350SMichael S. Tsirkin DEFINE_PROP_END_OF_LIST()
89315a1350SMichael S. Tsirkin };
90315a1350SMichael S. Tsirkin
91d2f69df7SBandan Das static const VMStateDescription vmstate_pcibus = {
92d2f69df7SBandan Das .name = "PCIBUS",
93d2f69df7SBandan Das .version_id = 1,
94d2f69df7SBandan Das .minimum_version_id = 1,
958e5e0890SRichard Henderson .fields = (const VMStateField[]) {
96d2164ad3SHalil Pasic VMSTATE_INT32_EQUAL(nirq, PCIBus, NULL),
97d2f69df7SBandan Das VMSTATE_VARRAY_INT32(irq_count, PCIBus,
98d2f69df7SBandan Das nirq, 0, vmstate_info_int32,
99d2f69df7SBandan Das int32_t),
100d2f69df7SBandan Das VMSTATE_END_OF_LIST()
101d2f69df7SBandan Das }
102d2f69df7SBandan Das };
103d2f69df7SBandan Das
g_cmp_uint32(gconstpointer a,gconstpointer b,gpointer user_data)104041b1c40SIgor Mammedov static gint g_cmp_uint32(gconstpointer a, gconstpointer b, gpointer user_data)
105041b1c40SIgor Mammedov {
106041b1c40SIgor Mammedov return a - b;
107041b1c40SIgor Mammedov }
108041b1c40SIgor Mammedov
pci_acpi_index_list(void)109041b1c40SIgor Mammedov static GSequence *pci_acpi_index_list(void)
110041b1c40SIgor Mammedov {
111041b1c40SIgor Mammedov static GSequence *used_acpi_index_list;
112041b1c40SIgor Mammedov
113041b1c40SIgor Mammedov if (!used_acpi_index_list) {
114041b1c40SIgor Mammedov used_acpi_index_list = g_sequence_new(NULL);
115041b1c40SIgor Mammedov }
116041b1c40SIgor Mammedov return used_acpi_index_list;
117041b1c40SIgor Mammedov }
118041b1c40SIgor Mammedov
pci_init_bus_master(PCIDevice * pci_dev)119b86eacb8SMarcel Apfelbaum static void pci_init_bus_master(PCIDevice *pci_dev)
120b86eacb8SMarcel Apfelbaum {
121b86eacb8SMarcel Apfelbaum AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev);
122b86eacb8SMarcel Apfelbaum
123b86eacb8SMarcel Apfelbaum memory_region_init_alias(&pci_dev->bus_master_enable_region,
124b86eacb8SMarcel Apfelbaum OBJECT(pci_dev), "bus master",
125b86eacb8SMarcel Apfelbaum dma_as->root, 0, memory_region_size(dma_as->root));
126b86eacb8SMarcel Apfelbaum memory_region_set_enabled(&pci_dev->bus_master_enable_region, false);
1273716d590SJason Wang memory_region_add_subregion(&pci_dev->bus_master_container_region, 0,
1283716d590SJason Wang &pci_dev->bus_master_enable_region);
129b86eacb8SMarcel Apfelbaum }
130b86eacb8SMarcel Apfelbaum
pcibus_machine_done(Notifier * notifier,void * data)131b86eacb8SMarcel Apfelbaum static void pcibus_machine_done(Notifier *notifier, void *data)
132b86eacb8SMarcel Apfelbaum {
133b86eacb8SMarcel Apfelbaum PCIBus *bus = container_of(notifier, PCIBus, machine_done);
134b86eacb8SMarcel Apfelbaum int i;
135b86eacb8SMarcel Apfelbaum
136b86eacb8SMarcel Apfelbaum for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
137b86eacb8SMarcel Apfelbaum if (bus->devices[i]) {
138b86eacb8SMarcel Apfelbaum pci_init_bus_master(bus->devices[i]);
139b86eacb8SMarcel Apfelbaum }
140b86eacb8SMarcel Apfelbaum }
141b86eacb8SMarcel Apfelbaum }
142b86eacb8SMarcel Apfelbaum
pci_bus_realize(BusState * qbus,Error ** errp)143d2f69df7SBandan Das static void pci_bus_realize(BusState *qbus, Error **errp)
144d2f69df7SBandan Das {
145d2f69df7SBandan Das PCIBus *bus = PCI_BUS(qbus);
146d2f69df7SBandan Das
147b86eacb8SMarcel Apfelbaum bus->machine_done.notify = pcibus_machine_done;
148b86eacb8SMarcel Apfelbaum qemu_add_machine_init_done_notifier(&bus->machine_done);
149b86eacb8SMarcel Apfelbaum
15099b16e8eSJuan Quintela vmstate_register_any(NULL, &vmstate_pcibus, bus);
151d2f69df7SBandan Das }
152d2f69df7SBandan Das
pcie_bus_realize(BusState * qbus,Error ** errp)1532f57db8aSDavid Gibson static void pcie_bus_realize(BusState *qbus, Error **errp)
1542f57db8aSDavid Gibson {
1552f57db8aSDavid Gibson PCIBus *bus = PCI_BUS(qbus);
156b52fa0eaSPhilippe Mathieu-Daudé Error *local_err = NULL;
1572f57db8aSDavid Gibson
158b52fa0eaSPhilippe Mathieu-Daudé pci_bus_realize(qbus, &local_err);
159b52fa0eaSPhilippe Mathieu-Daudé if (local_err) {
160b52fa0eaSPhilippe Mathieu-Daudé error_propagate(errp, local_err);
161b52fa0eaSPhilippe Mathieu-Daudé return;
162b52fa0eaSPhilippe Mathieu-Daudé }
1632f57db8aSDavid Gibson
1642f57db8aSDavid Gibson /*
1652f57db8aSDavid Gibson * A PCI-E bus can support extended config space if it's the root
1662f57db8aSDavid Gibson * bus, or if the bus/bridge above it does as well
1672f57db8aSDavid Gibson */
1682f57db8aSDavid Gibson if (pci_bus_is_root(bus)) {
1692f57db8aSDavid Gibson bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
1702f57db8aSDavid Gibson } else {
1712f57db8aSDavid Gibson PCIBus *parent_bus = pci_get_bus(bus->parent_dev);
1722f57db8aSDavid Gibson
1732f57db8aSDavid Gibson if (pci_bus_allows_extended_config_space(parent_bus)) {
1742f57db8aSDavid Gibson bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
1752f57db8aSDavid Gibson }
1762f57db8aSDavid Gibson }
1772f57db8aSDavid Gibson }
1782f57db8aSDavid Gibson
pci_bus_unrealize(BusState * qbus)179b69c3c21SMarkus Armbruster static void pci_bus_unrealize(BusState *qbus)
180d2f69df7SBandan Das {
181d2f69df7SBandan Das PCIBus *bus = PCI_BUS(qbus);
182d2f69df7SBandan Das
183b86eacb8SMarcel Apfelbaum qemu_remove_machine_init_done_notifier(&bus->machine_done);
184b86eacb8SMarcel Apfelbaum
185d2f69df7SBandan Das vmstate_unregister(NULL, &vmstate_pcibus, bus);
186d2f69df7SBandan Das }
187d2f69df7SBandan Das
pcibus_num(PCIBus * bus)188602141d9SMarcel Apfelbaum static int pcibus_num(PCIBus *bus)
189602141d9SMarcel Apfelbaum {
190b0e5196aSDavid Gibson if (pci_bus_is_root(bus)) {
191602141d9SMarcel Apfelbaum return 0; /* pci host bridge */
192602141d9SMarcel Apfelbaum }
193602141d9SMarcel Apfelbaum return bus->parent_dev->config[PCI_SECONDARY_BUS];
194602141d9SMarcel Apfelbaum }
195602141d9SMarcel Apfelbaum
pcibus_numa_node(PCIBus * bus)1966a3042b2SMarcel Apfelbaum static uint16_t pcibus_numa_node(PCIBus *bus)
1976a3042b2SMarcel Apfelbaum {
1986a3042b2SMarcel Apfelbaum return NUMA_NODE_UNASSIGNED;
1996a3042b2SMarcel Apfelbaum }
2006a3042b2SMarcel Apfelbaum
pci_bus_class_init(ObjectClass * klass,void * data)201315a1350SMichael S. Tsirkin static void pci_bus_class_init(ObjectClass *klass, void *data)
202315a1350SMichael S. Tsirkin {
203315a1350SMichael S. Tsirkin BusClass *k = BUS_CLASS(klass);
204ce6a28eeSMarcel Apfelbaum PCIBusClass *pbc = PCI_BUS_CLASS(klass);
205e6c03989SPeter Maydell ResettableClass *rc = RESETTABLE_CLASS(klass);
206315a1350SMichael S. Tsirkin
207315a1350SMichael S. Tsirkin k->print_dev = pcibus_dev_print;
208315a1350SMichael S. Tsirkin k->get_dev_path = pcibus_get_dev_path;
209315a1350SMichael S. Tsirkin k->get_fw_dev_path = pcibus_get_fw_dev_path;
210d2f69df7SBandan Das k->realize = pci_bus_realize;
211d2f69df7SBandan Das k->unrealize = pci_bus_unrealize;
212e6c03989SPeter Maydell
213e6c03989SPeter Maydell rc->phases.hold = pcibus_reset_hold;
214ce6a28eeSMarcel Apfelbaum
215602141d9SMarcel Apfelbaum pbc->bus_num = pcibus_num;
2166a3042b2SMarcel Apfelbaum pbc->numa_node = pcibus_numa_node;
217315a1350SMichael S. Tsirkin }
218315a1350SMichael S. Tsirkin
219315a1350SMichael S. Tsirkin static const TypeInfo pci_bus_info = {
220315a1350SMichael S. Tsirkin .name = TYPE_PCI_BUS,
221315a1350SMichael S. Tsirkin .parent = TYPE_BUS,
222315a1350SMichael S. Tsirkin .instance_size = sizeof(PCIBus),
223ce6a28eeSMarcel Apfelbaum .class_size = sizeof(PCIBusClass),
224315a1350SMichael S. Tsirkin .class_init = pci_bus_class_init,
225315a1350SMichael S. Tsirkin };
226315a1350SMichael S. Tsirkin
227cf04aba2SBen Widawsky static const TypeInfo cxl_interface_info = {
228cf04aba2SBen Widawsky .name = INTERFACE_CXL_DEVICE,
229cf04aba2SBen Widawsky .parent = TYPE_INTERFACE,
230cf04aba2SBen Widawsky };
231cf04aba2SBen Widawsky
232619f02aeSEduardo Habkost static const TypeInfo pcie_interface_info = {
233619f02aeSEduardo Habkost .name = INTERFACE_PCIE_DEVICE,
234619f02aeSEduardo Habkost .parent = TYPE_INTERFACE,
235619f02aeSEduardo Habkost };
236619f02aeSEduardo Habkost
237619f02aeSEduardo Habkost static const TypeInfo conventional_pci_interface_info = {
238619f02aeSEduardo Habkost .name = INTERFACE_CONVENTIONAL_PCI_DEVICE,
239619f02aeSEduardo Habkost .parent = TYPE_INTERFACE,
240619f02aeSEduardo Habkost };
241619f02aeSEduardo Habkost
pcie_bus_class_init(ObjectClass * klass,void * data)2421c685a90SGreg Kurz static void pcie_bus_class_init(ObjectClass *klass, void *data)
2431c685a90SGreg Kurz {
2442f57db8aSDavid Gibson BusClass *k = BUS_CLASS(klass);
2451c685a90SGreg Kurz
2462f57db8aSDavid Gibson k->realize = pcie_bus_realize;
2471c685a90SGreg Kurz }
2481c685a90SGreg Kurz
2493a861c46SAlex Williamson static const TypeInfo pcie_bus_info = {
2503a861c46SAlex Williamson .name = TYPE_PCIE_BUS,
2513a861c46SAlex Williamson .parent = TYPE_PCI_BUS,
2521c685a90SGreg Kurz .class_init = pcie_bus_class_init,
2533a861c46SAlex Williamson };
2543a861c46SAlex Williamson
2554f8db871SBen Widawsky static const TypeInfo cxl_bus_info = {
2564f8db871SBen Widawsky .name = TYPE_CXL_BUS,
2574f8db871SBen Widawsky .parent = TYPE_PCIE_BUS,
2584f8db871SBen Widawsky .class_init = pcie_bus_class_init,
2594f8db871SBen Widawsky };
2604f8db871SBen Widawsky
261315a1350SMichael S. Tsirkin static void pci_update_mappings(PCIDevice *d);
262d98f08f5SMarcel Apfelbaum static void pci_irq_handler(void *opaque, int irq_num, int level);
263133e9b22SMarkus Armbruster static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **);
264315a1350SMichael S. Tsirkin static void pci_del_option_rom(PCIDevice *pdev);
265315a1350SMichael S. Tsirkin
266315a1350SMichael S. Tsirkin static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
267315a1350SMichael S. Tsirkin static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
268315a1350SMichael S. Tsirkin
269987b73b3SMarkus Armbruster PCIHostStateList pci_host_bridges;
270315a1350SMichael S. Tsirkin
pci_bar(PCIDevice * d,int reg)271cf8c704dSMichael Roth int pci_bar(PCIDevice *d, int reg)
272315a1350SMichael S. Tsirkin {
273315a1350SMichael S. Tsirkin uint8_t type;
274315a1350SMichael S. Tsirkin
2757c0fa8dfSKnut Omang /* PCIe virtual functions do not have their own BARs */
2767c0fa8dfSKnut Omang assert(!pci_is_vf(d));
2777c0fa8dfSKnut Omang
278315a1350SMichael S. Tsirkin if (reg != PCI_ROM_SLOT)
279315a1350SMichael S. Tsirkin return PCI_BASE_ADDRESS_0 + reg * 4;
280315a1350SMichael S. Tsirkin
281315a1350SMichael S. Tsirkin type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
282315a1350SMichael S. Tsirkin return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
283315a1350SMichael S. Tsirkin }
284315a1350SMichael S. Tsirkin
pci_irq_state(PCIDevice * d,int irq_num)285315a1350SMichael S. Tsirkin static inline int pci_irq_state(PCIDevice *d, int irq_num)
286315a1350SMichael S. Tsirkin {
287315a1350SMichael S. Tsirkin return (d->irq_state >> irq_num) & 0x1;
288315a1350SMichael S. Tsirkin }
289315a1350SMichael S. Tsirkin
pci_set_irq_state(PCIDevice * d,int irq_num,int level)290315a1350SMichael S. Tsirkin static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
291315a1350SMichael S. Tsirkin {
292315a1350SMichael S. Tsirkin d->irq_state &= ~(0x1 << irq_num);
293315a1350SMichael S. Tsirkin d->irq_state |= level << irq_num;
294315a1350SMichael S. Tsirkin }
295315a1350SMichael S. Tsirkin
pci_bus_change_irq_level(PCIBus * bus,int irq_num,int change)296b06fe3e7SPhilippe Mathieu-Daudé static void pci_bus_change_irq_level(PCIBus *bus, int irq_num, int change)
297b06fe3e7SPhilippe Mathieu-Daudé {
298459ca8bfSMark Cave-Ayland assert(irq_num >= 0);
299459ca8bfSMark Cave-Ayland assert(irq_num < bus->nirq);
300b06fe3e7SPhilippe Mathieu-Daudé bus->irq_count[irq_num] += change;
301b06fe3e7SPhilippe Mathieu-Daudé bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
302b06fe3e7SPhilippe Mathieu-Daudé }
303b06fe3e7SPhilippe Mathieu-Daudé
pci_change_irq_level(PCIDevice * pci_dev,int irq_num,int change)304315a1350SMichael S. Tsirkin static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
305315a1350SMichael S. Tsirkin {
306315a1350SMichael S. Tsirkin PCIBus *bus;
307315a1350SMichael S. Tsirkin for (;;) {
30828566eabSPhilippe Mathieu-Daudé int dev_irq = irq_num;
309fd56e061SDavid Gibson bus = pci_get_bus(pci_dev);
310f021f4e9SBernhard Beschow assert(bus->map_irq);
311315a1350SMichael S. Tsirkin irq_num = bus->map_irq(pci_dev, irq_num);
31228566eabSPhilippe Mathieu-Daudé trace_pci_route_irq(dev_irq, DEVICE(pci_dev)->canonical_path, irq_num,
31328566eabSPhilippe Mathieu-Daudé pci_bus_is_root(bus) ? "root-complex"
31428566eabSPhilippe Mathieu-Daudé : DEVICE(bus->parent_dev)->canonical_path);
315315a1350SMichael S. Tsirkin if (bus->set_irq)
316315a1350SMichael S. Tsirkin break;
317315a1350SMichael S. Tsirkin pci_dev = bus->parent_dev;
318315a1350SMichael S. Tsirkin }
319b06fe3e7SPhilippe Mathieu-Daudé pci_bus_change_irq_level(bus, irq_num, change);
320315a1350SMichael S. Tsirkin }
321315a1350SMichael S. Tsirkin
pci_bus_get_irq_level(PCIBus * bus,int irq_num)322315a1350SMichael S. Tsirkin int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
323315a1350SMichael S. Tsirkin {
324315a1350SMichael S. Tsirkin assert(irq_num >= 0);
325315a1350SMichael S. Tsirkin assert(irq_num < bus->nirq);
326315a1350SMichael S. Tsirkin return !!bus->irq_count[irq_num];
327315a1350SMichael S. Tsirkin }
328315a1350SMichael S. Tsirkin
329315a1350SMichael S. Tsirkin /* Update interrupt status bit in config space on interrupt
330315a1350SMichael S. Tsirkin * state change. */
pci_update_irq_status(PCIDevice * dev)331315a1350SMichael S. Tsirkin static void pci_update_irq_status(PCIDevice *dev)
332315a1350SMichael S. Tsirkin {
333315a1350SMichael S. Tsirkin if (dev->irq_state) {
334315a1350SMichael S. Tsirkin dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
335315a1350SMichael S. Tsirkin } else {
336315a1350SMichael S. Tsirkin dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
337315a1350SMichael S. Tsirkin }
338315a1350SMichael S. Tsirkin }
339315a1350SMichael S. Tsirkin
pci_device_deassert_intx(PCIDevice * dev)340315a1350SMichael S. Tsirkin void pci_device_deassert_intx(PCIDevice *dev)
341315a1350SMichael S. Tsirkin {
342315a1350SMichael S. Tsirkin int i;
343315a1350SMichael S. Tsirkin for (i = 0; i < PCI_NUM_PINS; ++i) {
344d98f08f5SMarcel Apfelbaum pci_irq_handler(dev, i, 0);
345315a1350SMichael S. Tsirkin }
346315a1350SMichael S. Tsirkin }
347315a1350SMichael S. Tsirkin
pci_msi_trigger(PCIDevice * dev,MSIMessage msg)34808cf3dc6SJagannathan Raman static void pci_msi_trigger(PCIDevice *dev, MSIMessage msg)
34908cf3dc6SJagannathan Raman {
35008cf3dc6SJagannathan Raman MemTxAttrs attrs = {};
35108cf3dc6SJagannathan Raman
3526096cf78SDavid Woodhouse /*
3536096cf78SDavid Woodhouse * Xen uses the high bits of the address to contain some of the bits
3546096cf78SDavid Woodhouse * of the PIRQ#. Therefore we can't just send the write cycle and
3556096cf78SDavid Woodhouse * trust that it's caught by the APIC at 0xfee00000 because the
3566096cf78SDavid Woodhouse * target of the write might be e.g. 0x0x1000fee46000 for PIRQ#4166.
3576096cf78SDavid Woodhouse * So we intercept the delivery here instead of in kvm_send_msi().
3586096cf78SDavid Woodhouse */
3596096cf78SDavid Woodhouse if (xen_mode == XEN_EMULATE &&
3606096cf78SDavid Woodhouse xen_evtchn_deliver_pirq_msi(msg.address, msg.data)) {
3616096cf78SDavid Woodhouse return;
3626096cf78SDavid Woodhouse }
36308cf3dc6SJagannathan Raman attrs.requester_id = pci_requester_id(dev);
36408cf3dc6SJagannathan Raman address_space_stl_le(&dev->bus_master_as, msg.address, msg.data,
36508cf3dc6SJagannathan Raman attrs, NULL);
36608cf3dc6SJagannathan Raman }
36708cf3dc6SJagannathan Raman
pci_reset_regions(PCIDevice * dev)3687c0fa8dfSKnut Omang static void pci_reset_regions(PCIDevice *dev)
369315a1350SMichael S. Tsirkin {
370315a1350SMichael S. Tsirkin int r;
3717c0fa8dfSKnut Omang if (pci_is_vf(dev)) {
3727c0fa8dfSKnut Omang return;
3737c0fa8dfSKnut Omang }
374315a1350SMichael S. Tsirkin
3757c0fa8dfSKnut Omang for (r = 0; r < PCI_NUM_REGIONS; ++r) {
3767c0fa8dfSKnut Omang PCIIORegion *region = &dev->io_regions[r];
3777c0fa8dfSKnut Omang if (!region->size) {
3787c0fa8dfSKnut Omang continue;
3797c0fa8dfSKnut Omang }
3807c0fa8dfSKnut Omang
3817c0fa8dfSKnut Omang if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
3827c0fa8dfSKnut Omang region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
3837c0fa8dfSKnut Omang pci_set_quad(dev->config + pci_bar(dev, r), region->type);
3847c0fa8dfSKnut Omang } else {
3857c0fa8dfSKnut Omang pci_set_long(dev->config + pci_bar(dev, r), region->type);
3867c0fa8dfSKnut Omang }
3877c0fa8dfSKnut Omang }
3887c0fa8dfSKnut Omang }
3897c0fa8dfSKnut Omang
pci_do_device_reset(PCIDevice * dev)3907c0fa8dfSKnut Omang static void pci_do_device_reset(PCIDevice *dev)
3917c0fa8dfSKnut Omang {
392315a1350SMichael S. Tsirkin pci_device_deassert_intx(dev);
39358b59014SCole Robinson assert(dev->irq_state == 0);
39458b59014SCole Robinson
395315a1350SMichael S. Tsirkin /* Clear all writable bits */
396315a1350SMichael S. Tsirkin pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
397315a1350SMichael S. Tsirkin pci_get_word(dev->wmask + PCI_COMMAND) |
398315a1350SMichael S. Tsirkin pci_get_word(dev->w1cmask + PCI_COMMAND));
399315a1350SMichael S. Tsirkin pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
400315a1350SMichael S. Tsirkin pci_get_word(dev->wmask + PCI_STATUS) |
401315a1350SMichael S. Tsirkin pci_get_word(dev->w1cmask + PCI_STATUS));
4027ff81d63SBALATON Zoltan /* Some devices make bits of PCI_INTERRUPT_LINE read only */
4037ff81d63SBALATON Zoltan pci_byte_test_and_clear_mask(dev->config + PCI_INTERRUPT_LINE,
4047ff81d63SBALATON Zoltan pci_get_word(dev->wmask + PCI_INTERRUPT_LINE) |
4057ff81d63SBALATON Zoltan pci_get_word(dev->w1cmask + PCI_INTERRUPT_LINE));
406315a1350SMichael S. Tsirkin dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
4077c0fa8dfSKnut Omang pci_reset_regions(dev);
408315a1350SMichael S. Tsirkin pci_update_mappings(dev);
409315a1350SMichael S. Tsirkin
410315a1350SMichael S. Tsirkin msi_reset(dev);
411315a1350SMichael S. Tsirkin msix_reset(dev);
4121a909e3dSAkihiko Odaki pcie_sriov_pf_reset(dev);
413315a1350SMichael S. Tsirkin }
414315a1350SMichael S. Tsirkin
415315a1350SMichael S. Tsirkin /*
416dcc20931SPaolo Bonzini * This function is called on #RST and FLR.
417dcc20931SPaolo Bonzini * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
418315a1350SMichael S. Tsirkin */
pci_device_reset(PCIDevice * dev)419dcc20931SPaolo Bonzini void pci_device_reset(PCIDevice *dev)
420dcc20931SPaolo Bonzini {
42178e4d5cbSPeter Maydell device_cold_reset(&dev->qdev);
422dcc20931SPaolo Bonzini pci_do_device_reset(dev);
423dcc20931SPaolo Bonzini }
424dcc20931SPaolo Bonzini
425dcc20931SPaolo Bonzini /*
426dcc20931SPaolo Bonzini * Trigger pci bus reset under a given bus.
42778e4d5cbSPeter Maydell * Called via bus_cold_reset on RST# assert, after the devices
42878e4d5cbSPeter Maydell * have been reset device_cold_reset-ed already.
429dcc20931SPaolo Bonzini */
pcibus_reset_hold(Object * obj,ResetType type)430ad80e367SPeter Maydell static void pcibus_reset_hold(Object *obj, ResetType type)
431315a1350SMichael S. Tsirkin {
432e6c03989SPeter Maydell PCIBus *bus = PCI_BUS(obj);
433315a1350SMichael S. Tsirkin int i;
434315a1350SMichael S. Tsirkin
435315a1350SMichael S. Tsirkin for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
436315a1350SMichael S. Tsirkin if (bus->devices[i]) {
437dcc20931SPaolo Bonzini pci_do_device_reset(bus->devices[i]);
438315a1350SMichael S. Tsirkin }
439315a1350SMichael S. Tsirkin }
440315a1350SMichael S. Tsirkin
4419bdbbfc3SPaolo Bonzini for (i = 0; i < bus->nirq; i++) {
4429bdbbfc3SPaolo Bonzini assert(bus->irq_count[i] == 0);
4439bdbbfc3SPaolo Bonzini }
444315a1350SMichael S. Tsirkin }
445315a1350SMichael S. Tsirkin
pci_host_bus_register(DeviceState * host)4463dbc01aeSCao jin static void pci_host_bus_register(DeviceState *host)
447315a1350SMichael S. Tsirkin {
4483dbc01aeSCao jin PCIHostState *host_bridge = PCI_HOST_BRIDGE(host);
4497588e2b0SDavid Gibson
4507588e2b0SDavid Gibson QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next);
451315a1350SMichael S. Tsirkin }
452315a1350SMichael S. Tsirkin
pci_host_bus_unregister(DeviceState * host)453c13ee169SMichael Roth static void pci_host_bus_unregister(DeviceState *host)
454c13ee169SMichael Roth {
455c13ee169SMichael Roth PCIHostState *host_bridge = PCI_HOST_BRIDGE(host);
456c13ee169SMichael Roth
457c13ee169SMichael Roth QLIST_REMOVE(host_bridge, next);
458c13ee169SMichael Roth }
459c13ee169SMichael Roth
pci_device_root_bus(const PCIDevice * d)460c473d18dSDavid Gibson PCIBus *pci_device_root_bus(const PCIDevice *d)
461315a1350SMichael S. Tsirkin {
462fd56e061SDavid Gibson PCIBus *bus = pci_get_bus(d);
463315a1350SMichael S. Tsirkin
464ce6a28eeSMarcel Apfelbaum while (!pci_bus_is_root(bus)) {
465ce6a28eeSMarcel Apfelbaum d = bus->parent_dev;
466ce6a28eeSMarcel Apfelbaum assert(d != NULL);
467ce6a28eeSMarcel Apfelbaum
468fd56e061SDavid Gibson bus = pci_get_bus(d);
469315a1350SMichael S. Tsirkin }
470315a1350SMichael S. Tsirkin
471c473d18dSDavid Gibson return bus;
472315a1350SMichael S. Tsirkin }
473315a1350SMichael S. Tsirkin
pci_root_bus_path(PCIDevice * dev)474568f0690SDavid Gibson const char *pci_root_bus_path(PCIDevice *dev)
475c473d18dSDavid Gibson {
476568f0690SDavid Gibson PCIBus *rootbus = pci_device_root_bus(dev);
477568f0690SDavid Gibson PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent);
478568f0690SDavid Gibson PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge);
479c473d18dSDavid Gibson
480568f0690SDavid Gibson assert(host_bridge->bus == rootbus);
481568f0690SDavid Gibson
482568f0690SDavid Gibson if (hc->root_bus_path) {
483568f0690SDavid Gibson return (*hc->root_bus_path)(host_bridge, rootbus);
484315a1350SMichael S. Tsirkin }
485315a1350SMichael S. Tsirkin
486568f0690SDavid Gibson return rootbus->qbus.name;
487315a1350SMichael S. Tsirkin }
488315a1350SMichael S. Tsirkin
pci_bus_bypass_iommu(PCIBus * bus)4892d64b7bbSXingang Wang bool pci_bus_bypass_iommu(PCIBus *bus)
4902d64b7bbSXingang Wang {
4912d64b7bbSXingang Wang PCIBus *rootbus = bus;
4922d64b7bbSXingang Wang PCIHostState *host_bridge;
4932d64b7bbSXingang Wang
4942d64b7bbSXingang Wang if (!pci_bus_is_root(bus)) {
4952d64b7bbSXingang Wang rootbus = pci_device_root_bus(bus->parent_dev);
4962d64b7bbSXingang Wang }
4972d64b7bbSXingang Wang
4982d64b7bbSXingang Wang host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent);
4992d64b7bbSXingang Wang
5002d64b7bbSXingang Wang assert(host_bridge->bus == rootbus);
5012d64b7bbSXingang Wang
5022d64b7bbSXingang Wang return host_bridge->bypass_iommu;
5032d64b7bbSXingang Wang }
5042d64b7bbSXingang Wang
pci_root_bus_internal_init(PCIBus * bus,DeviceState * parent,MemoryRegion * mem,MemoryRegion * io,uint8_t devfn_min)5058d4cdf01SPeter Maydell static void pci_root_bus_internal_init(PCIBus *bus, DeviceState *parent,
50649909a0dSPhilippe Mathieu-Daudé MemoryRegion *mem, MemoryRegion *io,
507315a1350SMichael S. Tsirkin uint8_t devfn_min)
508315a1350SMichael S. Tsirkin {
509315a1350SMichael S. Tsirkin assert(PCI_FUNC(devfn_min) == 0);
510315a1350SMichael S. Tsirkin bus->devfn_min = devfn_min;
5118b884984SMark Cave-Ayland bus->slot_reserved_mask = 0x0;
51249909a0dSPhilippe Mathieu-Daudé bus->address_space_mem = mem;
51349909a0dSPhilippe Mathieu-Daudé bus->address_space_io = io;
514b0e5196aSDavid Gibson bus->flags |= PCI_BUS_IS_ROOT;
515315a1350SMichael S. Tsirkin
516315a1350SMichael S. Tsirkin /* host bridge */
517315a1350SMichael S. Tsirkin QLIST_INIT(&bus->child);
5182b8cc89aSDavid Gibson
5193dbc01aeSCao jin pci_host_bus_register(parent);
520315a1350SMichael S. Tsirkin }
521315a1350SMichael S. Tsirkin
pci_bus_uninit(PCIBus * bus)522c13ee169SMichael Roth static void pci_bus_uninit(PCIBus *bus)
523c13ee169SMichael Roth {
524c13ee169SMichael Roth pci_host_bus_unregister(BUS(bus)->parent);
525c13ee169SMichael Roth }
526c13ee169SMichael Roth
pci_bus_is_express(const PCIBus * bus)527c6f16471SIgor Mammedov bool pci_bus_is_express(const PCIBus *bus)
5288c0bf9e2SAlex Williamson {
5298c0bf9e2SAlex Williamson return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
5308c0bf9e2SAlex Williamson }
5318c0bf9e2SAlex Williamson
pci_root_bus_init(PCIBus * bus,size_t bus_size,DeviceState * parent,const char * name,MemoryRegion * mem,MemoryRegion * io,uint8_t devfn_min,const char * typename)5328d4cdf01SPeter Maydell void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent,
5334fec6404SPaolo Bonzini const char *name,
53449909a0dSPhilippe Mathieu-Daudé MemoryRegion *mem, MemoryRegion *io,
53560a0e443SAlex Williamson uint8_t devfn_min, const char *typename)
5364fec6404SPaolo Bonzini {
537d637e1dcSPeter Maydell qbus_init(bus, bus_size, typename, parent, name);
53849909a0dSPhilippe Mathieu-Daudé pci_root_bus_internal_init(bus, parent, mem, io, devfn_min);
5394fec6404SPaolo Bonzini }
5404fec6404SPaolo Bonzini
pci_root_bus_new(DeviceState * parent,const char * name,MemoryRegion * mem,MemoryRegion * io,uint8_t devfn_min,const char * typename)5411115ff6dSDavid Gibson PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
54249909a0dSPhilippe Mathieu-Daudé MemoryRegion *mem, MemoryRegion *io,
54360a0e443SAlex Williamson uint8_t devfn_min, const char *typename)
544315a1350SMichael S. Tsirkin {
545315a1350SMichael S. Tsirkin PCIBus *bus;
546315a1350SMichael S. Tsirkin
5479388d170SPeter Maydell bus = PCI_BUS(qbus_new(typename, parent, name));
54849909a0dSPhilippe Mathieu-Daudé pci_root_bus_internal_init(bus, parent, mem, io, devfn_min);
549315a1350SMichael S. Tsirkin return bus;
550315a1350SMichael S. Tsirkin }
551315a1350SMichael S. Tsirkin
pci_root_bus_cleanup(PCIBus * bus)552c13ee169SMichael Roth void pci_root_bus_cleanup(PCIBus *bus)
553c13ee169SMichael Roth {
554c13ee169SMichael Roth pci_bus_uninit(bus);
55507578b0aSDavid Hildenbrand /* the caller of the unplug hotplug handler will delete this device */
556f1483b46SMarkus Armbruster qbus_unrealize(BUS(bus));
557c13ee169SMichael Roth }
558c13ee169SMichael Roth
pci_bus_irqs(PCIBus * bus,pci_set_irq_fn set_irq,void * irq_opaque,int nirq)559f021f4e9SBernhard Beschow void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq,
560315a1350SMichael S. Tsirkin void *irq_opaque, int nirq)
561315a1350SMichael S. Tsirkin {
562315a1350SMichael S. Tsirkin bus->set_irq = set_irq;
563315a1350SMichael S. Tsirkin bus->irq_opaque = irq_opaque;
564315a1350SMichael S. Tsirkin bus->nirq = nirq;
565c0b59416SBernhard Beschow g_free(bus->irq_count);
566315a1350SMichael S. Tsirkin bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
567315a1350SMichael S. Tsirkin }
568315a1350SMichael S. Tsirkin
pci_bus_map_irqs(PCIBus * bus,pci_map_irq_fn map_irq)569f021f4e9SBernhard Beschow void pci_bus_map_irqs(PCIBus *bus, pci_map_irq_fn map_irq)
570f021f4e9SBernhard Beschow {
571f021f4e9SBernhard Beschow bus->map_irq = map_irq;
572f021f4e9SBernhard Beschow }
573f021f4e9SBernhard Beschow
pci_bus_irqs_cleanup(PCIBus * bus)574c13ee169SMichael Roth void pci_bus_irqs_cleanup(PCIBus *bus)
575c13ee169SMichael Roth {
576c13ee169SMichael Roth bus->set_irq = NULL;
577c13ee169SMichael Roth bus->map_irq = NULL;
578c13ee169SMichael Roth bus->irq_opaque = NULL;
579c13ee169SMichael Roth bus->nirq = 0;
580c13ee169SMichael Roth g_free(bus->irq_count);
581c0b59416SBernhard Beschow bus->irq_count = NULL;
582c13ee169SMichael Roth }
583c13ee169SMichael Roth
pci_register_root_bus(DeviceState * parent,const char * name,pci_set_irq_fn set_irq,pci_map_irq_fn map_irq,void * irq_opaque,MemoryRegion * mem,MemoryRegion * io,uint8_t devfn_min,int nirq,const char * typename)5841115ff6dSDavid Gibson PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
585315a1350SMichael S. Tsirkin pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
586315a1350SMichael S. Tsirkin void *irq_opaque,
58749909a0dSPhilippe Mathieu-Daudé MemoryRegion *mem, MemoryRegion *io,
5881115ff6dSDavid Gibson uint8_t devfn_min, int nirq,
5891115ff6dSDavid Gibson const char *typename)
590315a1350SMichael S. Tsirkin {
591315a1350SMichael S. Tsirkin PCIBus *bus;
592315a1350SMichael S. Tsirkin
59349909a0dSPhilippe Mathieu-Daudé bus = pci_root_bus_new(parent, name, mem, io, devfn_min, typename);
594f021f4e9SBernhard Beschow pci_bus_irqs(bus, set_irq, irq_opaque, nirq);
595f021f4e9SBernhard Beschow pci_bus_map_irqs(bus, map_irq);
596315a1350SMichael S. Tsirkin return bus;
597315a1350SMichael S. Tsirkin }
598315a1350SMichael S. Tsirkin
pci_unregister_root_bus(PCIBus * bus)599c13ee169SMichael Roth void pci_unregister_root_bus(PCIBus *bus)
600c13ee169SMichael Roth {
601c13ee169SMichael Roth pci_bus_irqs_cleanup(bus);
602c13ee169SMichael Roth pci_root_bus_cleanup(bus);
603c13ee169SMichael Roth }
604c13ee169SMichael Roth
pci_bus_num(PCIBus * s)605315a1350SMichael S. Tsirkin int pci_bus_num(PCIBus *s)
606315a1350SMichael S. Tsirkin {
607602141d9SMarcel Apfelbaum return PCI_BUS_GET_CLASS(s)->bus_num(s);
608315a1350SMichael S. Tsirkin }
609315a1350SMichael S. Tsirkin
610500db1daSXingang Wang /* Returns the min and max bus numbers of a PCI bus hierarchy */
pci_bus_range(PCIBus * bus,int * min_bus,int * max_bus)611500db1daSXingang Wang void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus)
612500db1daSXingang Wang {
613500db1daSXingang Wang int i;
614500db1daSXingang Wang *min_bus = *max_bus = pci_bus_num(bus);
615500db1daSXingang Wang
616500db1daSXingang Wang for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
617500db1daSXingang Wang PCIDevice *dev = bus->devices[i];
618500db1daSXingang Wang
619ad494274SIgor Mammedov if (dev && IS_PCI_BRIDGE(dev)) {
620500db1daSXingang Wang *min_bus = MIN(*min_bus, dev->config[PCI_SECONDARY_BUS]);
621500db1daSXingang Wang *max_bus = MAX(*max_bus, dev->config[PCI_SUBORDINATE_BUS]);
622500db1daSXingang Wang }
623500db1daSXingang Wang }
624500db1daSXingang Wang }
625500db1daSXingang Wang
pci_bus_numa_node(PCIBus * bus)6266a3042b2SMarcel Apfelbaum int pci_bus_numa_node(PCIBus *bus)
6276a3042b2SMarcel Apfelbaum {
6286a3042b2SMarcel Apfelbaum return PCI_BUS_GET_CLASS(bus)->numa_node(bus);
629315a1350SMichael S. Tsirkin }
630315a1350SMichael S. Tsirkin
get_pci_config_device(QEMUFile * f,void * pv,size_t size,const VMStateField * field)6312c21ee76SJianjun Duan static int get_pci_config_device(QEMUFile *f, void *pv, size_t size,
63203fee66fSMarc-André Lureau const VMStateField *field)
633315a1350SMichael S. Tsirkin {
634315a1350SMichael S. Tsirkin PCIDevice *s = container_of(pv, PCIDevice, config);
635315a1350SMichael S. Tsirkin uint8_t *config;
636315a1350SMichael S. Tsirkin int i;
637315a1350SMichael S. Tsirkin
638315a1350SMichael S. Tsirkin assert(size == pci_config_size(s));
639315a1350SMichael S. Tsirkin config = g_malloc(size);
640315a1350SMichael S. Tsirkin
641315a1350SMichael S. Tsirkin qemu_get_buffer(f, config, size);
642315a1350SMichael S. Tsirkin for (i = 0; i < size; ++i) {
643315a1350SMichael S. Tsirkin if ((config[i] ^ s->config[i]) &
644315a1350SMichael S. Tsirkin s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
6457c59364dSDr. David Alan Gilbert error_report("%s: Bad config data: i=0x%x read: %x device: %x "
6467c59364dSDr. David Alan Gilbert "cmask: %x wmask: %x w1cmask:%x", __func__,
6477c59364dSDr. David Alan Gilbert i, config[i], s->config[i],
6487c59364dSDr. David Alan Gilbert s->cmask[i], s->wmask[i], s->w1cmask[i]);
649315a1350SMichael S. Tsirkin g_free(config);
650315a1350SMichael S. Tsirkin return -EINVAL;
651315a1350SMichael S. Tsirkin }
652315a1350SMichael S. Tsirkin }
653315a1350SMichael S. Tsirkin memcpy(s->config, config, size);
654315a1350SMichael S. Tsirkin
655315a1350SMichael S. Tsirkin pci_update_mappings(s);
656ad494274SIgor Mammedov if (IS_PCI_BRIDGE(s)) {
657ad494274SIgor Mammedov pci_bridge_update_mappings(PCI_BRIDGE(s));
658e78e9ae4SDon Koch }
659315a1350SMichael S. Tsirkin
660315a1350SMichael S. Tsirkin memory_region_set_enabled(&s->bus_master_enable_region,
661315a1350SMichael S. Tsirkin pci_get_word(s->config + PCI_COMMAND)
662315a1350SMichael S. Tsirkin & PCI_COMMAND_MASTER);
663315a1350SMichael S. Tsirkin
664315a1350SMichael S. Tsirkin g_free(config);
665315a1350SMichael S. Tsirkin return 0;
666315a1350SMichael S. Tsirkin }
667315a1350SMichael S. Tsirkin
668315a1350SMichael S. Tsirkin /* just put buffer */
put_pci_config_device(QEMUFile * f,void * pv,size_t size,const VMStateField * field,JSONWriter * vmdesc)6692c21ee76SJianjun Duan static int put_pci_config_device(QEMUFile *f, void *pv, size_t size,
6703ddba9a9SMarkus Armbruster const VMStateField *field, JSONWriter *vmdesc)
671315a1350SMichael S. Tsirkin {
672315a1350SMichael S. Tsirkin const uint8_t **v = pv;
673315a1350SMichael S. Tsirkin assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
674315a1350SMichael S. Tsirkin qemu_put_buffer(f, *v, size);
6752c21ee76SJianjun Duan
6762c21ee76SJianjun Duan return 0;
677315a1350SMichael S. Tsirkin }
678315a1350SMichael S. Tsirkin
6798e5e0890SRichard Henderson static const VMStateInfo vmstate_info_pci_config = {
680315a1350SMichael S. Tsirkin .name = "pci config",
681315a1350SMichael S. Tsirkin .get = get_pci_config_device,
682315a1350SMichael S. Tsirkin .put = put_pci_config_device,
683315a1350SMichael S. Tsirkin };
684315a1350SMichael S. Tsirkin
get_pci_irq_state(QEMUFile * f,void * pv,size_t size,const VMStateField * field)6852c21ee76SJianjun Duan static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size,
68603fee66fSMarc-André Lureau const VMStateField *field)
687315a1350SMichael S. Tsirkin {
688315a1350SMichael S. Tsirkin PCIDevice *s = container_of(pv, PCIDevice, irq_state);
689315a1350SMichael S. Tsirkin uint32_t irq_state[PCI_NUM_PINS];
690315a1350SMichael S. Tsirkin int i;
691315a1350SMichael S. Tsirkin for (i = 0; i < PCI_NUM_PINS; ++i) {
692315a1350SMichael S. Tsirkin irq_state[i] = qemu_get_be32(f);
693315a1350SMichael S. Tsirkin if (irq_state[i] != 0x1 && irq_state[i] != 0) {
694315a1350SMichael S. Tsirkin fprintf(stderr, "irq state %d: must be 0 or 1.\n",
695315a1350SMichael S. Tsirkin irq_state[i]);
696315a1350SMichael S. Tsirkin return -EINVAL;
697315a1350SMichael S. Tsirkin }
698315a1350SMichael S. Tsirkin }
699315a1350SMichael S. Tsirkin
700315a1350SMichael S. Tsirkin for (i = 0; i < PCI_NUM_PINS; ++i) {
701315a1350SMichael S. Tsirkin pci_set_irq_state(s, i, irq_state[i]);
702315a1350SMichael S. Tsirkin }
703315a1350SMichael S. Tsirkin
704315a1350SMichael S. Tsirkin return 0;
705315a1350SMichael S. Tsirkin }
706315a1350SMichael S. Tsirkin
put_pci_irq_state(QEMUFile * f,void * pv,size_t size,const VMStateField * field,JSONWriter * vmdesc)7072c21ee76SJianjun Duan static int put_pci_irq_state(QEMUFile *f, void *pv, size_t size,
7083ddba9a9SMarkus Armbruster const VMStateField *field, JSONWriter *vmdesc)
709315a1350SMichael S. Tsirkin {
710315a1350SMichael S. Tsirkin int i;
711315a1350SMichael S. Tsirkin PCIDevice *s = container_of(pv, PCIDevice, irq_state);
712315a1350SMichael S. Tsirkin
713315a1350SMichael S. Tsirkin for (i = 0; i < PCI_NUM_PINS; ++i) {
714315a1350SMichael S. Tsirkin qemu_put_be32(f, pci_irq_state(s, i));
715315a1350SMichael S. Tsirkin }
7162c21ee76SJianjun Duan
7172c21ee76SJianjun Duan return 0;
718315a1350SMichael S. Tsirkin }
719315a1350SMichael S. Tsirkin
7208e5e0890SRichard Henderson static const VMStateInfo vmstate_info_pci_irq_state = {
721315a1350SMichael S. Tsirkin .name = "pci irq state",
722315a1350SMichael S. Tsirkin .get = get_pci_irq_state,
723315a1350SMichael S. Tsirkin .put = put_pci_irq_state,
724315a1350SMichael S. Tsirkin };
725315a1350SMichael S. Tsirkin
migrate_is_pcie(void * opaque,int version_id)72620daa90aSDr. David Alan Gilbert static bool migrate_is_pcie(void *opaque, int version_id)
72720daa90aSDr. David Alan Gilbert {
72820daa90aSDr. David Alan Gilbert return pci_is_express((PCIDevice *)opaque);
72920daa90aSDr. David Alan Gilbert }
73020daa90aSDr. David Alan Gilbert
migrate_is_not_pcie(void * opaque,int version_id)73120daa90aSDr. David Alan Gilbert static bool migrate_is_not_pcie(void *opaque, int version_id)
73220daa90aSDr. David Alan Gilbert {
73320daa90aSDr. David Alan Gilbert return !pci_is_express((PCIDevice *)opaque);
73420daa90aSDr. David Alan Gilbert }
73520daa90aSDr. David Alan Gilbert
736315a1350SMichael S. Tsirkin const VMStateDescription vmstate_pci_device = {
737315a1350SMichael S. Tsirkin .name = "PCIDevice",
738315a1350SMichael S. Tsirkin .version_id = 2,
739315a1350SMichael S. Tsirkin .minimum_version_id = 1,
7408e5e0890SRichard Henderson .fields = (const VMStateField[]) {
7413476436aSMichael S. Tsirkin VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice),
74220daa90aSDr. David Alan Gilbert VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice,
74320daa90aSDr. David Alan Gilbert migrate_is_not_pcie,
74420daa90aSDr. David Alan Gilbert 0, vmstate_info_pci_config,
745315a1350SMichael S. Tsirkin PCI_CONFIG_SPACE_SIZE),
74620daa90aSDr. David Alan Gilbert VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice,
74720daa90aSDr. David Alan Gilbert migrate_is_pcie,
74820daa90aSDr. David Alan Gilbert 0, vmstate_info_pci_config,
749315a1350SMichael S. Tsirkin PCIE_CONFIG_SPACE_SIZE),
750315a1350SMichael S. Tsirkin VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
751315a1350SMichael S. Tsirkin vmstate_info_pci_irq_state,
752315a1350SMichael S. Tsirkin PCI_NUM_PINS * sizeof(int32_t)),
753315a1350SMichael S. Tsirkin VMSTATE_END_OF_LIST()
754315a1350SMichael S. Tsirkin }
755315a1350SMichael S. Tsirkin };
756315a1350SMichael S. Tsirkin
757315a1350SMichael S. Tsirkin
pci_device_save(PCIDevice * s,QEMUFile * f)758315a1350SMichael S. Tsirkin void pci_device_save(PCIDevice *s, QEMUFile *f)
759315a1350SMichael S. Tsirkin {
760315a1350SMichael S. Tsirkin /* Clear interrupt status bit: it is implicit
761315a1350SMichael S. Tsirkin * in irq_state which we are saving.
762315a1350SMichael S. Tsirkin * This makes us compatible with old devices
763315a1350SMichael S. Tsirkin * which never set or clear this bit. */
764315a1350SMichael S. Tsirkin s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
76520daa90aSDr. David Alan Gilbert vmstate_save_state(f, &vmstate_pci_device, s, NULL);
766315a1350SMichael S. Tsirkin /* Restore the interrupt status bit. */
767315a1350SMichael S. Tsirkin pci_update_irq_status(s);
768315a1350SMichael S. Tsirkin }
769315a1350SMichael S. Tsirkin
pci_device_load(PCIDevice * s,QEMUFile * f)770315a1350SMichael S. Tsirkin int pci_device_load(PCIDevice *s, QEMUFile *f)
771315a1350SMichael S. Tsirkin {
772315a1350SMichael S. Tsirkin int ret;
77320daa90aSDr. David Alan Gilbert ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id);
774315a1350SMichael S. Tsirkin /* Restore the interrupt status bit. */
775315a1350SMichael S. Tsirkin pci_update_irq_status(s);
776315a1350SMichael S. Tsirkin return ret;
777315a1350SMichael S. Tsirkin }
778315a1350SMichael S. Tsirkin
pci_set_default_subsystem_id(PCIDevice * pci_dev)779315a1350SMichael S. Tsirkin static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
780315a1350SMichael S. Tsirkin {
781315a1350SMichael S. Tsirkin pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
782315a1350SMichael S. Tsirkin pci_default_sub_vendor_id);
783315a1350SMichael S. Tsirkin pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
784315a1350SMichael S. Tsirkin pci_default_sub_device_id);
785315a1350SMichael S. Tsirkin }
786315a1350SMichael S. Tsirkin
787315a1350SMichael S. Tsirkin /*
788315a1350SMichael S. Tsirkin * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
789315a1350SMichael S. Tsirkin * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
790315a1350SMichael S. Tsirkin */
pci_parse_devaddr(const char * addr,int * domp,int * busp,unsigned int * slotp,unsigned int * funcp)7916dbcb819SMarkus Armbruster static int pci_parse_devaddr(const char *addr, int *domp, int *busp,
792315a1350SMichael S. Tsirkin unsigned int *slotp, unsigned int *funcp)
793315a1350SMichael S. Tsirkin {
794315a1350SMichael S. Tsirkin const char *p;
795315a1350SMichael S. Tsirkin char *e;
796315a1350SMichael S. Tsirkin unsigned long val;
797315a1350SMichael S. Tsirkin unsigned long dom = 0, bus = 0;
798315a1350SMichael S. Tsirkin unsigned int slot = 0;
799315a1350SMichael S. Tsirkin unsigned int func = 0;
800315a1350SMichael S. Tsirkin
801315a1350SMichael S. Tsirkin p = addr;
802315a1350SMichael S. Tsirkin val = strtoul(p, &e, 16);
803315a1350SMichael S. Tsirkin if (e == p)
804315a1350SMichael S. Tsirkin return -1;
805315a1350SMichael S. Tsirkin if (*e == ':') {
806315a1350SMichael S. Tsirkin bus = val;
807315a1350SMichael S. Tsirkin p = e + 1;
808315a1350SMichael S. Tsirkin val = strtoul(p, &e, 16);
809315a1350SMichael S. Tsirkin if (e == p)
810315a1350SMichael S. Tsirkin return -1;
811315a1350SMichael S. Tsirkin if (*e == ':') {
812315a1350SMichael S. Tsirkin dom = bus;
813315a1350SMichael S. Tsirkin bus = val;
814315a1350SMichael S. Tsirkin p = e + 1;
815315a1350SMichael S. Tsirkin val = strtoul(p, &e, 16);
816315a1350SMichael S. Tsirkin if (e == p)
817315a1350SMichael S. Tsirkin return -1;
818315a1350SMichael S. Tsirkin }
819315a1350SMichael S. Tsirkin }
820315a1350SMichael S. Tsirkin
821315a1350SMichael S. Tsirkin slot = val;
822315a1350SMichael S. Tsirkin
823315a1350SMichael S. Tsirkin if (funcp != NULL) {
824315a1350SMichael S. Tsirkin if (*e != '.')
825315a1350SMichael S. Tsirkin return -1;
826315a1350SMichael S. Tsirkin
827315a1350SMichael S. Tsirkin p = e + 1;
828315a1350SMichael S. Tsirkin val = strtoul(p, &e, 16);
829315a1350SMichael S. Tsirkin if (e == p)
830315a1350SMichael S. Tsirkin return -1;
831315a1350SMichael S. Tsirkin
832315a1350SMichael S. Tsirkin func = val;
833315a1350SMichael S. Tsirkin }
834315a1350SMichael S. Tsirkin
835315a1350SMichael S. Tsirkin /* if funcp == NULL func is 0 */
836315a1350SMichael S. Tsirkin if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
837315a1350SMichael S. Tsirkin return -1;
838315a1350SMichael S. Tsirkin
839315a1350SMichael S. Tsirkin if (*e)
840315a1350SMichael S. Tsirkin return -1;
841315a1350SMichael S. Tsirkin
842315a1350SMichael S. Tsirkin *domp = dom;
843315a1350SMichael S. Tsirkin *busp = bus;
844315a1350SMichael S. Tsirkin *slotp = slot;
845315a1350SMichael S. Tsirkin if (funcp != NULL)
846315a1350SMichael S. Tsirkin *funcp = func;
847315a1350SMichael S. Tsirkin return 0;
848315a1350SMichael S. Tsirkin }
849315a1350SMichael S. Tsirkin
pci_init_cmask(PCIDevice * dev)850315a1350SMichael S. Tsirkin static void pci_init_cmask(PCIDevice *dev)
851315a1350SMichael S. Tsirkin {
852315a1350SMichael S. Tsirkin pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
853315a1350SMichael S. Tsirkin pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
854315a1350SMichael S. Tsirkin dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
855315a1350SMichael S. Tsirkin dev->cmask[PCI_REVISION_ID] = 0xff;
856315a1350SMichael S. Tsirkin dev->cmask[PCI_CLASS_PROG] = 0xff;
857315a1350SMichael S. Tsirkin pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
858315a1350SMichael S. Tsirkin dev->cmask[PCI_HEADER_TYPE] = 0xff;
859315a1350SMichael S. Tsirkin dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
860315a1350SMichael S. Tsirkin }
861315a1350SMichael S. Tsirkin
pci_init_wmask(PCIDevice * dev)862315a1350SMichael S. Tsirkin static void pci_init_wmask(PCIDevice *dev)
863315a1350SMichael S. Tsirkin {
864315a1350SMichael S. Tsirkin int config_size = pci_config_size(dev);
865315a1350SMichael S. Tsirkin
866315a1350SMichael S. Tsirkin dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
867315a1350SMichael S. Tsirkin dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
868315a1350SMichael S. Tsirkin pci_set_word(dev->wmask + PCI_COMMAND,
869315a1350SMichael S. Tsirkin PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
870315a1350SMichael S. Tsirkin PCI_COMMAND_INTX_DISABLE);
871315a1350SMichael S. Tsirkin pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
872315a1350SMichael S. Tsirkin
873315a1350SMichael S. Tsirkin memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
874315a1350SMichael S. Tsirkin config_size - PCI_CONFIG_HEADER_SIZE);
875315a1350SMichael S. Tsirkin }
876315a1350SMichael S. Tsirkin
pci_init_w1cmask(PCIDevice * dev)877315a1350SMichael S. Tsirkin static void pci_init_w1cmask(PCIDevice *dev)
878315a1350SMichael S. Tsirkin {
879315a1350SMichael S. Tsirkin /*
880315a1350SMichael S. Tsirkin * Note: It's okay to set w1cmask even for readonly bits as
881315a1350SMichael S. Tsirkin * long as their value is hardwired to 0.
882315a1350SMichael S. Tsirkin */
883315a1350SMichael S. Tsirkin pci_set_word(dev->w1cmask + PCI_STATUS,
884315a1350SMichael S. Tsirkin PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
885315a1350SMichael S. Tsirkin PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
886315a1350SMichael S. Tsirkin PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
887315a1350SMichael S. Tsirkin }
888315a1350SMichael S. Tsirkin
pci_init_mask_bridge(PCIDevice * d)889315a1350SMichael S. Tsirkin static void pci_init_mask_bridge(PCIDevice *d)
890315a1350SMichael S. Tsirkin {
891315a1350SMichael S. Tsirkin /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
8924565917bSMichael S. Tsirkin PCI_SEC_LATENCY_TIMER */
893315a1350SMichael S. Tsirkin memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
894315a1350SMichael S. Tsirkin
895315a1350SMichael S. Tsirkin /* base and limit */
896315a1350SMichael S. Tsirkin d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
897315a1350SMichael S. Tsirkin d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
898315a1350SMichael S. Tsirkin pci_set_word(d->wmask + PCI_MEMORY_BASE,
899315a1350SMichael S. Tsirkin PCI_MEMORY_RANGE_MASK & 0xffff);
900315a1350SMichael S. Tsirkin pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
901315a1350SMichael S. Tsirkin PCI_MEMORY_RANGE_MASK & 0xffff);
902315a1350SMichael S. Tsirkin pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
903315a1350SMichael S. Tsirkin PCI_PREF_RANGE_MASK & 0xffff);
904315a1350SMichael S. Tsirkin pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
905315a1350SMichael S. Tsirkin PCI_PREF_RANGE_MASK & 0xffff);
906315a1350SMichael S. Tsirkin
907315a1350SMichael S. Tsirkin /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
908315a1350SMichael S. Tsirkin memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
909315a1350SMichael S. Tsirkin
910315a1350SMichael S. Tsirkin /* Supported memory and i/o types */
911315a1350SMichael S. Tsirkin d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16;
912315a1350SMichael S. Tsirkin d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16;
913315a1350SMichael S. Tsirkin pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
914315a1350SMichael S. Tsirkin PCI_PREF_RANGE_TYPE_64);
915315a1350SMichael S. Tsirkin pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
916315a1350SMichael S. Tsirkin PCI_PREF_RANGE_TYPE_64);
917315a1350SMichael S. Tsirkin
918ba7d8515SAlex Williamson /*
919ba7d8515SAlex Williamson * TODO: Bridges default to 10-bit VGA decoding but we currently only
920ba7d8515SAlex Williamson * implement 16-bit decoding (no alias support).
921ba7d8515SAlex Williamson */
922315a1350SMichael S. Tsirkin pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
923315a1350SMichael S. Tsirkin PCI_BRIDGE_CTL_PARITY |
924315a1350SMichael S. Tsirkin PCI_BRIDGE_CTL_SERR |
925315a1350SMichael S. Tsirkin PCI_BRIDGE_CTL_ISA |
926315a1350SMichael S. Tsirkin PCI_BRIDGE_CTL_VGA |
927315a1350SMichael S. Tsirkin PCI_BRIDGE_CTL_VGA_16BIT |
928315a1350SMichael S. Tsirkin PCI_BRIDGE_CTL_MASTER_ABORT |
929315a1350SMichael S. Tsirkin PCI_BRIDGE_CTL_BUS_RESET |
930315a1350SMichael S. Tsirkin PCI_BRIDGE_CTL_FAST_BACK |
931315a1350SMichael S. Tsirkin PCI_BRIDGE_CTL_DISCARD |
932315a1350SMichael S. Tsirkin PCI_BRIDGE_CTL_SEC_DISCARD |
933315a1350SMichael S. Tsirkin PCI_BRIDGE_CTL_DISCARD_SERR);
934315a1350SMichael S. Tsirkin /* Below does not do anything as we never set this bit, put here for
935315a1350SMichael S. Tsirkin * completeness. */
936315a1350SMichael S. Tsirkin pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
937315a1350SMichael S. Tsirkin PCI_BRIDGE_CTL_DISCARD_STATUS);
938315a1350SMichael S. Tsirkin d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK;
939315a1350SMichael S. Tsirkin d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK;
940315a1350SMichael S. Tsirkin pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE,
941315a1350SMichael S. Tsirkin PCI_PREF_RANGE_TYPE_MASK);
942315a1350SMichael S. Tsirkin pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT,
943315a1350SMichael S. Tsirkin PCI_PREF_RANGE_TYPE_MASK);
944315a1350SMichael S. Tsirkin }
945315a1350SMichael S. Tsirkin
pci_init_multifunction(PCIBus * bus,PCIDevice * dev,Error ** errp)946133e9b22SMarkus Armbruster static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp)
947315a1350SMichael S. Tsirkin {
948315a1350SMichael S. Tsirkin uint8_t slot = PCI_SLOT(dev->devfn);
949315a1350SMichael S. Tsirkin uint8_t func;
950315a1350SMichael S. Tsirkin
951315a1350SMichael S. Tsirkin if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
952315a1350SMichael S. Tsirkin dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
953315a1350SMichael S. Tsirkin }
954315a1350SMichael S. Tsirkin
955aa01c491SMichael S. Tsirkin /*
956aa01c491SMichael S. Tsirkin * With SR/IOV and ARI, a device at function 0 need not be a multifunction
957aa01c491SMichael S. Tsirkin * device, as it may just be a VF that ended up with function 0 in
958aa01c491SMichael S. Tsirkin * the legacy PCI interpretation. Avoid failing in such cases:
959aa01c491SMichael S. Tsirkin */
960aa01c491SMichael S. Tsirkin if (pci_is_vf(dev) &&
961aa01c491SMichael S. Tsirkin dev->exp.sriov_vf.pf->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
9627c0fa8dfSKnut Omang return;
9637c0fa8dfSKnut Omang }
9647c0fa8dfSKnut Omang
9657c0fa8dfSKnut Omang /*
966315a1350SMichael S. Tsirkin * multifunction bit is interpreted in two ways as follows.
967315a1350SMichael S. Tsirkin * - all functions must set the bit to 1.
968315a1350SMichael S. Tsirkin * Example: Intel X53
969315a1350SMichael S. Tsirkin * - function 0 must set the bit, but the rest function (> 0)
970315a1350SMichael S. Tsirkin * is allowed to leave the bit to 0.
971315a1350SMichael S. Tsirkin * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
972315a1350SMichael S. Tsirkin *
973315a1350SMichael S. Tsirkin * So OS (at least Linux) checks the bit of only function 0,
974315a1350SMichael S. Tsirkin * and doesn't see the bit of function > 0.
975315a1350SMichael S. Tsirkin *
976315a1350SMichael S. Tsirkin * The below check allows both interpretation.
977315a1350SMichael S. Tsirkin */
978315a1350SMichael S. Tsirkin if (PCI_FUNC(dev->devfn)) {
979315a1350SMichael S. Tsirkin PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
980315a1350SMichael S. Tsirkin if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
981315a1350SMichael S. Tsirkin /* function 0 should set multifunction bit */
982133e9b22SMarkus Armbruster error_setg(errp, "PCI: single function device can't be populated "
983315a1350SMichael S. Tsirkin "in function %x.%x", slot, PCI_FUNC(dev->devfn));
984133e9b22SMarkus Armbruster return;
985315a1350SMichael S. Tsirkin }
986133e9b22SMarkus Armbruster return;
987315a1350SMichael S. Tsirkin }
988315a1350SMichael S. Tsirkin
989315a1350SMichael S. Tsirkin if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
990133e9b22SMarkus Armbruster return;
991315a1350SMichael S. Tsirkin }
992315a1350SMichael S. Tsirkin /* function 0 indicates single function, so function > 0 must be NULL */
993315a1350SMichael S. Tsirkin for (func = 1; func < PCI_FUNC_MAX; ++func) {
994aa01c491SMichael S. Tsirkin if (bus->devices[PCI_DEVFN(slot, func)]) {
995133e9b22SMarkus Armbruster error_setg(errp, "PCI: %x.0 indicates single function, "
996315a1350SMichael S. Tsirkin "but %x.%x is already populated.",
997315a1350SMichael S. Tsirkin slot, slot, func);
998133e9b22SMarkus Armbruster return;
999315a1350SMichael S. Tsirkin }
1000315a1350SMichael S. Tsirkin }
1001315a1350SMichael S. Tsirkin }
1002315a1350SMichael S. Tsirkin
pci_config_alloc(PCIDevice * pci_dev)1003315a1350SMichael S. Tsirkin static void pci_config_alloc(PCIDevice *pci_dev)
1004315a1350SMichael S. Tsirkin {
1005315a1350SMichael S. Tsirkin int config_size = pci_config_size(pci_dev);
1006315a1350SMichael S. Tsirkin
1007315a1350SMichael S. Tsirkin pci_dev->config = g_malloc0(config_size);
1008315a1350SMichael S. Tsirkin pci_dev->cmask = g_malloc0(config_size);
1009315a1350SMichael S. Tsirkin pci_dev->wmask = g_malloc0(config_size);
1010315a1350SMichael S. Tsirkin pci_dev->w1cmask = g_malloc0(config_size);
1011315a1350SMichael S. Tsirkin pci_dev->used = g_malloc0(config_size);
1012315a1350SMichael S. Tsirkin }
1013315a1350SMichael S. Tsirkin
pci_config_free(PCIDevice * pci_dev)1014315a1350SMichael S. Tsirkin static void pci_config_free(PCIDevice *pci_dev)
1015315a1350SMichael S. Tsirkin {
1016315a1350SMichael S. Tsirkin g_free(pci_dev->config);
1017315a1350SMichael S. Tsirkin g_free(pci_dev->cmask);
1018315a1350SMichael S. Tsirkin g_free(pci_dev->wmask);
1019315a1350SMichael S. Tsirkin g_free(pci_dev->w1cmask);
1020315a1350SMichael S. Tsirkin g_free(pci_dev->used);
1021315a1350SMichael S. Tsirkin }
1022315a1350SMichael S. Tsirkin
do_pci_unregister_device(PCIDevice * pci_dev)102330607764SMarcel Apfelbaum static void do_pci_unregister_device(PCIDevice *pci_dev)
102430607764SMarcel Apfelbaum {
1025fd56e061SDavid Gibson pci_get_bus(pci_dev)->devices[pci_dev->devfn] = NULL;
102630607764SMarcel Apfelbaum pci_config_free(pci_dev);
102730607764SMarcel Apfelbaum
10286096cf78SDavid Woodhouse if (xen_mode == XEN_EMULATE) {
10296096cf78SDavid Woodhouse xen_evtchn_remove_pci_device(pci_dev);
10306096cf78SDavid Woodhouse }
1031193982c6SAlexey Kardashevskiy if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) {
1032c53598edSAlexey Kardashevskiy memory_region_del_subregion(&pci_dev->bus_master_container_region,
1033c53598edSAlexey Kardashevskiy &pci_dev->bus_master_enable_region);
1034193982c6SAlexey Kardashevskiy }
103530607764SMarcel Apfelbaum address_space_destroy(&pci_dev->bus_master_as);
103630607764SMarcel Apfelbaum }
103730607764SMarcel Apfelbaum
10384a94b3aaSPeter Xu /* Extract PCIReqIDCache into BDF format */
pci_req_id_cache_extract(PCIReqIDCache * cache)10394a94b3aaSPeter Xu static uint16_t pci_req_id_cache_extract(PCIReqIDCache *cache)
10404a94b3aaSPeter Xu {
10414a94b3aaSPeter Xu uint8_t bus_n;
10424a94b3aaSPeter Xu uint16_t result;
10434a94b3aaSPeter Xu
10444a94b3aaSPeter Xu switch (cache->type) {
10454a94b3aaSPeter Xu case PCI_REQ_ID_BDF:
10464a94b3aaSPeter Xu result = pci_get_bdf(cache->dev);
10474a94b3aaSPeter Xu break;
10484a94b3aaSPeter Xu case PCI_REQ_ID_SECONDARY_BUS:
1049fd56e061SDavid Gibson bus_n = pci_dev_bus_num(cache->dev);
10504a94b3aaSPeter Xu result = PCI_BUILD_BDF(bus_n, 0);
10514a94b3aaSPeter Xu break;
10524a94b3aaSPeter Xu default:
1053eaf27fabSMarkus Armbruster error_report("Invalid PCI requester ID cache type: %d",
10544a94b3aaSPeter Xu cache->type);
10554a94b3aaSPeter Xu exit(1);
10564a94b3aaSPeter Xu break;
10574a94b3aaSPeter Xu }
10584a94b3aaSPeter Xu
10594a94b3aaSPeter Xu return result;
10604a94b3aaSPeter Xu }
10614a94b3aaSPeter Xu
10624a94b3aaSPeter Xu /* Parse bridges up to the root complex and return requester ID
10634a94b3aaSPeter Xu * cache for specific device. For full PCIe topology, the cache
10644a94b3aaSPeter Xu * result would be exactly the same as getting BDF of the device.
10654a94b3aaSPeter Xu * However, several tricks are required when system mixed up with
10664a94b3aaSPeter Xu * legacy PCI devices and PCIe-to-PCI bridges.
10674a94b3aaSPeter Xu *
10684a94b3aaSPeter Xu * Here we cache the proxy device (and type) not requester ID since
10694a94b3aaSPeter Xu * bus number might change from time to time.
10704a94b3aaSPeter Xu */
pci_req_id_cache_get(PCIDevice * dev)10714a94b3aaSPeter Xu static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev)
10724a94b3aaSPeter Xu {
10734a94b3aaSPeter Xu PCIDevice *parent;
10744a94b3aaSPeter Xu PCIReqIDCache cache = {
10754a94b3aaSPeter Xu .dev = dev,
10764a94b3aaSPeter Xu .type = PCI_REQ_ID_BDF,
10774a94b3aaSPeter Xu };
10784a94b3aaSPeter Xu
1079fd56e061SDavid Gibson while (!pci_bus_is_root(pci_get_bus(dev))) {
10804a94b3aaSPeter Xu /* We are under PCI/PCIe bridges */
1081fd56e061SDavid Gibson parent = pci_get_bus(dev)->parent_dev;
10824a94b3aaSPeter Xu if (pci_is_express(parent)) {
10834a94b3aaSPeter Xu if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) {
10844a94b3aaSPeter Xu /* When we pass through PCIe-to-PCI/PCIX bridges, we
10854a94b3aaSPeter Xu * override the requester ID using secondary bus
10864a94b3aaSPeter Xu * number of parent bridge with zeroed devfn
10874a94b3aaSPeter Xu * (pcie-to-pci bridge spec chap 2.3). */
10884a94b3aaSPeter Xu cache.type = PCI_REQ_ID_SECONDARY_BUS;
10894a94b3aaSPeter Xu cache.dev = dev;
10904a94b3aaSPeter Xu }
10914a94b3aaSPeter Xu } else {
10924a94b3aaSPeter Xu /* Legacy PCI, override requester ID with the bridge's
10934a94b3aaSPeter Xu * BDF upstream. When the root complex connects to
10944a94b3aaSPeter Xu * legacy PCI devices (including buses), it can only
10954a94b3aaSPeter Xu * obtain requester ID info from directly attached
10964a94b3aaSPeter Xu * devices. If devices are attached under bridges, only
10974a94b3aaSPeter Xu * the requester ID of the bridge that is directly
10984a94b3aaSPeter Xu * attached to the root complex can be recognized. */
10994a94b3aaSPeter Xu cache.type = PCI_REQ_ID_BDF;
11004a94b3aaSPeter Xu cache.dev = parent;
11014a94b3aaSPeter Xu }
11024a94b3aaSPeter Xu dev = parent;
11034a94b3aaSPeter Xu }
11044a94b3aaSPeter Xu
11054a94b3aaSPeter Xu return cache;
11064a94b3aaSPeter Xu }
11074a94b3aaSPeter Xu
pci_requester_id(PCIDevice * dev)11084a94b3aaSPeter Xu uint16_t pci_requester_id(PCIDevice *dev)
11094a94b3aaSPeter Xu {
11104a94b3aaSPeter Xu return pci_req_id_cache_extract(&dev->requester_id_cache);
11114a94b3aaSPeter Xu }
11124a94b3aaSPeter Xu
pci_bus_devfn_available(PCIBus * bus,int devfn)11139b717a3aSMark Cave-Ayland static bool pci_bus_devfn_available(PCIBus *bus, int devfn)
11149b717a3aSMark Cave-Ayland {
11159b717a3aSMark Cave-Ayland return !(bus->devices[devfn]);
11169b717a3aSMark Cave-Ayland }
11179b717a3aSMark Cave-Ayland
pci_bus_devfn_reserved(PCIBus * bus,int devfn)11188b884984SMark Cave-Ayland static bool pci_bus_devfn_reserved(PCIBus *bus, int devfn)
11198b884984SMark Cave-Ayland {
11208b884984SMark Cave-Ayland return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn));
11218b884984SMark Cave-Ayland }
11228b884984SMark Cave-Ayland
pci_bus_get_slot_reserved_mask(PCIBus * bus)1123b93fe7f2SChuck Zmudzinski uint32_t pci_bus_get_slot_reserved_mask(PCIBus *bus)
1124b93fe7f2SChuck Zmudzinski {
1125b93fe7f2SChuck Zmudzinski return bus->slot_reserved_mask;
1126b93fe7f2SChuck Zmudzinski }
1127b93fe7f2SChuck Zmudzinski
pci_bus_set_slot_reserved_mask(PCIBus * bus,uint32_t mask)1128b93fe7f2SChuck Zmudzinski void pci_bus_set_slot_reserved_mask(PCIBus *bus, uint32_t mask)
1129b93fe7f2SChuck Zmudzinski {
1130b93fe7f2SChuck Zmudzinski bus->slot_reserved_mask |= mask;
1131b93fe7f2SChuck Zmudzinski }
1132b93fe7f2SChuck Zmudzinski
pci_bus_clear_slot_reserved_mask(PCIBus * bus,uint32_t mask)1133b93fe7f2SChuck Zmudzinski void pci_bus_clear_slot_reserved_mask(PCIBus *bus, uint32_t mask)
1134b93fe7f2SChuck Zmudzinski {
1135b93fe7f2SChuck Zmudzinski bus->slot_reserved_mask &= ~mask;
1136b93fe7f2SChuck Zmudzinski }
1137b93fe7f2SChuck Zmudzinski
1138315a1350SMichael S. Tsirkin /* -1 for devfn means auto assign */
do_pci_register_device(PCIDevice * pci_dev,const char * name,int devfn,Error ** errp)1139fd56e061SDavid Gibson static PCIDevice *do_pci_register_device(PCIDevice *pci_dev,
1140133e9b22SMarkus Armbruster const char *name, int devfn,
1141133e9b22SMarkus Armbruster Error **errp)
1142315a1350SMichael S. Tsirkin {
1143315a1350SMichael S. Tsirkin PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
1144315a1350SMichael S. Tsirkin PCIConfigReadFunc *config_read = pc->config_read;
1145315a1350SMichael S. Tsirkin PCIConfigWriteFunc *config_write = pc->config_write;
1146133e9b22SMarkus Armbruster Error *local_err = NULL;
11473f1e1478SCao jin DeviceState *dev = DEVICE(pci_dev);
1148fd56e061SDavid Gibson PCIBus *bus = pci_get_bus(pci_dev);
1149ad494274SIgor Mammedov bool is_bridge = IS_PCI_BRIDGE(pci_dev);
11503f1e1478SCao jin
11510144f6f1SMarcel Apfelbaum /* Only pci bridges can be attached to extra PCI root buses */
1152ad494274SIgor Mammedov if (pci_bus_is_root(bus) && bus->parent_dev && !is_bridge) {
11530144f6f1SMarcel Apfelbaum error_setg(errp,
11540144f6f1SMarcel Apfelbaum "PCI: Only PCI/PCIe bridges can be plugged into %s",
11550144f6f1SMarcel Apfelbaum bus->parent_dev->name);
11560144f6f1SMarcel Apfelbaum return NULL;
11570144f6f1SMarcel Apfelbaum }
1158315a1350SMichael S. Tsirkin
1159315a1350SMichael S. Tsirkin if (devfn < 0) {
1160315a1350SMichael S. Tsirkin for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
1161315a1350SMichael S. Tsirkin devfn += PCI_FUNC_MAX) {
11628b884984SMark Cave-Ayland if (pci_bus_devfn_available(bus, devfn) &&
11638b884984SMark Cave-Ayland !pci_bus_devfn_reserved(bus, devfn)) {
1164315a1350SMichael S. Tsirkin goto found;
1165315a1350SMichael S. Tsirkin }
11669b717a3aSMark Cave-Ayland }
11678b884984SMark Cave-Ayland error_setg(errp, "PCI: no slot/function available for %s, all in use "
11688b884984SMark Cave-Ayland "or reserved", name);
1169315a1350SMichael S. Tsirkin return NULL;
1170315a1350SMichael S. Tsirkin found: ;
11718b884984SMark Cave-Ayland } else if (pci_bus_devfn_reserved(bus, devfn)) {
11728b884984SMark Cave-Ayland error_setg(errp, "PCI: slot %d function %d not available for %s,"
11738b884984SMark Cave-Ayland " reserved",
11748b884984SMark Cave-Ayland PCI_SLOT(devfn), PCI_FUNC(devfn), name);
11758b884984SMark Cave-Ayland return NULL;
11769b717a3aSMark Cave-Ayland } else if (!pci_bus_devfn_available(bus, devfn)) {
1177133e9b22SMarkus Armbruster error_setg(errp, "PCI: slot %d function %d not available for %s,"
1178ad003b9eSZhenzhong Duan " in use by %s,id=%s",
1179133e9b22SMarkus Armbruster PCI_SLOT(devfn), PCI_FUNC(devfn), name,
1180ad003b9eSZhenzhong Duan bus->devices[devfn]->name, bus->devices[devfn]->qdev.id);
1181315a1350SMichael S. Tsirkin return NULL;
118267d045a0SAni Sinha } /*
118367d045a0SAni Sinha * Populating function 0 triggers a scan from the guest that
118467d045a0SAni Sinha * exposes other non-zero functions. Hence we need to ensure that
118567d045a0SAni Sinha * function 0 wasn't added yet.
118667d045a0SAni Sinha */
118767d045a0SAni Sinha else if (dev->hotplugged &&
11887c0fa8dfSKnut Omang !pci_is_vf(pci_dev) &&
11893f1e1478SCao jin pci_get_function_0(pci_dev)) {
11903298bbceSJulia Suvorova error_setg(errp, "PCI: slot %d function 0 already occupied by %s,"
11913f1e1478SCao jin " new func %s cannot be exposed to guest.",
1192d93ddfb1SMichael S. Tsirkin PCI_SLOT(pci_get_function_0(pci_dev)->devfn),
1193d93ddfb1SMichael S. Tsirkin pci_get_function_0(pci_dev)->name,
11943f1e1478SCao jin name);
11953f1e1478SCao jin
11963f1e1478SCao jin return NULL;
1197315a1350SMichael S. Tsirkin }
1198e00387d5SAvi Kivity
1199efc8188eSLe Tan pci_dev->devfn = devfn;
12004a94b3aaSPeter Xu pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev);
1201d06bce95SAlexey Kardashevskiy pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
1202e00387d5SAvi Kivity
12033716d590SJason Wang memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev),
12043716d590SJason Wang "bus master container", UINT64_MAX);
12053716d590SJason Wang address_space_init(&pci_dev->bus_master_as,
12063716d590SJason Wang &pci_dev->bus_master_container_region, pci_dev->name);
12073716d590SJason Wang
12082f181fbdSPaolo Bonzini if (phase_check(PHASE_MACHINE_READY)) {
1209b86eacb8SMarcel Apfelbaum pci_init_bus_master(pci_dev);
1210b86eacb8SMarcel Apfelbaum }
1211315a1350SMichael S. Tsirkin pci_dev->irq_state = 0;
1212315a1350SMichael S. Tsirkin pci_config_alloc(pci_dev);
1213315a1350SMichael S. Tsirkin
1214315a1350SMichael S. Tsirkin pci_config_set_vendor_id(pci_dev->config, pc->vendor_id);
1215315a1350SMichael S. Tsirkin pci_config_set_device_id(pci_dev->config, pc->device_id);
1216315a1350SMichael S. Tsirkin pci_config_set_revision(pci_dev->config, pc->revision);
1217315a1350SMichael S. Tsirkin pci_config_set_class(pci_dev->config, pc->class_id);
1218315a1350SMichael S. Tsirkin
1219ad494274SIgor Mammedov if (!is_bridge) {
1220315a1350SMichael S. Tsirkin if (pc->subsystem_vendor_id || pc->subsystem_id) {
1221315a1350SMichael S. Tsirkin pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
1222315a1350SMichael S. Tsirkin pc->subsystem_vendor_id);
1223315a1350SMichael S. Tsirkin pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
1224315a1350SMichael S. Tsirkin pc->subsystem_id);
1225315a1350SMichael S. Tsirkin } else {
1226315a1350SMichael S. Tsirkin pci_set_default_subsystem_id(pci_dev);
1227315a1350SMichael S. Tsirkin }
1228315a1350SMichael S. Tsirkin } else {
1229315a1350SMichael S. Tsirkin /* subsystem_vendor_id/subsystem_id are only for header type 0 */
1230315a1350SMichael S. Tsirkin assert(!pc->subsystem_vendor_id);
1231315a1350SMichael S. Tsirkin assert(!pc->subsystem_id);
1232315a1350SMichael S. Tsirkin }
1233315a1350SMichael S. Tsirkin pci_init_cmask(pci_dev);
1234315a1350SMichael S. Tsirkin pci_init_wmask(pci_dev);
1235315a1350SMichael S. Tsirkin pci_init_w1cmask(pci_dev);
1236ad494274SIgor Mammedov if (is_bridge) {
1237315a1350SMichael S. Tsirkin pci_init_mask_bridge(pci_dev);
1238315a1350SMichael S. Tsirkin }
1239133e9b22SMarkus Armbruster pci_init_multifunction(bus, pci_dev, &local_err);
1240133e9b22SMarkus Armbruster if (local_err) {
1241133e9b22SMarkus Armbruster error_propagate(errp, local_err);
124230607764SMarcel Apfelbaum do_pci_unregister_device(pci_dev);
1243315a1350SMichael S. Tsirkin return NULL;
1244315a1350SMichael S. Tsirkin }
1245315a1350SMichael S. Tsirkin
1246315a1350SMichael S. Tsirkin if (!config_read)
1247315a1350SMichael S. Tsirkin config_read = pci_default_read_config;
1248315a1350SMichael S. Tsirkin if (!config_write)
1249315a1350SMichael S. Tsirkin config_write = pci_default_write_config;
1250315a1350SMichael S. Tsirkin pci_dev->config_read = config_read;
1251315a1350SMichael S. Tsirkin pci_dev->config_write = config_write;
1252315a1350SMichael S. Tsirkin bus->devices[devfn] = pci_dev;
1253315a1350SMichael S. Tsirkin pci_dev->version_id = 2; /* Current pci device vmstate version */
1254315a1350SMichael S. Tsirkin return pci_dev;
1255315a1350SMichael S. Tsirkin }
1256315a1350SMichael S. Tsirkin
pci_unregister_io_regions(PCIDevice * pci_dev)1257315a1350SMichael S. Tsirkin static void pci_unregister_io_regions(PCIDevice *pci_dev)
1258315a1350SMichael S. Tsirkin {
1259315a1350SMichael S. Tsirkin PCIIORegion *r;
1260315a1350SMichael S. Tsirkin int i;
1261315a1350SMichael S. Tsirkin
1262315a1350SMichael S. Tsirkin for(i = 0; i < PCI_NUM_REGIONS; i++) {
1263315a1350SMichael S. Tsirkin r = &pci_dev->io_regions[i];
1264315a1350SMichael S. Tsirkin if (!r->size || r->addr == PCI_BAR_UNMAPPED)
1265315a1350SMichael S. Tsirkin continue;
1266315a1350SMichael S. Tsirkin memory_region_del_subregion(r->address_space, r->memory);
1267315a1350SMichael S. Tsirkin }
1268e01fd687SAlex Williamson
1269e01fd687SAlex Williamson pci_unregister_vga(pci_dev);
1270315a1350SMichael S. Tsirkin }
1271315a1350SMichael S. Tsirkin
pci_qdev_unrealize(DeviceState * dev)1272b69c3c21SMarkus Armbruster static void pci_qdev_unrealize(DeviceState *dev)
1273315a1350SMichael S. Tsirkin {
1274315a1350SMichael S. Tsirkin PCIDevice *pci_dev = PCI_DEVICE(dev);
1275315a1350SMichael S. Tsirkin PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
1276315a1350SMichael S. Tsirkin
1277315a1350SMichael S. Tsirkin pci_unregister_io_regions(pci_dev);
1278315a1350SMichael S. Tsirkin pci_del_option_rom(pci_dev);
1279315a1350SMichael S. Tsirkin
1280315a1350SMichael S. Tsirkin if (pc->exit) {
1281315a1350SMichael S. Tsirkin pc->exit(pci_dev);
1282315a1350SMichael S. Tsirkin }
1283315a1350SMichael S. Tsirkin
12843936161fSHerongguang (Stephen) pci_device_deassert_intx(pci_dev);
1285315a1350SMichael S. Tsirkin do_pci_unregister_device(pci_dev);
128608cf3dc6SJagannathan Raman
128708cf3dc6SJagannathan Raman pci_dev->msi_trigger = NULL;
1288041b1c40SIgor Mammedov
1289041b1c40SIgor Mammedov /*
1290041b1c40SIgor Mammedov * clean up acpi-index so it could reused by another device
1291041b1c40SIgor Mammedov */
1292041b1c40SIgor Mammedov if (pci_dev->acpi_index) {
1293041b1c40SIgor Mammedov GSequence *used_indexes = pci_acpi_index_list();
1294041b1c40SIgor Mammedov
1295041b1c40SIgor Mammedov g_sequence_remove(g_sequence_lookup(used_indexes,
1296041b1c40SIgor Mammedov GINT_TO_POINTER(pci_dev->acpi_index),
1297041b1c40SIgor Mammedov g_cmp_uint32, NULL));
1298041b1c40SIgor Mammedov }
1299315a1350SMichael S. Tsirkin }
1300315a1350SMichael S. Tsirkin
pci_register_bar(PCIDevice * pci_dev,int region_num,uint8_t type,MemoryRegion * memory)1301315a1350SMichael S. Tsirkin void pci_register_bar(PCIDevice *pci_dev, int region_num,
1302315a1350SMichael S. Tsirkin uint8_t type, MemoryRegion *memory)
1303315a1350SMichael S. Tsirkin {
1304315a1350SMichael S. Tsirkin PCIIORegion *r;
13055178ecd8SCao jin uint32_t addr; /* offset in pci config space */
1306315a1350SMichael S. Tsirkin uint64_t wmask;
1307315a1350SMichael S. Tsirkin pcibus_t size = memory_region_size(memory);
13086a5b19caSBen Widawsky uint8_t hdr_type;
1309315a1350SMichael S. Tsirkin
1310aa01c491SMichael S. Tsirkin assert(!pci_is_vf(pci_dev)); /* VFs must use pcie_sriov_vf_register_bar */
1311315a1350SMichael S. Tsirkin assert(region_num >= 0);
1312315a1350SMichael S. Tsirkin assert(region_num < PCI_NUM_REGIONS);
13132c729dc8SBen Widawsky assert(is_power_of_2(size));
1314315a1350SMichael S. Tsirkin
13156a5b19caSBen Widawsky /* A PCI bridge device (with Type 1 header) may only have at most 2 BARs */
13166a5b19caSBen Widawsky hdr_type =
13176a5b19caSBen Widawsky pci_dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
13186a5b19caSBen Widawsky assert(hdr_type != PCI_HEADER_TYPE_BRIDGE || region_num < 2);
13196a5b19caSBen Widawsky
1320315a1350SMichael S. Tsirkin r = &pci_dev->io_regions[region_num];
1321aa01c491SMichael S. Tsirkin r->addr = PCI_BAR_UNMAPPED;
1322315a1350SMichael S. Tsirkin r->size = size;
1323315a1350SMichael S. Tsirkin r->type = type;
13245178ecd8SCao jin r->memory = memory;
13255178ecd8SCao jin r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO
1326fd56e061SDavid Gibson ? pci_get_bus(pci_dev)->address_space_io
1327fd56e061SDavid Gibson : pci_get_bus(pci_dev)->address_space_mem;
1328315a1350SMichael S. Tsirkin
1329315a1350SMichael S. Tsirkin wmask = ~(size - 1);
1330315a1350SMichael S. Tsirkin if (region_num == PCI_ROM_SLOT) {
1331315a1350SMichael S. Tsirkin /* ROM enable bit is writable */
1332315a1350SMichael S. Tsirkin wmask |= PCI_ROM_ADDRESS_ENABLE;
1333315a1350SMichael S. Tsirkin }
13345178ecd8SCao jin
13355178ecd8SCao jin addr = pci_bar(pci_dev, region_num);
1336315a1350SMichael S. Tsirkin pci_set_long(pci_dev->config + addr, type);
13375178ecd8SCao jin
1338315a1350SMichael S. Tsirkin if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
1339315a1350SMichael S. Tsirkin r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1340315a1350SMichael S. Tsirkin pci_set_quad(pci_dev->wmask + addr, wmask);
1341315a1350SMichael S. Tsirkin pci_set_quad(pci_dev->cmask + addr, ~0ULL);
1342315a1350SMichael S. Tsirkin } else {
1343315a1350SMichael S. Tsirkin pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
1344315a1350SMichael S. Tsirkin pci_set_long(pci_dev->cmask + addr, 0xffffffff);
1345315a1350SMichael S. Tsirkin }
1346315a1350SMichael S. Tsirkin }
1347315a1350SMichael S. Tsirkin
pci_update_vga(PCIDevice * pci_dev)1348e01fd687SAlex Williamson static void pci_update_vga(PCIDevice *pci_dev)
1349e01fd687SAlex Williamson {
1350e01fd687SAlex Williamson uint16_t cmd;
1351e01fd687SAlex Williamson
1352e01fd687SAlex Williamson if (!pci_dev->has_vga) {
1353e01fd687SAlex Williamson return;
1354e01fd687SAlex Williamson }
1355e01fd687SAlex Williamson
1356e01fd687SAlex Williamson cmd = pci_get_word(pci_dev->config + PCI_COMMAND);
1357e01fd687SAlex Williamson
1358e01fd687SAlex Williamson memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM],
1359e01fd687SAlex Williamson cmd & PCI_COMMAND_MEMORY);
1360e01fd687SAlex Williamson memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO],
1361e01fd687SAlex Williamson cmd & PCI_COMMAND_IO);
1362e01fd687SAlex Williamson memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI],
1363e01fd687SAlex Williamson cmd & PCI_COMMAND_IO);
1364e01fd687SAlex Williamson }
1365e01fd687SAlex Williamson
pci_register_vga(PCIDevice * pci_dev,MemoryRegion * mem,MemoryRegion * io_lo,MemoryRegion * io_hi)1366e01fd687SAlex Williamson void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
1367e01fd687SAlex Williamson MemoryRegion *io_lo, MemoryRegion *io_hi)
1368e01fd687SAlex Williamson {
1369fd56e061SDavid Gibson PCIBus *bus = pci_get_bus(pci_dev);
1370fd56e061SDavid Gibson
1371e01fd687SAlex Williamson assert(!pci_dev->has_vga);
1372e01fd687SAlex Williamson
1373e01fd687SAlex Williamson assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE);
1374e01fd687SAlex Williamson pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem;
1375fd56e061SDavid Gibson memory_region_add_subregion_overlap(bus->address_space_mem,
1376e01fd687SAlex Williamson QEMU_PCI_VGA_MEM_BASE, mem, 1);
1377e01fd687SAlex Williamson
1378e01fd687SAlex Williamson assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE);
1379e01fd687SAlex Williamson pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo;
1380fd56e061SDavid Gibson memory_region_add_subregion_overlap(bus->address_space_io,
1381e01fd687SAlex Williamson QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1);
1382e01fd687SAlex Williamson
1383e01fd687SAlex Williamson assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE);
1384e01fd687SAlex Williamson pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi;
1385fd56e061SDavid Gibson memory_region_add_subregion_overlap(bus->address_space_io,
1386e01fd687SAlex Williamson QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1);
1387e01fd687SAlex Williamson pci_dev->has_vga = true;
1388e01fd687SAlex Williamson
1389e01fd687SAlex Williamson pci_update_vga(pci_dev);
1390e01fd687SAlex Williamson }
1391e01fd687SAlex Williamson
pci_unregister_vga(PCIDevice * pci_dev)1392e01fd687SAlex Williamson void pci_unregister_vga(PCIDevice *pci_dev)
1393e01fd687SAlex Williamson {
1394fd56e061SDavid Gibson PCIBus *bus = pci_get_bus(pci_dev);
1395fd56e061SDavid Gibson
1396e01fd687SAlex Williamson if (!pci_dev->has_vga) {
1397e01fd687SAlex Williamson return;
1398e01fd687SAlex Williamson }
1399e01fd687SAlex Williamson
1400fd56e061SDavid Gibson memory_region_del_subregion(bus->address_space_mem,
1401e01fd687SAlex Williamson pci_dev->vga_regions[QEMU_PCI_VGA_MEM]);
1402fd56e061SDavid Gibson memory_region_del_subregion(bus->address_space_io,
1403e01fd687SAlex Williamson pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]);
1404fd56e061SDavid Gibson memory_region_del_subregion(bus->address_space_io,
1405e01fd687SAlex Williamson pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]);
1406e01fd687SAlex Williamson pci_dev->has_vga = false;
1407e01fd687SAlex Williamson }
1408e01fd687SAlex Williamson
pci_get_bar_addr(PCIDevice * pci_dev,int region_num)1409315a1350SMichael S. Tsirkin pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
1410315a1350SMichael S. Tsirkin {
1411315a1350SMichael S. Tsirkin return pci_dev->io_regions[region_num].addr;
1412315a1350SMichael S. Tsirkin }
1413315a1350SMichael S. Tsirkin
pci_config_get_bar_addr(PCIDevice * d,int reg,uint8_t type,pcibus_t size)14147c0fa8dfSKnut Omang static pcibus_t pci_config_get_bar_addr(PCIDevice *d, int reg,
14157c0fa8dfSKnut Omang uint8_t type, pcibus_t size)
14167c0fa8dfSKnut Omang {
14177c0fa8dfSKnut Omang pcibus_t new_addr;
14187c0fa8dfSKnut Omang if (!pci_is_vf(d)) {
14197c0fa8dfSKnut Omang int bar = pci_bar(d, reg);
14207c0fa8dfSKnut Omang if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
14217c0fa8dfSKnut Omang new_addr = pci_get_quad(d->config + bar);
14227c0fa8dfSKnut Omang } else {
14237c0fa8dfSKnut Omang new_addr = pci_get_long(d->config + bar);
14247c0fa8dfSKnut Omang }
14257c0fa8dfSKnut Omang } else {
14267c0fa8dfSKnut Omang PCIDevice *pf = d->exp.sriov_vf.pf;
14277c0fa8dfSKnut Omang uint16_t sriov_cap = pf->exp.sriov_cap;
14287c0fa8dfSKnut Omang int bar = sriov_cap + PCI_SRIOV_BAR + reg * 4;
14297c0fa8dfSKnut Omang uint16_t vf_offset =
14307c0fa8dfSKnut Omang pci_get_word(pf->config + sriov_cap + PCI_SRIOV_VF_OFFSET);
14317c0fa8dfSKnut Omang uint16_t vf_stride =
14327c0fa8dfSKnut Omang pci_get_word(pf->config + sriov_cap + PCI_SRIOV_VF_STRIDE);
143355845251SMichael S. Tsirkin uint32_t vf_num = (d->devfn - (pf->devfn + vf_offset)) / vf_stride;
14347c0fa8dfSKnut Omang
14357c0fa8dfSKnut Omang if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
14367c0fa8dfSKnut Omang new_addr = pci_get_quad(pf->config + bar);
14377c0fa8dfSKnut Omang } else {
14387c0fa8dfSKnut Omang new_addr = pci_get_long(pf->config + bar);
14397c0fa8dfSKnut Omang }
14407c0fa8dfSKnut Omang new_addr += vf_num * size;
14417c0fa8dfSKnut Omang }
14427c0fa8dfSKnut Omang /* The ROM slot has a specific enable bit, keep it intact */
14437c0fa8dfSKnut Omang if (reg != PCI_ROM_SLOT) {
14447c0fa8dfSKnut Omang new_addr &= ~(size - 1);
14457c0fa8dfSKnut Omang }
14467c0fa8dfSKnut Omang return new_addr;
14477c0fa8dfSKnut Omang }
14487c0fa8dfSKnut Omang
pci_bar_address(PCIDevice * d,int reg,uint8_t type,pcibus_t size)14497c0fa8dfSKnut Omang pcibus_t pci_bar_address(PCIDevice *d,
1450315a1350SMichael S. Tsirkin int reg, uint8_t type, pcibus_t size)
1451315a1350SMichael S. Tsirkin {
1452315a1350SMichael S. Tsirkin pcibus_t new_addr, last_addr;
1453315a1350SMichael S. Tsirkin uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
1454271233f2SPhilippe Mathieu-Daudé MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
1455e4024630SLaurent Vivier bool allow_0_address = mc->pci_allow_0_address;
1456315a1350SMichael S. Tsirkin
1457315a1350SMichael S. Tsirkin if (type & PCI_BASE_ADDRESS_SPACE_IO) {
1458315a1350SMichael S. Tsirkin if (!(cmd & PCI_COMMAND_IO)) {
1459315a1350SMichael S. Tsirkin return PCI_BAR_UNMAPPED;
1460315a1350SMichael S. Tsirkin }
14617c0fa8dfSKnut Omang new_addr = pci_config_get_bar_addr(d, reg, type, size);
1462315a1350SMichael S. Tsirkin last_addr = new_addr + size - 1;
14639f1a029aSHervé Poussineau /* Check if 32 bit BAR wraps around explicitly.
14649f1a029aSHervé Poussineau * TODO: make priorities correct and remove this work around.
14659f1a029aSHervé Poussineau */
1466e4024630SLaurent Vivier if (last_addr <= new_addr || last_addr >= UINT32_MAX ||
1467e4024630SLaurent Vivier (!allow_0_address && new_addr == 0)) {
1468315a1350SMichael S. Tsirkin return PCI_BAR_UNMAPPED;
1469315a1350SMichael S. Tsirkin }
1470315a1350SMichael S. Tsirkin return new_addr;
1471315a1350SMichael S. Tsirkin }
1472315a1350SMichael S. Tsirkin
1473315a1350SMichael S. Tsirkin if (!(cmd & PCI_COMMAND_MEMORY)) {
1474315a1350SMichael S. Tsirkin return PCI_BAR_UNMAPPED;
1475315a1350SMichael S. Tsirkin }
14767c0fa8dfSKnut Omang new_addr = pci_config_get_bar_addr(d, reg, type, size);
1477315a1350SMichael S. Tsirkin /* the ROM slot has a specific enable bit */
1478315a1350SMichael S. Tsirkin if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
1479315a1350SMichael S. Tsirkin return PCI_BAR_UNMAPPED;
1480315a1350SMichael S. Tsirkin }
1481315a1350SMichael S. Tsirkin new_addr &= ~(size - 1);
1482315a1350SMichael S. Tsirkin last_addr = new_addr + size - 1;
1483315a1350SMichael S. Tsirkin /* NOTE: we do not support wrapping */
1484315a1350SMichael S. Tsirkin /* XXX: as we cannot support really dynamic
1485315a1350SMichael S. Tsirkin mappings, we handle specific values as invalid
1486315a1350SMichael S. Tsirkin mappings. */
1487e4024630SLaurent Vivier if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED ||
1488e4024630SLaurent Vivier (!allow_0_address && new_addr == 0)) {
1489315a1350SMichael S. Tsirkin return PCI_BAR_UNMAPPED;
1490315a1350SMichael S. Tsirkin }
1491315a1350SMichael S. Tsirkin
1492315a1350SMichael S. Tsirkin /* Now pcibus_t is 64bit.
1493315a1350SMichael S. Tsirkin * Check if 32 bit BAR wraps around explicitly.
1494315a1350SMichael S. Tsirkin * Without this, PC ide doesn't work well.
1495315a1350SMichael S. Tsirkin * TODO: remove this work around.
1496315a1350SMichael S. Tsirkin */
1497315a1350SMichael S. Tsirkin if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
1498315a1350SMichael S. Tsirkin return PCI_BAR_UNMAPPED;
1499315a1350SMichael S. Tsirkin }
1500315a1350SMichael S. Tsirkin
1501315a1350SMichael S. Tsirkin /*
1502315a1350SMichael S. Tsirkin * OS is allowed to set BAR beyond its addressable
1503315a1350SMichael S. Tsirkin * bits. For example, 32 bit OS can set 64bit bar
1504315a1350SMichael S. Tsirkin * to >4G. Check it. TODO: we might need to support
1505315a1350SMichael S. Tsirkin * it in the future for e.g. PAE.
1506315a1350SMichael S. Tsirkin */
1507315a1350SMichael S. Tsirkin if (last_addr >= HWADDR_MAX) {
1508315a1350SMichael S. Tsirkin return PCI_BAR_UNMAPPED;
1509315a1350SMichael S. Tsirkin }
1510315a1350SMichael S. Tsirkin
1511315a1350SMichael S. Tsirkin return new_addr;
1512315a1350SMichael S. Tsirkin }
1513315a1350SMichael S. Tsirkin
pci_update_mappings(PCIDevice * d)1514315a1350SMichael S. Tsirkin static void pci_update_mappings(PCIDevice *d)
1515315a1350SMichael S. Tsirkin {
1516315a1350SMichael S. Tsirkin PCIIORegion *r;
1517315a1350SMichael S. Tsirkin int i;
1518315a1350SMichael S. Tsirkin pcibus_t new_addr;
1519315a1350SMichael S. Tsirkin
1520315a1350SMichael S. Tsirkin for(i = 0; i < PCI_NUM_REGIONS; i++) {
1521315a1350SMichael S. Tsirkin r = &d->io_regions[i];
1522315a1350SMichael S. Tsirkin
1523315a1350SMichael S. Tsirkin /* this region isn't registered */
1524315a1350SMichael S. Tsirkin if (!r->size)
1525315a1350SMichael S. Tsirkin continue;
1526315a1350SMichael S. Tsirkin
1527315a1350SMichael S. Tsirkin new_addr = pci_bar_address(d, i, r->type, r->size);
1528*93829009SMichael S. Tsirkin if (!d->has_power) {
152923786d13SGerd Hoffmann new_addr = PCI_BAR_UNMAPPED;
153023786d13SGerd Hoffmann }
1531315a1350SMichael S. Tsirkin
1532315a1350SMichael S. Tsirkin /* This bar isn't changed */
1533315a1350SMichael S. Tsirkin if (new_addr == r->addr)
1534315a1350SMichael S. Tsirkin continue;
1535315a1350SMichael S. Tsirkin
1536315a1350SMichael S. Tsirkin /* now do the real mapping */
1537315a1350SMichael S. Tsirkin if (r->addr != PCI_BAR_UNMAPPED) {
1538deeb956cSLaurent Vivier trace_pci_update_mappings_del(d->name, pci_dev_bus_num(d),
15397828d750SDon Koch PCI_SLOT(d->devfn),
15400f288f85SLaszlo Ersek PCI_FUNC(d->devfn),
15417828d750SDon Koch i, r->addr, r->size);
1542315a1350SMichael S. Tsirkin memory_region_del_subregion(r->address_space, r->memory);
1543315a1350SMichael S. Tsirkin }
1544315a1350SMichael S. Tsirkin r->addr = new_addr;
1545315a1350SMichael S. Tsirkin if (r->addr != PCI_BAR_UNMAPPED) {
1546deeb956cSLaurent Vivier trace_pci_update_mappings_add(d->name, pci_dev_bus_num(d),
15477828d750SDon Koch PCI_SLOT(d->devfn),
15480f288f85SLaszlo Ersek PCI_FUNC(d->devfn),
15497828d750SDon Koch i, r->addr, r->size);
1550315a1350SMichael S. Tsirkin memory_region_add_subregion_overlap(r->address_space,
1551315a1350SMichael S. Tsirkin r->addr, r->memory, 1);
1552315a1350SMichael S. Tsirkin }
1553315a1350SMichael S. Tsirkin }
1554e01fd687SAlex Williamson
1555e01fd687SAlex Williamson pci_update_vga(d);
1556315a1350SMichael S. Tsirkin }
1557315a1350SMichael S. Tsirkin
pci_irq_disabled(PCIDevice * d)1558315a1350SMichael S. Tsirkin static inline int pci_irq_disabled(PCIDevice *d)
1559315a1350SMichael S. Tsirkin {
1560315a1350SMichael S. Tsirkin return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1561315a1350SMichael S. Tsirkin }
1562315a1350SMichael S. Tsirkin
1563315a1350SMichael S. Tsirkin /* Called after interrupt disabled field update in config space,
1564315a1350SMichael S. Tsirkin * assert/deassert interrupts if necessary.
1565315a1350SMichael S. Tsirkin * Gets original interrupt disable bit value (before update). */
pci_update_irq_disabled(PCIDevice * d,int was_irq_disabled)1566315a1350SMichael S. Tsirkin static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1567315a1350SMichael S. Tsirkin {
1568315a1350SMichael S. Tsirkin int i, disabled = pci_irq_disabled(d);
1569315a1350SMichael S. Tsirkin if (disabled == was_irq_disabled)
1570315a1350SMichael S. Tsirkin return;
1571315a1350SMichael S. Tsirkin for (i = 0; i < PCI_NUM_PINS; ++i) {
1572315a1350SMichael S. Tsirkin int state = pci_irq_state(d, i);
1573315a1350SMichael S. Tsirkin pci_change_irq_level(d, i, disabled ? -state : state);
1574315a1350SMichael S. Tsirkin }
1575315a1350SMichael S. Tsirkin }
1576315a1350SMichael S. Tsirkin
pci_default_read_config(PCIDevice * d,uint32_t address,int len)1577315a1350SMichael S. Tsirkin uint32_t pci_default_read_config(PCIDevice *d,
1578315a1350SMichael S. Tsirkin uint32_t address, int len)
1579315a1350SMichael S. Tsirkin {
1580315a1350SMichael S. Tsirkin uint32_t val = 0;
1581315a1350SMichael S. Tsirkin
1582f7d6a635SPrasad J Pandit assert(address + len <= pci_config_size(d));
1583f7d6a635SPrasad J Pandit
1584727b4866SAlex Williamson if (pci_is_express_downstream_port(d) &&
1585727b4866SAlex Williamson ranges_overlap(address, len, d->exp.exp_cap + PCI_EXP_LNKSTA, 2)) {
1586727b4866SAlex Williamson pcie_sync_bridge_lnk(d);
1587727b4866SAlex Williamson }
1588315a1350SMichael S. Tsirkin memcpy(&val, d->config + address, len);
1589315a1350SMichael S. Tsirkin return le32_to_cpu(val);
1590315a1350SMichael S. Tsirkin }
1591315a1350SMichael S. Tsirkin
pci_default_write_config(PCIDevice * d,uint32_t addr,uint32_t val_in,int l)1592d7efb7e0SKnut Omang void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l)
1593315a1350SMichael S. Tsirkin {
1594315a1350SMichael S. Tsirkin int i, was_irq_disabled = pci_irq_disabled(d);
1595d7efb7e0SKnut Omang uint32_t val = val_in;
1596315a1350SMichael S. Tsirkin
1597f7d6a635SPrasad J Pandit assert(addr + l <= pci_config_size(d));
1598f7d6a635SPrasad J Pandit
1599315a1350SMichael S. Tsirkin for (i = 0; i < l; val >>= 8, ++i) {
1600315a1350SMichael S. Tsirkin uint8_t wmask = d->wmask[addr + i];
1601315a1350SMichael S. Tsirkin uint8_t w1cmask = d->w1cmask[addr + i];
1602315a1350SMichael S. Tsirkin assert(!(wmask & w1cmask));
1603315a1350SMichael S. Tsirkin d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1604315a1350SMichael S. Tsirkin d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1605315a1350SMichael S. Tsirkin }
1606315a1350SMichael S. Tsirkin if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1607315a1350SMichael S. Tsirkin ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1608315a1350SMichael S. Tsirkin ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1609315a1350SMichael S. Tsirkin range_covers_byte(addr, l, PCI_COMMAND))
1610315a1350SMichael S. Tsirkin pci_update_mappings(d);
1611315a1350SMichael S. Tsirkin
16120f936247SGuoyi Tu if (ranges_overlap(addr, l, PCI_COMMAND, 2)) {
1613315a1350SMichael S. Tsirkin pci_update_irq_disabled(d, was_irq_disabled);
1614315a1350SMichael S. Tsirkin memory_region_set_enabled(&d->bus_master_enable_region,
161523786d13SGerd Hoffmann (pci_get_word(d->config + PCI_COMMAND)
1616*93829009SMichael S. Tsirkin & PCI_COMMAND_MASTER) && d->has_power);
1617315a1350SMichael S. Tsirkin }
1618315a1350SMichael S. Tsirkin
1619d7efb7e0SKnut Omang msi_write_config(d, addr, val_in, l);
1620d7efb7e0SKnut Omang msix_write_config(d, addr, val_in, l);
16217c0fa8dfSKnut Omang pcie_sriov_config_write(d, addr, val_in, l);
1622315a1350SMichael S. Tsirkin }
1623315a1350SMichael S. Tsirkin
1624315a1350SMichael S. Tsirkin /***********************************************************/
1625315a1350SMichael S. Tsirkin /* generic PCI irq support */
1626315a1350SMichael S. Tsirkin
1627315a1350SMichael S. Tsirkin /* 0 <= irq_num <= 3. level must be 0 or 1 */
pci_irq_handler(void * opaque,int irq_num,int level)1628d98f08f5SMarcel Apfelbaum static void pci_irq_handler(void *opaque, int irq_num, int level)
1629315a1350SMichael S. Tsirkin {
1630315a1350SMichael S. Tsirkin PCIDevice *pci_dev = opaque;
1631315a1350SMichael S. Tsirkin int change;
1632315a1350SMichael S. Tsirkin
16338ddf5432SIsaku Yamahata assert(0 <= irq_num && irq_num < PCI_NUM_PINS);
16348ddf5432SIsaku Yamahata assert(level == 0 || level == 1);
1635315a1350SMichael S. Tsirkin change = level - pci_irq_state(pci_dev, irq_num);
1636315a1350SMichael S. Tsirkin if (!change)
1637315a1350SMichael S. Tsirkin return;
1638315a1350SMichael S. Tsirkin
1639315a1350SMichael S. Tsirkin pci_set_irq_state(pci_dev, irq_num, level);
1640315a1350SMichael S. Tsirkin pci_update_irq_status(pci_dev);
1641315a1350SMichael S. Tsirkin if (pci_irq_disabled(pci_dev))
1642315a1350SMichael S. Tsirkin return;
1643315a1350SMichael S. Tsirkin pci_change_irq_level(pci_dev, irq_num, change);
1644315a1350SMichael S. Tsirkin }
1645315a1350SMichael S. Tsirkin
pci_allocate_irq(PCIDevice * pci_dev)1646d98f08f5SMarcel Apfelbaum qemu_irq pci_allocate_irq(PCIDevice *pci_dev)
1647d98f08f5SMarcel Apfelbaum {
1648d98f08f5SMarcel Apfelbaum int intx = pci_intx(pci_dev);
16498ddf5432SIsaku Yamahata assert(0 <= intx && intx < PCI_NUM_PINS);
1650d98f08f5SMarcel Apfelbaum
1651d98f08f5SMarcel Apfelbaum return qemu_allocate_irq(pci_irq_handler, pci_dev, intx);
1652d98f08f5SMarcel Apfelbaum }
1653d98f08f5SMarcel Apfelbaum
pci_set_irq(PCIDevice * pci_dev,int level)1654d98f08f5SMarcel Apfelbaum void pci_set_irq(PCIDevice *pci_dev, int level)
1655d98f08f5SMarcel Apfelbaum {
1656d98f08f5SMarcel Apfelbaum int intx = pci_intx(pci_dev);
1657d98f08f5SMarcel Apfelbaum pci_irq_handler(pci_dev, intx, level);
1658d98f08f5SMarcel Apfelbaum }
1659d98f08f5SMarcel Apfelbaum
1660315a1350SMichael S. Tsirkin /* Special hooks used by device assignment */
pci_bus_set_route_irq_fn(PCIBus * bus,pci_route_irq_fn route_intx_to_irq)1661315a1350SMichael S. Tsirkin void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq)
1662315a1350SMichael S. Tsirkin {
16630889464aSAlex Williamson assert(pci_bus_is_root(bus));
1664315a1350SMichael S. Tsirkin bus->route_intx_to_irq = route_intx_to_irq;
1665315a1350SMichael S. Tsirkin }
1666315a1350SMichael S. Tsirkin
pci_device_route_intx_to_irq(PCIDevice * dev,int pin)1667315a1350SMichael S. Tsirkin PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin)
1668315a1350SMichael S. Tsirkin {
1669315a1350SMichael S. Tsirkin PCIBus *bus;
1670315a1350SMichael S. Tsirkin
1671315a1350SMichael S. Tsirkin do {
167228566eabSPhilippe Mathieu-Daudé int dev_irq = pin;
1673fd56e061SDavid Gibson bus = pci_get_bus(dev);
1674315a1350SMichael S. Tsirkin pin = bus->map_irq(dev, pin);
167528566eabSPhilippe Mathieu-Daudé trace_pci_route_irq(dev_irq, DEVICE(dev)->canonical_path, pin,
167628566eabSPhilippe Mathieu-Daudé pci_bus_is_root(bus) ? "root-complex"
167728566eabSPhilippe Mathieu-Daudé : DEVICE(bus->parent_dev)->canonical_path);
1678315a1350SMichael S. Tsirkin dev = bus->parent_dev;
1679315a1350SMichael S. Tsirkin } while (dev);
1680315a1350SMichael S. Tsirkin
1681315a1350SMichael S. Tsirkin if (!bus->route_intx_to_irq) {
1682312fd5f2SMarkus Armbruster error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
1683315a1350SMichael S. Tsirkin object_get_typename(OBJECT(bus->qbus.parent)));
1684315a1350SMichael S. Tsirkin return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 };
1685315a1350SMichael S. Tsirkin }
1686315a1350SMichael S. Tsirkin
1687315a1350SMichael S. Tsirkin return bus->route_intx_to_irq(bus->irq_opaque, pin);
1688315a1350SMichael S. Tsirkin }
1689315a1350SMichael S. Tsirkin
pci_intx_route_changed(PCIINTxRoute * old,PCIINTxRoute * new)1690315a1350SMichael S. Tsirkin bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new)
1691315a1350SMichael S. Tsirkin {
1692315a1350SMichael S. Tsirkin return old->mode != new->mode || old->irq != new->irq;
1693315a1350SMichael S. Tsirkin }
1694315a1350SMichael S. Tsirkin
pci_bus_fire_intx_routing_notifier(PCIBus * bus)1695315a1350SMichael S. Tsirkin void pci_bus_fire_intx_routing_notifier(PCIBus *bus)
1696315a1350SMichael S. Tsirkin {
1697315a1350SMichael S. Tsirkin PCIDevice *dev;
1698315a1350SMichael S. Tsirkin PCIBus *sec;
1699315a1350SMichael S. Tsirkin int i;
1700315a1350SMichael S. Tsirkin
1701315a1350SMichael S. Tsirkin for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1702315a1350SMichael S. Tsirkin dev = bus->devices[i];
1703315a1350SMichael S. Tsirkin if (dev && dev->intx_routing_notifier) {
1704315a1350SMichael S. Tsirkin dev->intx_routing_notifier(dev);
1705315a1350SMichael S. Tsirkin }
1706e5368f0dSAlex Williamson }
1707e5368f0dSAlex Williamson
1708315a1350SMichael S. Tsirkin QLIST_FOREACH(sec, &bus->child, sibling) {
1709315a1350SMichael S. Tsirkin pci_bus_fire_intx_routing_notifier(sec);
1710315a1350SMichael S. Tsirkin }
1711315a1350SMichael S. Tsirkin }
1712315a1350SMichael S. Tsirkin
pci_device_set_intx_routing_notifier(PCIDevice * dev,PCIINTxRoutingNotifier notifier)1713315a1350SMichael S. Tsirkin void pci_device_set_intx_routing_notifier(PCIDevice *dev,
1714315a1350SMichael S. Tsirkin PCIINTxRoutingNotifier notifier)
1715315a1350SMichael S. Tsirkin {
1716315a1350SMichael S. Tsirkin dev->intx_routing_notifier = notifier;
1717315a1350SMichael S. Tsirkin }
1718315a1350SMichael S. Tsirkin
1719315a1350SMichael S. Tsirkin /*
1720315a1350SMichael S. Tsirkin * PCI-to-PCI bridge specification
1721315a1350SMichael S. Tsirkin * 9.1: Interrupt routing. Table 9-1
1722315a1350SMichael S. Tsirkin *
1723315a1350SMichael S. Tsirkin * the PCI Express Base Specification, Revision 2.1
17249d724e0bSPhilippe Mathieu-Daudé * 2.2.8.1: INTx interrupt signaling - Rules
1725315a1350SMichael S. Tsirkin * the Implementation Note
1726315a1350SMichael S. Tsirkin * Table 2-20
1727315a1350SMichael S. Tsirkin */
1728315a1350SMichael S. Tsirkin /*
1729315a1350SMichael S. Tsirkin * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
1730315a1350SMichael S. Tsirkin * 0-origin unlike PCI interrupt pin register.
1731315a1350SMichael S. Tsirkin */
pci_swizzle_map_irq_fn(PCIDevice * pci_dev,int pin)1732315a1350SMichael S. Tsirkin int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin)
1733315a1350SMichael S. Tsirkin {
1734e8ec4adfSGreg Kurz return pci_swizzle(PCI_SLOT(pci_dev->devfn), pin);
1735315a1350SMichael S. Tsirkin }
1736315a1350SMichael S. Tsirkin
1737315a1350SMichael S. Tsirkin /***********************************************************/
1738315a1350SMichael S. Tsirkin /* monitor info on PCI */
1739315a1350SMichael S. Tsirkin
1740315a1350SMichael S. Tsirkin static const pci_class_desc pci_class_descriptions[] =
1741315a1350SMichael S. Tsirkin {
1742315a1350SMichael S. Tsirkin { 0x0001, "VGA controller", "display"},
1743315a1350SMichael S. Tsirkin { 0x0100, "SCSI controller", "scsi"},
1744315a1350SMichael S. Tsirkin { 0x0101, "IDE controller", "ide"},
1745315a1350SMichael S. Tsirkin { 0x0102, "Floppy controller", "fdc"},
1746315a1350SMichael S. Tsirkin { 0x0103, "IPI controller", "ipi"},
1747315a1350SMichael S. Tsirkin { 0x0104, "RAID controller", "raid"},
1748315a1350SMichael S. Tsirkin { 0x0106, "SATA controller"},
1749315a1350SMichael S. Tsirkin { 0x0107, "SAS controller"},
1750315a1350SMichael S. Tsirkin { 0x0180, "Storage controller"},
1751315a1350SMichael S. Tsirkin { 0x0200, "Ethernet controller", "ethernet"},
1752315a1350SMichael S. Tsirkin { 0x0201, "Token Ring controller", "token-ring"},
1753315a1350SMichael S. Tsirkin { 0x0202, "FDDI controller", "fddi"},
1754315a1350SMichael S. Tsirkin { 0x0203, "ATM controller", "atm"},
1755315a1350SMichael S. Tsirkin { 0x0280, "Network controller"},
1756315a1350SMichael S. Tsirkin { 0x0300, "VGA controller", "display", 0x00ff},
1757315a1350SMichael S. Tsirkin { 0x0301, "XGA controller"},
1758315a1350SMichael S. Tsirkin { 0x0302, "3D controller"},
1759315a1350SMichael S. Tsirkin { 0x0380, "Display controller"},
1760315a1350SMichael S. Tsirkin { 0x0400, "Video controller", "video"},
1761315a1350SMichael S. Tsirkin { 0x0401, "Audio controller", "sound"},
1762315a1350SMichael S. Tsirkin { 0x0402, "Phone"},
1763315a1350SMichael S. Tsirkin { 0x0403, "Audio controller", "sound"},
1764315a1350SMichael S. Tsirkin { 0x0480, "Multimedia controller"},
1765315a1350SMichael S. Tsirkin { 0x0500, "RAM controller", "memory"},
1766315a1350SMichael S. Tsirkin { 0x0501, "Flash controller", "flash"},
1767315a1350SMichael S. Tsirkin { 0x0580, "Memory controller"},
1768315a1350SMichael S. Tsirkin { 0x0600, "Host bridge", "host"},
1769315a1350SMichael S. Tsirkin { 0x0601, "ISA bridge", "isa"},
1770315a1350SMichael S. Tsirkin { 0x0602, "EISA bridge", "eisa"},
1771315a1350SMichael S. Tsirkin { 0x0603, "MC bridge", "mca"},
17724c41425dSGerd Hoffmann { 0x0604, "PCI bridge", "pci-bridge"},
1773315a1350SMichael S. Tsirkin { 0x0605, "PCMCIA bridge", "pcmcia"},
1774315a1350SMichael S. Tsirkin { 0x0606, "NUBUS bridge", "nubus"},
1775315a1350SMichael S. Tsirkin { 0x0607, "CARDBUS bridge", "cardbus"},
1776315a1350SMichael S. Tsirkin { 0x0608, "RACEWAY bridge"},
1777315a1350SMichael S. Tsirkin { 0x0680, "Bridge"},
1778315a1350SMichael S. Tsirkin { 0x0700, "Serial port", "serial"},
1779315a1350SMichael S. Tsirkin { 0x0701, "Parallel port", "parallel"},
1780315a1350SMichael S. Tsirkin { 0x0800, "Interrupt controller", "interrupt-controller"},
1781315a1350SMichael S. Tsirkin { 0x0801, "DMA controller", "dma-controller"},
1782315a1350SMichael S. Tsirkin { 0x0802, "Timer", "timer"},
1783315a1350SMichael S. Tsirkin { 0x0803, "RTC", "rtc"},
1784315a1350SMichael S. Tsirkin { 0x0900, "Keyboard", "keyboard"},
1785315a1350SMichael S. Tsirkin { 0x0901, "Pen", "pen"},
1786315a1350SMichael S. Tsirkin { 0x0902, "Mouse", "mouse"},
1787315a1350SMichael S. Tsirkin { 0x0A00, "Dock station", "dock", 0x00ff},
1788315a1350SMichael S. Tsirkin { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1789d1e9e646SRebecca Cran { 0x0c00, "Firewire controller", "firewire"},
1790315a1350SMichael S. Tsirkin { 0x0c01, "Access bus controller", "access-bus"},
1791315a1350SMichael S. Tsirkin { 0x0c02, "SSA controller", "ssa"},
1792315a1350SMichael S. Tsirkin { 0x0c03, "USB controller", "usb"},
1793315a1350SMichael S. Tsirkin { 0x0c04, "Fibre channel controller", "fibre-channel"},
1794315a1350SMichael S. Tsirkin { 0x0c05, "SMBus"},
1795315a1350SMichael S. Tsirkin { 0, NULL}
1796315a1350SMichael S. Tsirkin };
1797315a1350SMichael S. Tsirkin
pci_for_each_device_under_bus_reverse(PCIBus * bus,pci_bus_dev_fn fn,void * opaque)17982914fc61SPeter Xu void pci_for_each_device_under_bus_reverse(PCIBus *bus,
1799b3dcf94fSPeter Xu pci_bus_dev_fn fn,
1800a8eeafdaSGreg Kurz void *opaque)
1801a8eeafdaSGreg Kurz {
1802a8eeafdaSGreg Kurz PCIDevice *d;
1803a8eeafdaSGreg Kurz int devfn;
1804a8eeafdaSGreg Kurz
1805a8eeafdaSGreg Kurz for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1806a8eeafdaSGreg Kurz d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn];
1807a8eeafdaSGreg Kurz if (d) {
1808a8eeafdaSGreg Kurz fn(bus, d, opaque);
1809a8eeafdaSGreg Kurz }
1810a8eeafdaSGreg Kurz }
1811a8eeafdaSGreg Kurz }
1812a8eeafdaSGreg Kurz
pci_for_each_device_reverse(PCIBus * bus,int bus_num,pci_bus_dev_fn fn,void * opaque)1813a8eeafdaSGreg Kurz void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
1814b3dcf94fSPeter Xu pci_bus_dev_fn fn, void *opaque)
1815a8eeafdaSGreg Kurz {
1816a8eeafdaSGreg Kurz bus = pci_find_bus_nr(bus, bus_num);
1817a8eeafdaSGreg Kurz
1818a8eeafdaSGreg Kurz if (bus) {
1819a8eeafdaSGreg Kurz pci_for_each_device_under_bus_reverse(bus, fn, opaque);
1820a8eeafdaSGreg Kurz }
1821a8eeafdaSGreg Kurz }
1822a8eeafdaSGreg Kurz
pci_for_each_device_under_bus(PCIBus * bus,pci_bus_dev_fn fn,void * opaque)18232914fc61SPeter Xu void pci_for_each_device_under_bus(PCIBus *bus,
1824b3dcf94fSPeter Xu pci_bus_dev_fn fn, void *opaque)
1825315a1350SMichael S. Tsirkin {
1826315a1350SMichael S. Tsirkin PCIDevice *d;
1827315a1350SMichael S. Tsirkin int devfn;
1828315a1350SMichael S. Tsirkin
1829315a1350SMichael S. Tsirkin for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1830315a1350SMichael S. Tsirkin d = bus->devices[devfn];
1831315a1350SMichael S. Tsirkin if (d) {
1832315a1350SMichael S. Tsirkin fn(bus, d, opaque);
1833315a1350SMichael S. Tsirkin }
1834315a1350SMichael S. Tsirkin }
1835315a1350SMichael S. Tsirkin }
1836315a1350SMichael S. Tsirkin
pci_for_each_device(PCIBus * bus,int bus_num,pci_bus_dev_fn fn,void * opaque)1837315a1350SMichael S. Tsirkin void pci_for_each_device(PCIBus *bus, int bus_num,
1838b3dcf94fSPeter Xu pci_bus_dev_fn fn, void *opaque)
1839315a1350SMichael S. Tsirkin {
1840315a1350SMichael S. Tsirkin bus = pci_find_bus_nr(bus, bus_num);
1841315a1350SMichael S. Tsirkin
1842315a1350SMichael S. Tsirkin if (bus) {
1843315a1350SMichael S. Tsirkin pci_for_each_device_under_bus(bus, fn, opaque);
1844315a1350SMichael S. Tsirkin }
1845315a1350SMichael S. Tsirkin }
1846315a1350SMichael S. Tsirkin
get_class_desc(int class)1847987b73b3SMarkus Armbruster const pci_class_desc *get_class_desc(int class)
1848315a1350SMichael S. Tsirkin {
1849315a1350SMichael S. Tsirkin const pci_class_desc *desc;
1850315a1350SMichael S. Tsirkin
1851315a1350SMichael S. Tsirkin desc = pci_class_descriptions;
1852315a1350SMichael S. Tsirkin while (desc->desc && class != desc->class) {
1853315a1350SMichael S. Tsirkin desc++;
1854315a1350SMichael S. Tsirkin }
1855315a1350SMichael S. Tsirkin
1856315a1350SMichael S. Tsirkin return desc;
1857315a1350SMichael S. Tsirkin }
1858315a1350SMichael S. Tsirkin
pci_init_nic_devices(PCIBus * bus,const char * default_model)18591785ae69SDavid Woodhouse void pci_init_nic_devices(PCIBus *bus, const char *default_model)
18601785ae69SDavid Woodhouse {
18611785ae69SDavid Woodhouse qemu_create_nic_bus_devices(&bus->qbus, TYPE_PCI_DEVICE, default_model,
18621785ae69SDavid Woodhouse "virtio", "virtio-net-pci");
18631785ae69SDavid Woodhouse }
18641785ae69SDavid Woodhouse
pci_init_nic_in_slot(PCIBus * rootbus,const char * model,const char * alias,const char * devaddr)18651785ae69SDavid Woodhouse bool pci_init_nic_in_slot(PCIBus *rootbus, const char *model,
18661785ae69SDavid Woodhouse const char *alias, const char *devaddr)
18671785ae69SDavid Woodhouse {
18681785ae69SDavid Woodhouse NICInfo *nd = qemu_find_nic_info(model, true, alias);
18691785ae69SDavid Woodhouse int dom, busnr, devfn;
18701785ae69SDavid Woodhouse PCIDevice *pci_dev;
18711785ae69SDavid Woodhouse unsigned slot;
18721785ae69SDavid Woodhouse PCIBus *bus;
18731785ae69SDavid Woodhouse
18741785ae69SDavid Woodhouse if (!nd) {
18751785ae69SDavid Woodhouse return false;
18761785ae69SDavid Woodhouse }
18771785ae69SDavid Woodhouse
18781785ae69SDavid Woodhouse if (!devaddr || pci_parse_devaddr(devaddr, &dom, &busnr, &slot, NULL) < 0) {
18791785ae69SDavid Woodhouse error_report("Invalid PCI device address %s for device %s",
18801785ae69SDavid Woodhouse devaddr, model);
18811785ae69SDavid Woodhouse exit(1);
18821785ae69SDavid Woodhouse }
18831785ae69SDavid Woodhouse
18841785ae69SDavid Woodhouse if (dom != 0) {
18851785ae69SDavid Woodhouse error_report("No support for non-zero PCI domains");
18861785ae69SDavid Woodhouse exit(1);
18871785ae69SDavid Woodhouse }
18881785ae69SDavid Woodhouse
18891785ae69SDavid Woodhouse devfn = PCI_DEVFN(slot, 0);
18901785ae69SDavid Woodhouse
18911785ae69SDavid Woodhouse bus = pci_find_bus_nr(rootbus, busnr);
18921785ae69SDavid Woodhouse if (!bus) {
18931785ae69SDavid Woodhouse error_report("Invalid PCI device address %s for device %s",
18941785ae69SDavid Woodhouse devaddr, model);
18951785ae69SDavid Woodhouse exit(1);
18961785ae69SDavid Woodhouse }
18971785ae69SDavid Woodhouse
18981785ae69SDavid Woodhouse pci_dev = pci_new(devfn, model);
18991785ae69SDavid Woodhouse qdev_set_nic_properties(&pci_dev->qdev, nd);
19001785ae69SDavid Woodhouse pci_realize_and_unref(pci_dev, bus, &error_fatal);
19011785ae69SDavid Woodhouse return true;
19021785ae69SDavid Woodhouse }
19031785ae69SDavid Woodhouse
pci_vga_init(PCIBus * bus)1904315a1350SMichael S. Tsirkin PCIDevice *pci_vga_init(PCIBus *bus)
1905315a1350SMichael S. Tsirkin {
1906f9bcb2d6SGautam Agrawal vga_interface_created = true;
1907315a1350SMichael S. Tsirkin switch (vga_interface_type) {
1908315a1350SMichael S. Tsirkin case VGA_CIRRUS:
1909315a1350SMichael S. Tsirkin return pci_create_simple(bus, -1, "cirrus-vga");
1910315a1350SMichael S. Tsirkin case VGA_QXL:
1911315a1350SMichael S. Tsirkin return pci_create_simple(bus, -1, "qxl-vga");
1912315a1350SMichael S. Tsirkin case VGA_STD:
1913315a1350SMichael S. Tsirkin return pci_create_simple(bus, -1, "VGA");
1914315a1350SMichael S. Tsirkin case VGA_VMWARE:
1915315a1350SMichael S. Tsirkin return pci_create_simple(bus, -1, "vmware-svga");
1916a94f0c5cSGerd Hoffmann case VGA_VIRTIO:
1917a94f0c5cSGerd Hoffmann return pci_create_simple(bus, -1, "virtio-vga");
1918315a1350SMichael S. Tsirkin case VGA_NONE:
1919315a1350SMichael S. Tsirkin default: /* Other non-PCI types. Checking for unsupported types is already
1920315a1350SMichael S. Tsirkin done in vl.c. */
1921315a1350SMichael S. Tsirkin return NULL;
1922315a1350SMichael S. Tsirkin }
1923315a1350SMichael S. Tsirkin }
1924315a1350SMichael S. Tsirkin
1925315a1350SMichael S. Tsirkin /* Whether a given bus number is in range of the secondary
1926315a1350SMichael S. Tsirkin * bus of the given bridge device. */
pci_secondary_bus_in_range(PCIDevice * dev,int bus_num)1927315a1350SMichael S. Tsirkin static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1928315a1350SMichael S. Tsirkin {
1929315a1350SMichael S. Tsirkin return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1930315a1350SMichael S. Tsirkin PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
193109e5b819SMarcel Apfelbaum dev->config[PCI_SECONDARY_BUS] <= bus_num &&
1932315a1350SMichael S. Tsirkin bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1933315a1350SMichael S. Tsirkin }
1934315a1350SMichael S. Tsirkin
193509e5b819SMarcel Apfelbaum /* Whether a given bus number is in a range of a root bus */
pci_root_bus_in_range(PCIBus * bus,int bus_num)193609e5b819SMarcel Apfelbaum static bool pci_root_bus_in_range(PCIBus *bus, int bus_num)
193709e5b819SMarcel Apfelbaum {
193809e5b819SMarcel Apfelbaum int i;
193909e5b819SMarcel Apfelbaum
194009e5b819SMarcel Apfelbaum for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
194109e5b819SMarcel Apfelbaum PCIDevice *dev = bus->devices[i];
194209e5b819SMarcel Apfelbaum
1943ad494274SIgor Mammedov if (dev && IS_PCI_BRIDGE(dev)) {
194409e5b819SMarcel Apfelbaum if (pci_secondary_bus_in_range(dev, bus_num)) {
194509e5b819SMarcel Apfelbaum return true;
194609e5b819SMarcel Apfelbaum }
194709e5b819SMarcel Apfelbaum }
194809e5b819SMarcel Apfelbaum }
194909e5b819SMarcel Apfelbaum
195009e5b819SMarcel Apfelbaum return false;
195109e5b819SMarcel Apfelbaum }
195209e5b819SMarcel Apfelbaum
pci_find_bus_nr(PCIBus * bus,int bus_num)1953987b73b3SMarkus Armbruster PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
1954315a1350SMichael S. Tsirkin {
1955315a1350SMichael S. Tsirkin PCIBus *sec;
1956315a1350SMichael S. Tsirkin
1957315a1350SMichael S. Tsirkin if (!bus) {
1958315a1350SMichael S. Tsirkin return NULL;
1959315a1350SMichael S. Tsirkin }
1960315a1350SMichael S. Tsirkin
1961315a1350SMichael S. Tsirkin if (pci_bus_num(bus) == bus_num) {
1962315a1350SMichael S. Tsirkin return bus;
1963315a1350SMichael S. Tsirkin }
1964315a1350SMichael S. Tsirkin
1965315a1350SMichael S. Tsirkin /* Consider all bus numbers in range for the host pci bridge. */
19660889464aSAlex Williamson if (!pci_bus_is_root(bus) &&
1967315a1350SMichael S. Tsirkin !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1968315a1350SMichael S. Tsirkin return NULL;
1969315a1350SMichael S. Tsirkin }
1970315a1350SMichael S. Tsirkin
1971315a1350SMichael S. Tsirkin /* try child bus */
1972315a1350SMichael S. Tsirkin for (; bus; bus = sec) {
1973315a1350SMichael S. Tsirkin QLIST_FOREACH(sec, &bus->child, sibling) {
197409e5b819SMarcel Apfelbaum if (pci_bus_num(sec) == bus_num) {
1975315a1350SMichael S. Tsirkin return sec;
1976315a1350SMichael S. Tsirkin }
197709e5b819SMarcel Apfelbaum /* PXB buses assumed to be children of bus 0 */
197809e5b819SMarcel Apfelbaum if (pci_bus_is_root(sec)) {
197909e5b819SMarcel Apfelbaum if (pci_root_bus_in_range(sec, bus_num)) {
198009e5b819SMarcel Apfelbaum break;
198109e5b819SMarcel Apfelbaum }
198209e5b819SMarcel Apfelbaum } else {
1983315a1350SMichael S. Tsirkin if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1984315a1350SMichael S. Tsirkin break;
1985315a1350SMichael S. Tsirkin }
1986315a1350SMichael S. Tsirkin }
1987315a1350SMichael S. Tsirkin }
198809e5b819SMarcel Apfelbaum }
1989315a1350SMichael S. Tsirkin
1990315a1350SMichael S. Tsirkin return NULL;
1991315a1350SMichael S. Tsirkin }
1992315a1350SMichael S. Tsirkin
pci_for_each_bus_depth_first(PCIBus * bus,pci_bus_ret_fn begin,pci_bus_fn end,void * parent_state)1993b3dcf94fSPeter Xu void pci_for_each_bus_depth_first(PCIBus *bus, pci_bus_ret_fn begin,
1994b3dcf94fSPeter Xu pci_bus_fn end, void *parent_state)
1995eb0acfddSMichael S. Tsirkin {
1996eb0acfddSMichael S. Tsirkin PCIBus *sec;
1997eb0acfddSMichael S. Tsirkin void *state;
1998eb0acfddSMichael S. Tsirkin
1999eb0acfddSMichael S. Tsirkin if (!bus) {
2000eb0acfddSMichael S. Tsirkin return;
2001eb0acfddSMichael S. Tsirkin }
2002eb0acfddSMichael S. Tsirkin
2003eb0acfddSMichael S. Tsirkin if (begin) {
2004eb0acfddSMichael S. Tsirkin state = begin(bus, parent_state);
2005eb0acfddSMichael S. Tsirkin } else {
2006eb0acfddSMichael S. Tsirkin state = parent_state;
2007eb0acfddSMichael S. Tsirkin }
2008eb0acfddSMichael S. Tsirkin
2009eb0acfddSMichael S. Tsirkin QLIST_FOREACH(sec, &bus->child, sibling) {
2010eb0acfddSMichael S. Tsirkin pci_for_each_bus_depth_first(sec, begin, end, state);
2011eb0acfddSMichael S. Tsirkin }
2012eb0acfddSMichael S. Tsirkin
2013eb0acfddSMichael S. Tsirkin if (end) {
2014eb0acfddSMichael S. Tsirkin end(bus, state);
2015eb0acfddSMichael S. Tsirkin }
2016eb0acfddSMichael S. Tsirkin }
2017eb0acfddSMichael S. Tsirkin
2018eb0acfddSMichael S. Tsirkin
pci_find_device(PCIBus * bus,int bus_num,uint8_t devfn)2019315a1350SMichael S. Tsirkin PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
2020315a1350SMichael S. Tsirkin {
2021315a1350SMichael S. Tsirkin bus = pci_find_bus_nr(bus, bus_num);
2022315a1350SMichael S. Tsirkin
2023315a1350SMichael S. Tsirkin if (!bus)
2024315a1350SMichael S. Tsirkin return NULL;
2025315a1350SMichael S. Tsirkin
2026315a1350SMichael S. Tsirkin return bus->devices[devfn];
2027315a1350SMichael S. Tsirkin }
2028315a1350SMichael S. Tsirkin
2029041b1c40SIgor Mammedov #define ONBOARD_INDEX_MAX (16 * 1024 - 1)
2030041b1c40SIgor Mammedov
pci_qdev_realize(DeviceState * qdev,Error ** errp)2031133e9b22SMarkus Armbruster static void pci_qdev_realize(DeviceState *qdev, Error **errp)
2032315a1350SMichael S. Tsirkin {
2033315a1350SMichael S. Tsirkin PCIDevice *pci_dev = (PCIDevice *)qdev;
2034315a1350SMichael S. Tsirkin PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
2035d61a363dSYoni Bettan ObjectClass *klass = OBJECT_CLASS(pc);
2036133e9b22SMarkus Armbruster Error *local_err = NULL;
2037315a1350SMichael S. Tsirkin bool is_default_rom;
20384f5b6a05SJens Freimann uint16_t class_id;
2039315a1350SMichael S. Tsirkin
2040041b1c40SIgor Mammedov /*
2041041b1c40SIgor Mammedov * capped by systemd (see: udev-builtin-net_id.c)
2042041b1c40SIgor Mammedov * as it's the only known user honor it to avoid users
2043041b1c40SIgor Mammedov * misconfigure QEMU and then wonder why acpi-index doesn't work
2044041b1c40SIgor Mammedov */
2045041b1c40SIgor Mammedov if (pci_dev->acpi_index > ONBOARD_INDEX_MAX) {
2046041b1c40SIgor Mammedov error_setg(errp, "acpi-index should be less or equal to %u",
2047041b1c40SIgor Mammedov ONBOARD_INDEX_MAX);
2048041b1c40SIgor Mammedov return;
2049041b1c40SIgor Mammedov }
2050041b1c40SIgor Mammedov
2051041b1c40SIgor Mammedov /*
2052041b1c40SIgor Mammedov * make sure that acpi-index is unique across all present PCI devices
2053041b1c40SIgor Mammedov */
2054041b1c40SIgor Mammedov if (pci_dev->acpi_index) {
2055041b1c40SIgor Mammedov GSequence *used_indexes = pci_acpi_index_list();
2056041b1c40SIgor Mammedov
2057041b1c40SIgor Mammedov if (g_sequence_lookup(used_indexes,
2058041b1c40SIgor Mammedov GINT_TO_POINTER(pci_dev->acpi_index),
2059041b1c40SIgor Mammedov g_cmp_uint32, NULL)) {
2060041b1c40SIgor Mammedov error_setg(errp, "a PCI device with acpi-index = %" PRIu32
2061041b1c40SIgor Mammedov " already exist", pci_dev->acpi_index);
2062041b1c40SIgor Mammedov return;
2063041b1c40SIgor Mammedov }
2064041b1c40SIgor Mammedov g_sequence_insert_sorted(used_indexes,
2065041b1c40SIgor Mammedov GINT_TO_POINTER(pci_dev->acpi_index),
2066041b1c40SIgor Mammedov g_cmp_uint32, NULL);
2067041b1c40SIgor Mammedov }
2068041b1c40SIgor Mammedov
20696a67577dSAkihiko Odaki if (pci_dev->romsize != UINT32_MAX && !is_power_of_2(pci_dev->romsize)) {
207008b1df8fSPaolo Bonzini error_setg(errp, "ROM size %u is not a power of two", pci_dev->romsize);
207108b1df8fSPaolo Bonzini return;
207208b1df8fSPaolo Bonzini }
207308b1df8fSPaolo Bonzini
2074d61a363dSYoni Bettan /* initialize cap_present for pci_is_express() and pci_config_size(),
2075d61a363dSYoni Bettan * Note that hybrid PCIs are not set automatically and need to manage
2076d61a363dSYoni Bettan * QEMU_PCI_CAP_EXPRESS manually */
2077d61a363dSYoni Bettan if (object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE) &&
2078d61a363dSYoni Bettan !object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE)) {
2079315a1350SMichael S. Tsirkin pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
2080315a1350SMichael S. Tsirkin }
2081315a1350SMichael S. Tsirkin
2082cf04aba2SBen Widawsky if (object_class_dynamic_cast(klass, INTERFACE_CXL_DEVICE)) {
2083cf04aba2SBen Widawsky pci_dev->cap_present |= QEMU_PCIE_CAP_CXL;
2084cf04aba2SBen Widawsky }
2085cf04aba2SBen Widawsky
2086fd56e061SDavid Gibson pci_dev = do_pci_register_device(pci_dev,
2087315a1350SMichael S. Tsirkin object_get_typename(OBJECT(qdev)),
2088133e9b22SMarkus Armbruster pci_dev->devfn, errp);
2089315a1350SMichael S. Tsirkin if (pci_dev == NULL)
2090133e9b22SMarkus Armbruster return;
20912897ae02SIgor Mammedov
20927ee6c1e1SMarkus Armbruster if (pc->realize) {
20937ee6c1e1SMarkus Armbruster pc->realize(pci_dev, &local_err);
20947ee6c1e1SMarkus Armbruster if (local_err) {
20957ee6c1e1SMarkus Armbruster error_propagate(errp, local_err);
2096315a1350SMichael S. Tsirkin do_pci_unregister_device(pci_dev);
2097133e9b22SMarkus Armbruster return;
2098315a1350SMichael S. Tsirkin }
2099315a1350SMichael S. Tsirkin }
2100315a1350SMichael S. Tsirkin
2101ca92eb5dSAni Sinha /*
2102ca92eb5dSAni Sinha * A PCIe Downstream Port that do not have ARI Forwarding enabled must
2103ca92eb5dSAni Sinha * associate only Device 0 with the device attached to the bus
2104ca92eb5dSAni Sinha * representing the Link from the Port (PCIe base spec rev 4.0 ver 0.3,
2105ca92eb5dSAni Sinha * sec 7.3.1).
2106ca92eb5dSAni Sinha * With ARI, PCI_SLOT() can return non-zero value as the traditional
2107ca92eb5dSAni Sinha * 5-bit Device Number and 3-bit Function Number fields in its associated
2108ca92eb5dSAni Sinha * Routing IDs, Requester IDs and Completer IDs are interpreted as a
2109ca92eb5dSAni Sinha * single 8-bit Function Number. Hence, ignore ARI capable devices.
2110ca92eb5dSAni Sinha */
2111ca92eb5dSAni Sinha if (pci_is_express(pci_dev) &&
2112ca92eb5dSAni Sinha !pcie_find_capability(pci_dev, PCI_EXT_CAP_ID_ARI) &&
2113ca92eb5dSAni Sinha pcie_has_upstream_port(pci_dev) &&
2114ca92eb5dSAni Sinha PCI_SLOT(pci_dev->devfn)) {
2115ca92eb5dSAni Sinha warn_report("PCI: slot %d is not valid for %s,"
2116ca92eb5dSAni Sinha " parent device only allows plugging into slot 0.",
2117ca92eb5dSAni Sinha PCI_SLOT(pci_dev->devfn), pci_dev->name);
2118ca92eb5dSAni Sinha }
2119ca92eb5dSAni Sinha
21204f5b6a05SJens Freimann if (pci_dev->failover_pair_id) {
21214f5b6a05SJens Freimann if (!pci_bus_is_express(pci_get_bus(pci_dev))) {
21224f5b6a05SJens Freimann error_setg(errp, "failover primary device must be on "
21234f5b6a05SJens Freimann "PCIExpress bus");
2124b69c3c21SMarkus Armbruster pci_qdev_unrealize(DEVICE(pci_dev));
21254f5b6a05SJens Freimann return;
21264f5b6a05SJens Freimann }
21274f5b6a05SJens Freimann class_id = pci_get_word(pci_dev->config + PCI_CLASS_DEVICE);
21284f5b6a05SJens Freimann if (class_id != PCI_CLASS_NETWORK_ETHERNET) {
21294f5b6a05SJens Freimann error_setg(errp, "failover primary device is not an "
21304f5b6a05SJens Freimann "Ethernet device");
2131b69c3c21SMarkus Armbruster pci_qdev_unrealize(DEVICE(pci_dev));
21324f5b6a05SJens Freimann return;
21334f5b6a05SJens Freimann }
2134b01a4901SLaurent Vivier if ((pci_dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)
2135b01a4901SLaurent Vivier || (PCI_FUNC(pci_dev->devfn) != 0)) {
21364f5b6a05SJens Freimann error_setg(errp, "failover: primary device must be in its own "
21374f5b6a05SJens Freimann "PCI slot");
2138b69c3c21SMarkus Armbruster pci_qdev_unrealize(DEVICE(pci_dev));
21394f5b6a05SJens Freimann return;
21404f5b6a05SJens Freimann }
2141a1190ab6SJens Freimann qdev->allow_unplug_during_migration = true;
21424f5b6a05SJens Freimann }
21434f5b6a05SJens Freimann
2144315a1350SMichael S. Tsirkin /* rom loading */
2145315a1350SMichael S. Tsirkin is_default_rom = false;
2146315a1350SMichael S. Tsirkin if (pci_dev->romfile == NULL && pc->romfile != NULL) {
2147315a1350SMichael S. Tsirkin pci_dev->romfile = g_strdup(pc->romfile);
2148315a1350SMichael S. Tsirkin is_default_rom = true;
2149315a1350SMichael S. Tsirkin }
2150178e785fSMarcel Apfelbaum
2151133e9b22SMarkus Armbruster pci_add_option_rom(pci_dev, is_default_rom, &local_err);
2152133e9b22SMarkus Armbruster if (local_err) {
2153133e9b22SMarkus Armbruster error_propagate(errp, local_err);
2154b69c3c21SMarkus Armbruster pci_qdev_unrealize(DEVICE(pci_dev));
2155133e9b22SMarkus Armbruster return;
2156178e785fSMarcel Apfelbaum }
215723786d13SGerd Hoffmann
215823786d13SGerd Hoffmann pci_set_power(pci_dev, true);
215908cf3dc6SJagannathan Raman
216008cf3dc6SJagannathan Raman pci_dev->msi_trigger = pci_msi_trigger;
2161315a1350SMichael S. Tsirkin }
2162315a1350SMichael S. Tsirkin
pci_new_internal(int devfn,bool multifunction,const char * name)2163c925f40aSBernhard Beschow static PCIDevice *pci_new_internal(int devfn, bool multifunction,
21647411aa63SMarkus Armbruster const char *name)
21657411aa63SMarkus Armbruster {
21667411aa63SMarkus Armbruster DeviceState *dev;
21677411aa63SMarkus Armbruster
21687411aa63SMarkus Armbruster dev = qdev_new(name);
21697411aa63SMarkus Armbruster qdev_prop_set_int32(dev, "addr", devfn);
21707411aa63SMarkus Armbruster qdev_prop_set_bit(dev, "multifunction", multifunction);
21717411aa63SMarkus Armbruster return PCI_DEVICE(dev);
21727411aa63SMarkus Armbruster }
21737411aa63SMarkus Armbruster
pci_new_multifunction(int devfn,const char * name)2174c925f40aSBernhard Beschow PCIDevice *pci_new_multifunction(int devfn, const char *name)
2175c925f40aSBernhard Beschow {
2176c925f40aSBernhard Beschow return pci_new_internal(devfn, true, name);
2177c925f40aSBernhard Beschow }
2178c925f40aSBernhard Beschow
pci_new(int devfn,const char * name)21797411aa63SMarkus Armbruster PCIDevice *pci_new(int devfn, const char *name)
21807411aa63SMarkus Armbruster {
2181c925f40aSBernhard Beschow return pci_new_internal(devfn, false, name);
21827411aa63SMarkus Armbruster }
21837411aa63SMarkus Armbruster
pci_realize_and_unref(PCIDevice * dev,PCIBus * bus,Error ** errp)21847411aa63SMarkus Armbruster bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp)
21857411aa63SMarkus Armbruster {
21867411aa63SMarkus Armbruster return qdev_realize_and_unref(&dev->qdev, &bus->qbus, errp);
21877411aa63SMarkus Armbruster }
21887411aa63SMarkus Armbruster
pci_create_simple_multifunction(PCIBus * bus,int devfn,const char * name)2189315a1350SMichael S. Tsirkin PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
2190315a1350SMichael S. Tsirkin const char *name)
2191315a1350SMichael S. Tsirkin {
2192c925f40aSBernhard Beschow PCIDevice *dev = pci_new_multifunction(devfn, name);
21939307d06dSMarkus Armbruster pci_realize_and_unref(dev, bus, &error_fatal);
2194315a1350SMichael S. Tsirkin return dev;
2195315a1350SMichael S. Tsirkin }
2196315a1350SMichael S. Tsirkin
pci_create_simple(PCIBus * bus,int devfn,const char * name)2197315a1350SMichael S. Tsirkin PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
2198315a1350SMichael S. Tsirkin {
2199e052944aSBernhard Beschow PCIDevice *dev = pci_new(devfn, name);
2200e052944aSBernhard Beschow pci_realize_and_unref(dev, bus, &error_fatal);
2201e052944aSBernhard Beschow return dev;
2202315a1350SMichael S. Tsirkin }
2203315a1350SMichael S. Tsirkin
pci_find_space(PCIDevice * pdev,uint8_t size)2204315a1350SMichael S. Tsirkin static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size)
2205315a1350SMichael S. Tsirkin {
2206315a1350SMichael S. Tsirkin int offset = PCI_CONFIG_HEADER_SIZE;
2207315a1350SMichael S. Tsirkin int i;
2208315a1350SMichael S. Tsirkin for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) {
2209315a1350SMichael S. Tsirkin if (pdev->used[i])
2210315a1350SMichael S. Tsirkin offset = i + 1;
2211315a1350SMichael S. Tsirkin else if (i - offset + 1 == size)
2212315a1350SMichael S. Tsirkin return offset;
2213315a1350SMichael S. Tsirkin }
2214315a1350SMichael S. Tsirkin return 0;
2215315a1350SMichael S. Tsirkin }
2216315a1350SMichael S. Tsirkin
pci_find_capability_list(PCIDevice * pdev,uint8_t cap_id,uint8_t * prev_p)2217315a1350SMichael S. Tsirkin static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
2218315a1350SMichael S. Tsirkin uint8_t *prev_p)
2219315a1350SMichael S. Tsirkin {
2220315a1350SMichael S. Tsirkin uint8_t next, prev;
2221315a1350SMichael S. Tsirkin
2222315a1350SMichael S. Tsirkin if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
2223315a1350SMichael S. Tsirkin return 0;
2224315a1350SMichael S. Tsirkin
2225315a1350SMichael S. Tsirkin for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
2226315a1350SMichael S. Tsirkin prev = next + PCI_CAP_LIST_NEXT)
2227315a1350SMichael S. Tsirkin if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
2228315a1350SMichael S. Tsirkin break;
2229315a1350SMichael S. Tsirkin
2230315a1350SMichael S. Tsirkin if (prev_p)
2231315a1350SMichael S. Tsirkin *prev_p = prev;
2232315a1350SMichael S. Tsirkin return next;
2233315a1350SMichael S. Tsirkin }
2234315a1350SMichael S. Tsirkin
pci_find_capability_at_offset(PCIDevice * pdev,uint8_t offset)2235315a1350SMichael S. Tsirkin static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
2236315a1350SMichael S. Tsirkin {
2237315a1350SMichael S. Tsirkin uint8_t next, prev, found = 0;
2238315a1350SMichael S. Tsirkin
2239315a1350SMichael S. Tsirkin if (!(pdev->used[offset])) {
2240315a1350SMichael S. Tsirkin return 0;
2241315a1350SMichael S. Tsirkin }
2242315a1350SMichael S. Tsirkin
2243315a1350SMichael S. Tsirkin assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST);
2244315a1350SMichael S. Tsirkin
2245315a1350SMichael S. Tsirkin for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
2246315a1350SMichael S. Tsirkin prev = next + PCI_CAP_LIST_NEXT) {
2247315a1350SMichael S. Tsirkin if (next <= offset && next > found) {
2248315a1350SMichael S. Tsirkin found = next;
2249315a1350SMichael S. Tsirkin }
2250315a1350SMichael S. Tsirkin }
2251315a1350SMichael S. Tsirkin return found;
2252315a1350SMichael S. Tsirkin }
2253315a1350SMichael S. Tsirkin
2254315a1350SMichael S. Tsirkin /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
2255315a1350SMichael S. Tsirkin This is needed for an option rom which is used for more than one device. */
pci_patch_ids(PCIDevice * pdev,uint8_t * ptr,uint32_t size)22567c16b5bbSPaolo Bonzini static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, uint32_t size)
2257315a1350SMichael S. Tsirkin {
2258315a1350SMichael S. Tsirkin uint16_t vendor_id;
2259315a1350SMichael S. Tsirkin uint16_t device_id;
2260315a1350SMichael S. Tsirkin uint16_t rom_vendor_id;
2261315a1350SMichael S. Tsirkin uint16_t rom_device_id;
2262315a1350SMichael S. Tsirkin uint16_t rom_magic;
2263315a1350SMichael S. Tsirkin uint16_t pcir_offset;
2264315a1350SMichael S. Tsirkin uint8_t checksum;
2265315a1350SMichael S. Tsirkin
2266315a1350SMichael S. Tsirkin /* Words in rom data are little endian (like in PCI configuration),
2267315a1350SMichael S. Tsirkin so they can be read / written with pci_get_word / pci_set_word. */
2268315a1350SMichael S. Tsirkin
2269315a1350SMichael S. Tsirkin /* Only a valid rom will be patched. */
2270315a1350SMichael S. Tsirkin rom_magic = pci_get_word(ptr);
2271315a1350SMichael S. Tsirkin if (rom_magic != 0xaa55) {
2272315a1350SMichael S. Tsirkin PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
2273315a1350SMichael S. Tsirkin return;
2274315a1350SMichael S. Tsirkin }
2275315a1350SMichael S. Tsirkin pcir_offset = pci_get_word(ptr + 0x18);
2276315a1350SMichael S. Tsirkin if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
2277315a1350SMichael S. Tsirkin PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
2278315a1350SMichael S. Tsirkin return;
2279315a1350SMichael S. Tsirkin }
2280315a1350SMichael S. Tsirkin
2281315a1350SMichael S. Tsirkin vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
2282315a1350SMichael S. Tsirkin device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
2283315a1350SMichael S. Tsirkin rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
2284315a1350SMichael S. Tsirkin rom_device_id = pci_get_word(ptr + pcir_offset + 6);
2285315a1350SMichael S. Tsirkin
2286315a1350SMichael S. Tsirkin PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
2287315a1350SMichael S. Tsirkin vendor_id, device_id, rom_vendor_id, rom_device_id);
2288315a1350SMichael S. Tsirkin
2289315a1350SMichael S. Tsirkin checksum = ptr[6];
2290315a1350SMichael S. Tsirkin
2291315a1350SMichael S. Tsirkin if (vendor_id != rom_vendor_id) {
2292315a1350SMichael S. Tsirkin /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
2293315a1350SMichael S. Tsirkin checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
2294315a1350SMichael S. Tsirkin checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
2295315a1350SMichael S. Tsirkin PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
2296315a1350SMichael S. Tsirkin ptr[6] = checksum;
2297315a1350SMichael S. Tsirkin pci_set_word(ptr + pcir_offset + 4, vendor_id);
2298315a1350SMichael S. Tsirkin }
2299315a1350SMichael S. Tsirkin
2300315a1350SMichael S. Tsirkin if (device_id != rom_device_id) {
2301315a1350SMichael S. Tsirkin /* Patch device id and checksum (at offset 6 for etherboot roms). */
2302315a1350SMichael S. Tsirkin checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
2303315a1350SMichael S. Tsirkin checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
2304315a1350SMichael S. Tsirkin PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
2305315a1350SMichael S. Tsirkin ptr[6] = checksum;
2306315a1350SMichael S. Tsirkin pci_set_word(ptr + pcir_offset + 6, device_id);
2307315a1350SMichael S. Tsirkin }
2308315a1350SMichael S. Tsirkin }
2309315a1350SMichael S. Tsirkin
2310315a1350SMichael S. Tsirkin /* Add an option rom for the device */
pci_add_option_rom(PCIDevice * pdev,bool is_default_rom,Error ** errp)2311133e9b22SMarkus Armbruster static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom,
2312133e9b22SMarkus Armbruster Error **errp)
2313315a1350SMichael S. Tsirkin {
23148eb85fb5SVladimir Sementsov-Ogievskiy int64_t size = 0;
23155b52692fSVladimir Sementsov-Ogievskiy g_autofree char *path = NULL;
2316315a1350SMichael S. Tsirkin char name[32];
2317315a1350SMichael S. Tsirkin const VMStateDescription *vmsd;
2318315a1350SMichael S. Tsirkin
23198eb85fb5SVladimir Sementsov-Ogievskiy /*
23208eb85fb5SVladimir Sementsov-Ogievskiy * In case of incoming migration ROM will come with migration stream, no
23218eb85fb5SVladimir Sementsov-Ogievskiy * reason to load the file. Neither we want to fail if local ROM file
23228eb85fb5SVladimir Sementsov-Ogievskiy * mismatches with specified romsize.
23238eb85fb5SVladimir Sementsov-Ogievskiy */
23248eb85fb5SVladimir Sementsov-Ogievskiy bool load_file = !runstate_check(RUN_STATE_INMIGRATE);
23258eb85fb5SVladimir Sementsov-Ogievskiy
23264ab049c7SVladimir Sementsov-Ogievskiy if (!pdev->romfile || !strlen(pdev->romfile)) {
2327133e9b22SMarkus Armbruster return;
23284ab049c7SVladimir Sementsov-Ogievskiy }
2329315a1350SMichael S. Tsirkin
2330315a1350SMichael S. Tsirkin if (!pdev->rom_bar) {
2331315a1350SMichael S. Tsirkin /*
2332315a1350SMichael S. Tsirkin * Load rom via fw_cfg instead of creating a rom bar,
2333315a1350SMichael S. Tsirkin * for 0.11 compatibility.
2334315a1350SMichael S. Tsirkin */
2335315a1350SMichael S. Tsirkin int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
2336db80c7b9SMarcel Apfelbaum
2337db80c7b9SMarcel Apfelbaum /*
2338db80c7b9SMarcel Apfelbaum * Hot-plugged devices can't use the option ROM
2339db80c7b9SMarcel Apfelbaum * if the rom bar is disabled.
2340db80c7b9SMarcel Apfelbaum */
2341db80c7b9SMarcel Apfelbaum if (DEVICE(pdev)->hotplugged) {
2342133e9b22SMarkus Armbruster error_setg(errp, "Hot-plugged device without ROM bar"
2343133e9b22SMarkus Armbruster " can't have an option ROM");
2344133e9b22SMarkus Armbruster return;
2345db80c7b9SMarcel Apfelbaum }
2346db80c7b9SMarcel Apfelbaum
2347315a1350SMichael S. Tsirkin if (class == 0x0300) {
2348315a1350SMichael S. Tsirkin rom_add_vga(pdev->romfile);
2349315a1350SMichael S. Tsirkin } else {
2350315a1350SMichael S. Tsirkin rom_add_option(pdev->romfile, -1);
2351315a1350SMichael S. Tsirkin }
2352133e9b22SMarkus Armbruster return;
2353315a1350SMichael S. Tsirkin }
2354315a1350SMichael S. Tsirkin
23556a67577dSAkihiko Odaki if (load_file || pdev->romsize == UINT32_MAX) {
2356315a1350SMichael S. Tsirkin path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
2357315a1350SMichael S. Tsirkin if (path == NULL) {
2358315a1350SMichael S. Tsirkin path = g_strdup(pdev->romfile);
2359315a1350SMichael S. Tsirkin }
2360315a1350SMichael S. Tsirkin
2361315a1350SMichael S. Tsirkin size = get_image_size(path);
2362315a1350SMichael S. Tsirkin if (size < 0) {
2363133e9b22SMarkus Armbruster error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile);
2364133e9b22SMarkus Armbruster return;
23658c7f3dd0SStefan Hajnoczi } else if (size == 0) {
2366133e9b22SMarkus Armbruster error_setg(errp, "romfile \"%s\" is empty", pdev->romfile);
2367133e9b22SMarkus Armbruster return;
23687c16b5bbSPaolo Bonzini } else if (size > 2 * GiB) {
23698eb85fb5SVladimir Sementsov-Ogievskiy error_setg(errp,
23708eb85fb5SVladimir Sementsov-Ogievskiy "romfile \"%s\" too large (size cannot exceed 2 GiB)",
23717c16b5bbSPaolo Bonzini pdev->romfile);
23727c16b5bbSPaolo Bonzini return;
2373315a1350SMichael S. Tsirkin }
23746a67577dSAkihiko Odaki if (pdev->romsize != UINT_MAX) {
237508b1df8fSPaolo Bonzini if (size > pdev->romsize) {
23764ab049c7SVladimir Sementsov-Ogievskiy error_setg(errp, "romfile \"%s\" (%u bytes) "
23774ab049c7SVladimir Sementsov-Ogievskiy "is too large for ROM size %u",
237808b1df8fSPaolo Bonzini pdev->romfile, (uint32_t)size, pdev->romsize);
237908b1df8fSPaolo Bonzini return;
238008b1df8fSPaolo Bonzini }
238108b1df8fSPaolo Bonzini } else {
238208b1df8fSPaolo Bonzini pdev->romsize = pow2ceil(size);
238308b1df8fSPaolo Bonzini }
23848eb85fb5SVladimir Sementsov-Ogievskiy }
2385315a1350SMichael S. Tsirkin
2386315a1350SMichael S. Tsirkin vmsd = qdev_get_vmsd(DEVICE(pdev));
23874ab049c7SVladimir Sementsov-Ogievskiy snprintf(name, sizeof(name), "%s.rom",
23884ab049c7SVladimir Sementsov-Ogievskiy vmsd ? vmsd->name : object_get_typename(OBJECT(pdev)));
2389315a1350SMichael S. Tsirkin
2390315a1350SMichael S. Tsirkin pdev->has_rom = true;
23914ab049c7SVladimir Sementsov-Ogievskiy memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, pdev->romsize,
23924ab049c7SVladimir Sementsov-Ogievskiy &error_fatal);
23934ab049c7SVladimir Sementsov-Ogievskiy
23948eb85fb5SVladimir Sementsov-Ogievskiy if (load_file) {
23958eb85fb5SVladimir Sementsov-Ogievskiy void *ptr = memory_region_get_ram_ptr(&pdev->rom);
23968eb85fb5SVladimir Sementsov-Ogievskiy
239736bde091SPeter Maydell if (load_image_size(path, ptr, size) < 0) {
239836bde091SPeter Maydell error_setg(errp, "failed to load romfile \"%s\"", pdev->romfile);
239936bde091SPeter Maydell return;
240036bde091SPeter Maydell }
2401315a1350SMichael S. Tsirkin
2402315a1350SMichael S. Tsirkin if (is_default_rom) {
2403315a1350SMichael S. Tsirkin /* Only the default rom images will be patched (if needed). */
2404315a1350SMichael S. Tsirkin pci_patch_ids(pdev, ptr, size);
2405315a1350SMichael S. Tsirkin }
24068eb85fb5SVladimir Sementsov-Ogievskiy }
2407315a1350SMichael S. Tsirkin
2408315a1350SMichael S. Tsirkin pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
2409315a1350SMichael S. Tsirkin }
2410315a1350SMichael S. Tsirkin
pci_del_option_rom(PCIDevice * pdev)2411315a1350SMichael S. Tsirkin static void pci_del_option_rom(PCIDevice *pdev)
2412315a1350SMichael S. Tsirkin {
2413315a1350SMichael S. Tsirkin if (!pdev->has_rom)
2414315a1350SMichael S. Tsirkin return;
2415315a1350SMichael S. Tsirkin
2416315a1350SMichael S. Tsirkin vmstate_unregister_ram(&pdev->rom, &pdev->qdev);
2417315a1350SMichael S. Tsirkin pdev->has_rom = false;
2418315a1350SMichael S. Tsirkin }
2419315a1350SMichael S. Tsirkin
2420315a1350SMichael S. Tsirkin /*
242127841278SMao Zhongyi * On success, pci_add_capability() returns a positive value
2422eacbc632SMao Zhongyi * that the offset of the pci capability.
2423eacbc632SMao Zhongyi * On failure, it sets an error and returns a negative error
2424eacbc632SMao Zhongyi * code.
2425eacbc632SMao Zhongyi */
pci_add_capability(PCIDevice * pdev,uint8_t cap_id,uint8_t offset,uint8_t size,Error ** errp)242627841278SMao Zhongyi int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
2427cd9aa33eSLaszlo Ersek uint8_t offset, uint8_t size,
2428cd9aa33eSLaszlo Ersek Error **errp)
2429cd9aa33eSLaszlo Ersek {
2430315a1350SMichael S. Tsirkin uint8_t *config;
2431315a1350SMichael S. Tsirkin int i, overlapping_cap;
2432315a1350SMichael S. Tsirkin
2433315a1350SMichael S. Tsirkin if (!offset) {
2434315a1350SMichael S. Tsirkin offset = pci_find_space(pdev, size);
243597fe42f1SCao jin /* out of PCI config space is programming error */
243697fe42f1SCao jin assert(offset);
2437315a1350SMichael S. Tsirkin } else {
2438315a1350SMichael S. Tsirkin /* Verify that capabilities don't overlap. Note: device assignment
2439315a1350SMichael S. Tsirkin * depends on this check to verify that the device is not broken.
2440315a1350SMichael S. Tsirkin * Should never trigger for emulated devices, but it's helpful
2441315a1350SMichael S. Tsirkin * for debugging these. */
2442315a1350SMichael S. Tsirkin for (i = offset; i < offset + size; i++) {
2443315a1350SMichael S. Tsirkin overlapping_cap = pci_find_capability_at_offset(pdev, i);
2444315a1350SMichael S. Tsirkin if (overlapping_cap) {
2445cd9aa33eSLaszlo Ersek error_setg(errp, "%s:%02x:%02x.%x "
2446315a1350SMichael S. Tsirkin "Attempt to add PCI capability %x at offset "
2447cd9aa33eSLaszlo Ersek "%x overlaps existing capability %x at offset %x",
2448fd56e061SDavid Gibson pci_root_bus_path(pdev), pci_dev_bus_num(pdev),
2449315a1350SMichael S. Tsirkin PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2450315a1350SMichael S. Tsirkin cap_id, offset, overlapping_cap, i);
2451315a1350SMichael S. Tsirkin return -EINVAL;
2452315a1350SMichael S. Tsirkin }
2453315a1350SMichael S. Tsirkin }
2454315a1350SMichael S. Tsirkin }
2455315a1350SMichael S. Tsirkin
2456315a1350SMichael S. Tsirkin config = pdev->config + offset;
2457315a1350SMichael S. Tsirkin config[PCI_CAP_LIST_ID] = cap_id;
2458315a1350SMichael S. Tsirkin config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
2459315a1350SMichael S. Tsirkin pdev->config[PCI_CAPABILITY_LIST] = offset;
2460315a1350SMichael S. Tsirkin pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
2461315a1350SMichael S. Tsirkin memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4));
2462315a1350SMichael S. Tsirkin /* Make capability read-only by default */
2463315a1350SMichael S. Tsirkin memset(pdev->wmask + offset, 0, size);
2464315a1350SMichael S. Tsirkin /* Check capability by default */
2465315a1350SMichael S. Tsirkin memset(pdev->cmask + offset, 0xFF, size);
2466315a1350SMichael S. Tsirkin return offset;
2467315a1350SMichael S. Tsirkin }
2468315a1350SMichael S. Tsirkin
2469315a1350SMichael S. Tsirkin /* Unlink capability from the pci config space. */
pci_del_capability(PCIDevice * pdev,uint8_t cap_id,uint8_t size)2470315a1350SMichael S. Tsirkin void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
2471315a1350SMichael S. Tsirkin {
2472315a1350SMichael S. Tsirkin uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
2473315a1350SMichael S. Tsirkin if (!offset)
2474315a1350SMichael S. Tsirkin return;
2475315a1350SMichael S. Tsirkin pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
2476315a1350SMichael S. Tsirkin /* Make capability writable again */
2477315a1350SMichael S. Tsirkin memset(pdev->wmask + offset, 0xff, size);
2478315a1350SMichael S. Tsirkin memset(pdev->w1cmask + offset, 0, size);
2479315a1350SMichael S. Tsirkin /* Clear cmask as device-specific registers can't be checked */
2480315a1350SMichael S. Tsirkin memset(pdev->cmask + offset, 0, size);
2481315a1350SMichael S. Tsirkin memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4));
2482315a1350SMichael S. Tsirkin
2483315a1350SMichael S. Tsirkin if (!pdev->config[PCI_CAPABILITY_LIST])
2484315a1350SMichael S. Tsirkin pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
2485315a1350SMichael S. Tsirkin }
2486315a1350SMichael S. Tsirkin
pci_find_capability(PCIDevice * pdev,uint8_t cap_id)2487315a1350SMichael S. Tsirkin uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
2488315a1350SMichael S. Tsirkin {
2489315a1350SMichael S. Tsirkin return pci_find_capability_list(pdev, cap_id, NULL);
2490315a1350SMichael S. Tsirkin }
2491315a1350SMichael S. Tsirkin
pci_dev_fw_name(DeviceState * dev,char * buf,int len)2492315a1350SMichael S. Tsirkin static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
2493315a1350SMichael S. Tsirkin {
2494315a1350SMichael S. Tsirkin PCIDevice *d = (PCIDevice *)dev;
2495315a1350SMichael S. Tsirkin const char *name = NULL;
2496315a1350SMichael S. Tsirkin const pci_class_desc *desc = pci_class_descriptions;
2497315a1350SMichael S. Tsirkin int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2498315a1350SMichael S. Tsirkin
2499315a1350SMichael S. Tsirkin while (desc->desc &&
2500315a1350SMichael S. Tsirkin (class & ~desc->fw_ign_bits) !=
2501315a1350SMichael S. Tsirkin (desc->class & ~desc->fw_ign_bits)) {
2502315a1350SMichael S. Tsirkin desc++;
2503315a1350SMichael S. Tsirkin }
2504315a1350SMichael S. Tsirkin
2505315a1350SMichael S. Tsirkin if (desc->desc) {
2506315a1350SMichael S. Tsirkin name = desc->fw_name;
2507315a1350SMichael S. Tsirkin }
2508315a1350SMichael S. Tsirkin
2509315a1350SMichael S. Tsirkin if (name) {
2510315a1350SMichael S. Tsirkin pstrcpy(buf, len, name);
2511315a1350SMichael S. Tsirkin } else {
2512315a1350SMichael S. Tsirkin snprintf(buf, len, "pci%04x,%04x",
2513315a1350SMichael S. Tsirkin pci_get_word(d->config + PCI_VENDOR_ID),
2514315a1350SMichael S. Tsirkin pci_get_word(d->config + PCI_DEVICE_ID));
2515315a1350SMichael S. Tsirkin }
2516315a1350SMichael S. Tsirkin
2517315a1350SMichael S. Tsirkin return buf;
2518315a1350SMichael S. Tsirkin }
2519315a1350SMichael S. Tsirkin
pcibus_get_fw_dev_path(DeviceState * dev)2520315a1350SMichael S. Tsirkin static char *pcibus_get_fw_dev_path(DeviceState *dev)
2521315a1350SMichael S. Tsirkin {
2522315a1350SMichael S. Tsirkin PCIDevice *d = (PCIDevice *)dev;
252336f18c69SClaudio Fontana char name[33];
252436f18c69SClaudio Fontana int has_func = !!PCI_FUNC(d->devfn);
2525315a1350SMichael S. Tsirkin
252636f18c69SClaudio Fontana return g_strdup_printf("%s@%x%s%.*x",
252736f18c69SClaudio Fontana pci_dev_fw_name(dev, name, sizeof(name)),
252836f18c69SClaudio Fontana PCI_SLOT(d->devfn),
252936f18c69SClaudio Fontana has_func ? "," : "",
253036f18c69SClaudio Fontana has_func,
253136f18c69SClaudio Fontana PCI_FUNC(d->devfn));
2532315a1350SMichael S. Tsirkin }
2533315a1350SMichael S. Tsirkin
pcibus_get_dev_path(DeviceState * dev)2534315a1350SMichael S. Tsirkin static char *pcibus_get_dev_path(DeviceState *dev)
2535315a1350SMichael S. Tsirkin {
2536315a1350SMichael S. Tsirkin PCIDevice *d = container_of(dev, PCIDevice, qdev);
2537315a1350SMichael S. Tsirkin PCIDevice *t;
2538315a1350SMichael S. Tsirkin int slot_depth;
2539315a1350SMichael S. Tsirkin /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2540315a1350SMichael S. Tsirkin * 00 is added here to make this format compatible with
2541315a1350SMichael S. Tsirkin * domain:Bus:Slot.Func for systems without nested PCI bridges.
2542315a1350SMichael S. Tsirkin * Slot.Function list specifies the slot and function numbers for all
2543315a1350SMichael S. Tsirkin * devices on the path from root to the specific device. */
2544568f0690SDavid Gibson const char *root_bus_path;
2545568f0690SDavid Gibson int root_bus_len;
2546315a1350SMichael S. Tsirkin char slot[] = ":SS.F";
2547315a1350SMichael S. Tsirkin int slot_len = sizeof slot - 1 /* For '\0' */;
2548315a1350SMichael S. Tsirkin int path_len;
2549315a1350SMichael S. Tsirkin char *path, *p;
2550315a1350SMichael S. Tsirkin int s;
2551315a1350SMichael S. Tsirkin
2552568f0690SDavid Gibson root_bus_path = pci_root_bus_path(d);
2553568f0690SDavid Gibson root_bus_len = strlen(root_bus_path);
2554568f0690SDavid Gibson
2555315a1350SMichael S. Tsirkin /* Calculate # of slots on path between device and root. */;
2556315a1350SMichael S. Tsirkin slot_depth = 0;
2557fd56e061SDavid Gibson for (t = d; t; t = pci_get_bus(t)->parent_dev) {
2558315a1350SMichael S. Tsirkin ++slot_depth;
2559315a1350SMichael S. Tsirkin }
2560315a1350SMichael S. Tsirkin
2561568f0690SDavid Gibson path_len = root_bus_len + slot_len * slot_depth;
2562315a1350SMichael S. Tsirkin
2563315a1350SMichael S. Tsirkin /* Allocate memory, fill in the terminating null byte. */
2564315a1350SMichael S. Tsirkin path = g_malloc(path_len + 1 /* For '\0' */);
2565315a1350SMichael S. Tsirkin path[path_len] = '\0';
2566315a1350SMichael S. Tsirkin
2567568f0690SDavid Gibson memcpy(path, root_bus_path, root_bus_len);
2568315a1350SMichael S. Tsirkin
2569315a1350SMichael S. Tsirkin /* Fill in slot numbers. We walk up from device to root, so need to print
2570315a1350SMichael S. Tsirkin * them in the reverse order, last to first. */
2571315a1350SMichael S. Tsirkin p = path + path_len;
2572fd56e061SDavid Gibson for (t = d; t; t = pci_get_bus(t)->parent_dev) {
2573315a1350SMichael S. Tsirkin p -= slot_len;
2574315a1350SMichael S. Tsirkin s = snprintf(slot, sizeof slot, ":%02x.%x",
2575315a1350SMichael S. Tsirkin PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
2576315a1350SMichael S. Tsirkin assert(s == slot_len);
2577315a1350SMichael S. Tsirkin memcpy(p, slot, slot_len);
2578315a1350SMichael S. Tsirkin }
2579315a1350SMichael S. Tsirkin
2580315a1350SMichael S. Tsirkin return path;
2581315a1350SMichael S. Tsirkin }
2582315a1350SMichael S. Tsirkin
pci_qdev_find_recursive(PCIBus * bus,const char * id,PCIDevice ** pdev)2583315a1350SMichael S. Tsirkin static int pci_qdev_find_recursive(PCIBus *bus,
2584315a1350SMichael S. Tsirkin const char *id, PCIDevice **pdev)
2585315a1350SMichael S. Tsirkin {
2586315a1350SMichael S. Tsirkin DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2587315a1350SMichael S. Tsirkin if (!qdev) {
2588315a1350SMichael S. Tsirkin return -ENODEV;
2589315a1350SMichael S. Tsirkin }
2590315a1350SMichael S. Tsirkin
2591315a1350SMichael S. Tsirkin /* roughly check if given qdev is pci device */
2592315a1350SMichael S. Tsirkin if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) {
2593315a1350SMichael S. Tsirkin *pdev = PCI_DEVICE(qdev);
2594315a1350SMichael S. Tsirkin return 0;
2595315a1350SMichael S. Tsirkin }
2596315a1350SMichael S. Tsirkin return -EINVAL;
2597315a1350SMichael S. Tsirkin }
2598315a1350SMichael S. Tsirkin
pci_qdev_find_device(const char * id,PCIDevice ** pdev)2599315a1350SMichael S. Tsirkin int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2600315a1350SMichael S. Tsirkin {
26017588e2b0SDavid Gibson PCIHostState *host_bridge;
2602315a1350SMichael S. Tsirkin int rc = -ENODEV;
2603315a1350SMichael S. Tsirkin
26047588e2b0SDavid Gibson QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
26057588e2b0SDavid Gibson int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev);
2606315a1350SMichael S. Tsirkin if (!tmp) {
2607315a1350SMichael S. Tsirkin rc = 0;
2608315a1350SMichael S. Tsirkin break;
2609315a1350SMichael S. Tsirkin }
2610315a1350SMichael S. Tsirkin if (tmp != -ENODEV) {
2611315a1350SMichael S. Tsirkin rc = tmp;
2612315a1350SMichael S. Tsirkin }
2613315a1350SMichael S. Tsirkin }
2614315a1350SMichael S. Tsirkin
2615315a1350SMichael S. Tsirkin return rc;
2616315a1350SMichael S. Tsirkin }
2617315a1350SMichael S. Tsirkin
pci_address_space(PCIDevice * dev)2618315a1350SMichael S. Tsirkin MemoryRegion *pci_address_space(PCIDevice *dev)
2619315a1350SMichael S. Tsirkin {
2620fd56e061SDavid Gibson return pci_get_bus(dev)->address_space_mem;
2621315a1350SMichael S. Tsirkin }
2622315a1350SMichael S. Tsirkin
pci_address_space_io(PCIDevice * dev)2623315a1350SMichael S. Tsirkin MemoryRegion *pci_address_space_io(PCIDevice *dev)
2624315a1350SMichael S. Tsirkin {
2625fd56e061SDavid Gibson return pci_get_bus(dev)->address_space_io;
2626315a1350SMichael S. Tsirkin }
2627315a1350SMichael S. Tsirkin
pci_device_class_init(ObjectClass * klass,void * data)2628315a1350SMichael S. Tsirkin static void pci_device_class_init(ObjectClass *klass, void *data)
2629315a1350SMichael S. Tsirkin {
2630315a1350SMichael S. Tsirkin DeviceClass *k = DEVICE_CLASS(klass);
26317ee6c1e1SMarkus Armbruster
2632133e9b22SMarkus Armbruster k->realize = pci_qdev_realize;
2633133e9b22SMarkus Armbruster k->unrealize = pci_qdev_unrealize;
2634315a1350SMichael S. Tsirkin k->bus_type = TYPE_PCI_BUS;
26354f67d30bSMarc-André Lureau device_class_set_props(k, pci_props);
2636315a1350SMichael S. Tsirkin }
2637315a1350SMichael S. Tsirkin
pci_device_class_base_init(ObjectClass * klass,void * data)26382fefa16cSEduardo Habkost static void pci_device_class_base_init(ObjectClass *klass, void *data)
26392fefa16cSEduardo Habkost {
26402fefa16cSEduardo Habkost if (!object_class_is_abstract(klass)) {
26412fefa16cSEduardo Habkost ObjectClass *conventional =
26422fefa16cSEduardo Habkost object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE);
26432fefa16cSEduardo Habkost ObjectClass *pcie =
26442fefa16cSEduardo Habkost object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE);
2645d86d3019SBen Widawsky ObjectClass *cxl =
2646d86d3019SBen Widawsky object_class_dynamic_cast(klass, INTERFACE_CXL_DEVICE);
2647d86d3019SBen Widawsky assert(conventional || pcie || cxl);
26482fefa16cSEduardo Habkost }
26492fefa16cSEduardo Habkost }
26502fefa16cSEduardo Habkost
26516c8ed5feSZhenzhong Duan /*
26526c8ed5feSZhenzhong Duan * Get IOMMU root bus, aliased bus and devfn of a PCI device
26536c8ed5feSZhenzhong Duan *
26546c8ed5feSZhenzhong Duan * IOMMU root bus is needed by all call sites to call into iommu_ops.
26556c8ed5feSZhenzhong Duan * For call sites which don't need aliased BDF, passing NULL to
26566c8ed5feSZhenzhong Duan * aliased_[bus|devfn] is allowed.
26576c8ed5feSZhenzhong Duan *
26586c8ed5feSZhenzhong Duan * @piommu_bus: return root #PCIBus backed by an IOMMU for the PCI device.
26596c8ed5feSZhenzhong Duan *
26606c8ed5feSZhenzhong Duan * @aliased_bus: return aliased #PCIBus of the PCI device, optional.
26616c8ed5feSZhenzhong Duan *
26626c8ed5feSZhenzhong Duan * @aliased_devfn: return aliased devfn of the PCI device, optional.
26636c8ed5feSZhenzhong Duan */
pci_device_get_iommu_bus_devfn(PCIDevice * dev,PCIBus ** piommu_bus,PCIBus ** aliased_bus,int * aliased_devfn)26646c8ed5feSZhenzhong Duan static void pci_device_get_iommu_bus_devfn(PCIDevice *dev,
26656c8ed5feSZhenzhong Duan PCIBus **piommu_bus,
26666c8ed5feSZhenzhong Duan PCIBus **aliased_bus,
26676c8ed5feSZhenzhong Duan int *aliased_devfn)
26689eda7d37SAlexey Kardashevskiy {
2669fd56e061SDavid Gibson PCIBus *bus = pci_get_bus(dev);
26705af2ae23SBenjamin Herrenschmidt PCIBus *iommu_bus = bus;
26716c8ed5feSZhenzhong Duan int devfn = dev->devfn;
26729eda7d37SAlexey Kardashevskiy
2673ba7d12ebSYi Liu while (iommu_bus && !iommu_bus->iommu_ops && iommu_bus->parent_dev) {
267477ef8f8dSAlex Williamson PCIBus *parent_bus = pci_get_bus(iommu_bus->parent_dev);
267577ef8f8dSAlex Williamson
267677ef8f8dSAlex Williamson /*
267777ef8f8dSAlex Williamson * The requester ID of the provided device may be aliased, as seen from
267877ef8f8dSAlex Williamson * the IOMMU, due to topology limitations. The IOMMU relies on a
267977ef8f8dSAlex Williamson * requester ID to provide a unique AddressSpace for devices, but
268077ef8f8dSAlex Williamson * conventional PCI buses pre-date such concepts. Instead, the PCIe-
268177ef8f8dSAlex Williamson * to-PCI bridge creates and accepts transactions on behalf of down-
268277ef8f8dSAlex Williamson * stream devices. When doing so, all downstream devices are masked
268377ef8f8dSAlex Williamson * (aliased) behind a single requester ID. The requester ID used
268477ef8f8dSAlex Williamson * depends on the format of the bridge devices. Proper PCIe-to-PCI
268577ef8f8dSAlex Williamson * bridges, with a PCIe capability indicating such, follow the
268677ef8f8dSAlex Williamson * guidelines of chapter 2.3 of the PCIe-to-PCI/X bridge specification,
268777ef8f8dSAlex Williamson * where the bridge uses the seconary bus as the bridge portion of the
268877ef8f8dSAlex Williamson * requester ID and devfn of 00.0. For other bridges, typically those
268977ef8f8dSAlex Williamson * found on the root complex such as the dmi-to-pci-bridge, we follow
269077ef8f8dSAlex Williamson * the convention of typical bare-metal hardware, which uses the
269177ef8f8dSAlex Williamson * requester ID of the bridge itself. There are device specific
269277ef8f8dSAlex Williamson * exceptions to these rules, but these are the defaults that the
269377ef8f8dSAlex Williamson * Linux kernel uses when determining DMA aliases itself and believed
269477ef8f8dSAlex Williamson * to be true for the bare metal equivalents of the devices emulated
269577ef8f8dSAlex Williamson * in QEMU.
269677ef8f8dSAlex Williamson */
269777ef8f8dSAlex Williamson if (!pci_bus_is_express(iommu_bus)) {
269877ef8f8dSAlex Williamson PCIDevice *parent = iommu_bus->parent_dev;
269977ef8f8dSAlex Williamson
270077ef8f8dSAlex Williamson if (pci_is_express(parent) &&
270177ef8f8dSAlex Williamson pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) {
270277ef8f8dSAlex Williamson devfn = PCI_DEVFN(0, 0);
270377ef8f8dSAlex Williamson bus = iommu_bus;
270477ef8f8dSAlex Williamson } else {
270577ef8f8dSAlex Williamson devfn = parent->devfn;
270677ef8f8dSAlex Williamson bus = parent_bus;
270777ef8f8dSAlex Williamson }
270877ef8f8dSAlex Williamson }
270977ef8f8dSAlex Williamson
271077ef8f8dSAlex Williamson iommu_bus = parent_bus;
27119eda7d37SAlexey Kardashevskiy }
27126c8ed5feSZhenzhong Duan
27136c8ed5feSZhenzhong Duan assert(0 <= devfn && devfn < PCI_DEVFN_MAX);
27146c8ed5feSZhenzhong Duan assert(iommu_bus);
27156c8ed5feSZhenzhong Duan
27166c8ed5feSZhenzhong Duan if (pci_bus_bypass_iommu(bus) || !iommu_bus->iommu_ops) {
27176c8ed5feSZhenzhong Duan iommu_bus = NULL;
27186c8ed5feSZhenzhong Duan }
27196c8ed5feSZhenzhong Duan
27206c8ed5feSZhenzhong Duan *piommu_bus = iommu_bus;
27216c8ed5feSZhenzhong Duan
27226c8ed5feSZhenzhong Duan if (aliased_bus) {
27236c8ed5feSZhenzhong Duan *aliased_bus = bus;
27246c8ed5feSZhenzhong Duan }
27256c8ed5feSZhenzhong Duan
27266c8ed5feSZhenzhong Duan if (aliased_devfn) {
27276c8ed5feSZhenzhong Duan *aliased_devfn = devfn;
27286c8ed5feSZhenzhong Duan }
27296c8ed5feSZhenzhong Duan }
27306c8ed5feSZhenzhong Duan
pci_device_iommu_address_space(PCIDevice * dev)27316c8ed5feSZhenzhong Duan AddressSpace *pci_device_iommu_address_space(PCIDevice *dev)
27326c8ed5feSZhenzhong Duan {
27336c8ed5feSZhenzhong Duan PCIBus *bus;
27346c8ed5feSZhenzhong Duan PCIBus *iommu_bus;
27356c8ed5feSZhenzhong Duan int devfn;
27366c8ed5feSZhenzhong Duan
27376c8ed5feSZhenzhong Duan pci_device_get_iommu_bus_devfn(dev, &iommu_bus, &bus, &devfn);
27386c8ed5feSZhenzhong Duan if (iommu_bus) {
2739ba7d12ebSYi Liu return iommu_bus->iommu_ops->get_address_space(bus,
2740ba7d12ebSYi Liu iommu_bus->iommu_opaque, devfn);
27419eda7d37SAlexey Kardashevskiy }
27429eda7d37SAlexey Kardashevskiy return &address_space_memory;
27439eda7d37SAlexey Kardashevskiy }
27449eda7d37SAlexey Kardashevskiy
pci_device_set_iommu_device(PCIDevice * dev,HostIOMMUDevice * hiod,Error ** errp)2745b025ea68SYi Liu bool pci_device_set_iommu_device(PCIDevice *dev, HostIOMMUDevice *hiod,
2746b025ea68SYi Liu Error **errp)
2747b025ea68SYi Liu {
2748a9526419SEric Auger PCIBus *iommu_bus, *aliased_bus;
2749a9526419SEric Auger int aliased_devfn;
2750b025ea68SYi Liu
2751b025ea68SYi Liu /* set_iommu_device requires device's direct BDF instead of aliased BDF */
2752a9526419SEric Auger pci_device_get_iommu_bus_devfn(dev, &iommu_bus,
2753a9526419SEric Auger &aliased_bus, &aliased_devfn);
2754b025ea68SYi Liu if (iommu_bus && iommu_bus->iommu_ops->set_iommu_device) {
2755a9526419SEric Auger hiod->aliased_bus = aliased_bus;
2756a9526419SEric Auger hiod->aliased_devfn = aliased_devfn;
2757b025ea68SYi Liu return iommu_bus->iommu_ops->set_iommu_device(pci_get_bus(dev),
2758b025ea68SYi Liu iommu_bus->iommu_opaque,
2759b025ea68SYi Liu dev->devfn, hiod, errp);
2760b025ea68SYi Liu }
2761b025ea68SYi Liu return true;
2762b025ea68SYi Liu }
2763b025ea68SYi Liu
pci_device_unset_iommu_device(PCIDevice * dev)2764b025ea68SYi Liu void pci_device_unset_iommu_device(PCIDevice *dev)
2765b025ea68SYi Liu {
2766b025ea68SYi Liu PCIBus *iommu_bus;
2767b025ea68SYi Liu
2768b025ea68SYi Liu pci_device_get_iommu_bus_devfn(dev, &iommu_bus, NULL, NULL);
2769b025ea68SYi Liu if (iommu_bus && iommu_bus->iommu_ops->unset_iommu_device) {
2770b025ea68SYi Liu return iommu_bus->iommu_ops->unset_iommu_device(pci_get_bus(dev),
2771b025ea68SYi Liu iommu_bus->iommu_opaque,
2772b025ea68SYi Liu dev->devfn);
2773b025ea68SYi Liu }
2774b025ea68SYi Liu }
2775b025ea68SYi Liu
pci_setup_iommu(PCIBus * bus,const PCIIOMMUOps * ops,void * opaque)2776ba7d12ebSYi Liu void pci_setup_iommu(PCIBus *bus, const PCIIOMMUOps *ops, void *opaque)
2777315a1350SMichael S. Tsirkin {
2778ba7d12ebSYi Liu /*
2779ba7d12ebSYi Liu * If called, pci_setup_iommu() should provide a minimum set of
2780ba7d12ebSYi Liu * useful callbacks for the bus.
2781ba7d12ebSYi Liu */
2782ba7d12ebSYi Liu assert(ops);
2783ba7d12ebSYi Liu assert(ops->get_address_space);
2784ba7d12ebSYi Liu
2785ba7d12ebSYi Liu bus->iommu_ops = ops;
2786e00387d5SAvi Kivity bus->iommu_opaque = opaque;
2787315a1350SMichael S. Tsirkin }
2788315a1350SMichael S. Tsirkin
pci_dev_get_w64(PCIBus * b,PCIDevice * dev,void * opaque)278943864069SMichael S. Tsirkin static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque)
279043864069SMichael S. Tsirkin {
279143864069SMichael S. Tsirkin Range *range = opaque;
279243864069SMichael S. Tsirkin uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND);
279377d6f4eaSMichael S. Tsirkin int i;
279443864069SMichael S. Tsirkin
279543864069SMichael S. Tsirkin if (!(cmd & PCI_COMMAND_MEMORY)) {
279643864069SMichael S. Tsirkin return;
279743864069SMichael S. Tsirkin }
279843864069SMichael S. Tsirkin
2799ad494274SIgor Mammedov if (IS_PCI_BRIDGE(dev)) {
280043864069SMichael S. Tsirkin pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
280143864069SMichael S. Tsirkin pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
280243864069SMichael S. Tsirkin
280343864069SMichael S. Tsirkin base = MAX(base, 0x1ULL << 32);
280443864069SMichael S. Tsirkin
280543864069SMichael S. Tsirkin if (limit >= base) {
280643864069SMichael S. Tsirkin Range pref_range;
2807a0efbf16SMarkus Armbruster range_set_bounds(&pref_range, base, limit);
280843864069SMichael S. Tsirkin range_extend(range, &pref_range);
280943864069SMichael S. Tsirkin }
281043864069SMichael S. Tsirkin }
281177d6f4eaSMichael S. Tsirkin for (i = 0; i < PCI_NUM_REGIONS; ++i) {
281277d6f4eaSMichael S. Tsirkin PCIIORegion *r = &dev->io_regions[i];
2813a0efbf16SMarkus Armbruster pcibus_t lob, upb;
281443864069SMichael S. Tsirkin Range region_range;
281543864069SMichael S. Tsirkin
281677d6f4eaSMichael S. Tsirkin if (!r->size ||
281777d6f4eaSMichael S. Tsirkin (r->type & PCI_BASE_ADDRESS_SPACE_IO) ||
281877d6f4eaSMichael S. Tsirkin !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) {
281943864069SMichael S. Tsirkin continue;
282043864069SMichael S. Tsirkin }
282177d6f4eaSMichael S. Tsirkin
2822a0efbf16SMarkus Armbruster lob = pci_bar_address(dev, i, r->type, r->size);
2823a0efbf16SMarkus Armbruster upb = lob + r->size - 1;
2824a0efbf16SMarkus Armbruster if (lob == PCI_BAR_UNMAPPED) {
282577d6f4eaSMichael S. Tsirkin continue;
282677d6f4eaSMichael S. Tsirkin }
282743864069SMichael S. Tsirkin
2828a0efbf16SMarkus Armbruster lob = MAX(lob, 0x1ULL << 32);
282943864069SMichael S. Tsirkin
2830a0efbf16SMarkus Armbruster if (upb >= lob) {
2831a0efbf16SMarkus Armbruster range_set_bounds(®ion_range, lob, upb);
283243864069SMichael S. Tsirkin range_extend(range, ®ion_range);
283343864069SMichael S. Tsirkin }
283443864069SMichael S. Tsirkin }
283543864069SMichael S. Tsirkin }
283643864069SMichael S. Tsirkin
pci_bus_get_w64_range(PCIBus * bus,Range * range)283743864069SMichael S. Tsirkin void pci_bus_get_w64_range(PCIBus *bus, Range *range)
283843864069SMichael S. Tsirkin {
2839a0efbf16SMarkus Armbruster range_make_empty(range);
284043864069SMichael S. Tsirkin pci_for_each_device_under_bus(bus, pci_dev_get_w64, range);
284143864069SMichael S. Tsirkin }
284243864069SMichael S. Tsirkin
pcie_has_upstream_port(PCIDevice * dev)28433f1e1478SCao jin static bool pcie_has_upstream_port(PCIDevice *dev)
28443f1e1478SCao jin {
2845fd56e061SDavid Gibson PCIDevice *parent_dev = pci_bridge_get_device(pci_get_bus(dev));
28463f1e1478SCao jin
28473f1e1478SCao jin /* Device associated with an upstream port.
28483f1e1478SCao jin * As there are several types of these, it's easier to check the
28493f1e1478SCao jin * parent device: upstream ports are always connected to
28503f1e1478SCao jin * root or downstream ports.
28513f1e1478SCao jin */
28523f1e1478SCao jin return parent_dev &&
28533f1e1478SCao jin pci_is_express(parent_dev) &&
28543f1e1478SCao jin parent_dev->exp.exp_cap &&
28553f1e1478SCao jin (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT ||
28563f1e1478SCao jin pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM);
28573f1e1478SCao jin }
28583f1e1478SCao jin
pci_get_function_0(PCIDevice * pci_dev)28593f1e1478SCao jin PCIDevice *pci_get_function_0(PCIDevice *pci_dev)
28603f1e1478SCao jin {
2861fd56e061SDavid Gibson PCIBus *bus = pci_get_bus(pci_dev);
2862fd56e061SDavid Gibson
28633f1e1478SCao jin if(pcie_has_upstream_port(pci_dev)) {
28643f1e1478SCao jin /* With an upstream PCIe port, we only support 1 device at slot 0 */
2865fd56e061SDavid Gibson return bus->devices[0];
28663f1e1478SCao jin } else {
28673f1e1478SCao jin /* Other bus types might support multiple devices at slots 0-31 */
2868fd56e061SDavid Gibson return bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)];
28693f1e1478SCao jin }
28703f1e1478SCao jin }
28713f1e1478SCao jin
pci_get_msi_message(PCIDevice * dev,int vector)2872e1d4fb2dSPeter Xu MSIMessage pci_get_msi_message(PCIDevice *dev, int vector)
2873e1d4fb2dSPeter Xu {
2874e1d4fb2dSPeter Xu MSIMessage msg;
2875e1d4fb2dSPeter Xu if (msix_enabled(dev)) {
2876e1d4fb2dSPeter Xu msg = msix_get_message(dev, vector);
2877e1d4fb2dSPeter Xu } else if (msi_enabled(dev)) {
2878e1d4fb2dSPeter Xu msg = msi_get_message(dev, vector);
2879e1d4fb2dSPeter Xu } else {
2880e1d4fb2dSPeter Xu /* Should never happen */
2881e1d4fb2dSPeter Xu error_report("%s: unknown interrupt type", __func__);
2882e1d4fb2dSPeter Xu abort();
2883e1d4fb2dSPeter Xu }
2884e1d4fb2dSPeter Xu return msg;
2885e1d4fb2dSPeter Xu }
2886e1d4fb2dSPeter Xu
pci_set_power(PCIDevice * d,bool state)2887*93829009SMichael S. Tsirkin void pci_set_power(PCIDevice *d, bool state)
288823786d13SGerd Hoffmann {
2889*93829009SMichael S. Tsirkin if (d->has_power == state) {
289023786d13SGerd Hoffmann return;
289123786d13SGerd Hoffmann }
289223786d13SGerd Hoffmann
2893*93829009SMichael S. Tsirkin d->has_power = state;
289423786d13SGerd Hoffmann pci_update_mappings(d);
289523786d13SGerd Hoffmann memory_region_set_enabled(&d->bus_master_enable_region,
289623786d13SGerd Hoffmann (pci_get_word(d->config + PCI_COMMAND)
2897*93829009SMichael S. Tsirkin & PCI_COMMAND_MASTER) && d->has_power);
2898*93829009SMichael S. Tsirkin if (!d->has_power) {
289923786d13SGerd Hoffmann pci_device_reset(d);
290023786d13SGerd Hoffmann }
290123786d13SGerd Hoffmann }
290223786d13SGerd Hoffmann
29038c43a6f0SAndreas Färber static const TypeInfo pci_device_type_info = {
2904315a1350SMichael S. Tsirkin .name = TYPE_PCI_DEVICE,
2905315a1350SMichael S. Tsirkin .parent = TYPE_DEVICE,
2906315a1350SMichael S. Tsirkin .instance_size = sizeof(PCIDevice),
2907315a1350SMichael S. Tsirkin .abstract = true,
2908315a1350SMichael S. Tsirkin .class_size = sizeof(PCIDeviceClass),
2909315a1350SMichael S. Tsirkin .class_init = pci_device_class_init,
29102fefa16cSEduardo Habkost .class_base_init = pci_device_class_base_init,
2911315a1350SMichael S. Tsirkin };
2912315a1350SMichael S. Tsirkin
pci_register_types(void)2913315a1350SMichael S. Tsirkin static void pci_register_types(void)
2914315a1350SMichael S. Tsirkin {
2915315a1350SMichael S. Tsirkin type_register_static(&pci_bus_info);
29163a861c46SAlex Williamson type_register_static(&pcie_bus_info);
29174f8db871SBen Widawsky type_register_static(&cxl_bus_info);
2918619f02aeSEduardo Habkost type_register_static(&conventional_pci_interface_info);
2919cf04aba2SBen Widawsky type_register_static(&cxl_interface_info);
2920619f02aeSEduardo Habkost type_register_static(&pcie_interface_info);
2921315a1350SMichael S. Tsirkin type_register_static(&pci_device_type_info);
2922315a1350SMichael S. Tsirkin }
2923315a1350SMichael S. Tsirkin
2924315a1350SMichael S. Tsirkin type_init(pci_register_types)
2925