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Searched refs:val (Results 1 – 25 of 2060) sorted by relevance

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/openbmc/u-boot/include/bedbug/
H A Dregs.h169 #define SET_REGISTER( str, val ) \ argument
170 ({ unsigned long __value = (val); \
180 #define SET_CR(val) SET_REGISTER( "mtcr %0", val ) argument
182 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val ) argument
184 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val ) argument
186 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val ) argument
188 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val ) argument
190 #define SET_DSISR(val) SET_REGISTER( "mtspr 18,%0", val ) argument
192 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val ) argument
194 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val ) argument
[all …]
/openbmc/qemu/target/hppa/
H A Dgdbstub.c33 uint32_t val; in hppa_cpu_gdb_read_register() local
37 val = cpu_hppa_get_psw(env); in hppa_cpu_gdb_read_register()
40 val = env->gr[n]; in hppa_cpu_gdb_read_register()
43 val = env->cr[CR_SAR]; in hppa_cpu_gdb_read_register()
46 val = env->iaoq_f; in hppa_cpu_gdb_read_register()
49 val = env->iasq_f >> 32; in hppa_cpu_gdb_read_register()
52 val = env->iaoq_b; in hppa_cpu_gdb_read_register()
55 val = env->iasq_b >> 32; in hppa_cpu_gdb_read_register()
58 val = env->cr[CR_EIEM]; in hppa_cpu_gdb_read_register()
61 val = env->cr[CR_IIR]; in hppa_cpu_gdb_read_register()
[all …]
/openbmc/qemu/util/
H A Ds390x_pci_mmio.c34 uint64_t val; in s390x_pcilgi() local
42 : [cc] "=d"(cc), [val] "=d"(val), in s390x_pcilgi()
46 val = -1ULL; in s390x_pcilgi()
49 return val; in s390x_pcilgi()
52 static void s390x_pcistgi(void *ioaddr, uint64_t val, size_t len) in s390x_pcistgi() argument
60 : [val] "d" (val) in s390x_pcistgi()
66 uint8_t val = 0; in s390x_pci_mmio_read_8() local
69 val = s390x_pcilgi(ioaddr, sizeof(val)); in s390x_pci_mmio_read_8()
71 syscall(__NR_s390_pci_mmio_read, ioaddr, &val, sizeof(val)); in s390x_pci_mmio_read_8()
73 return val; in s390x_pci_mmio_read_8()
[all …]
H A Dlockcnt.c58 static bool qemu_lockcnt_cmpxchg_or_wait(QemuLockCnt *lockcnt, int *val, in qemu_lockcnt_cmpxchg_or_wait() argument
62 if ((*val & QEMU_LOCKCNT_STATE_MASK) == QEMU_LOCKCNT_STATE_FREE) { in qemu_lockcnt_cmpxchg_or_wait()
63 int expected = *val; in qemu_lockcnt_cmpxchg_or_wait()
66 *val = qatomic_cmpxchg(&lockcnt->count, expected, new_if_free); in qemu_lockcnt_cmpxchg_or_wait()
67 if (*val == expected) { in qemu_lockcnt_cmpxchg_or_wait()
69 *val = new_if_free; in qemu_lockcnt_cmpxchg_or_wait()
80 while ((*val & QEMU_LOCKCNT_STATE_MASK) != QEMU_LOCKCNT_STATE_FREE) { in qemu_lockcnt_cmpxchg_or_wait()
81 if ((*val & QEMU_LOCKCNT_STATE_MASK) == QEMU_LOCKCNT_STATE_LOCKED) { in qemu_lockcnt_cmpxchg_or_wait()
82 int expected = *val; in qemu_lockcnt_cmpxchg_or_wait()
86 *val = qatomic_cmpxchg(&lockcnt->count, expected, new); in qemu_lockcnt_cmpxchg_or_wait()
[all …]
/openbmc/u-boot/drivers/net/phy/
H A Dmv88e61xx.c224 int val; in mv88e61xx_smi_wait() local
228 val = bus->read(bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG); in mv88e61xx_smi_wait()
229 if (val >= 0 && (val & SMI_BUSY) == 0) in mv88e61xx_smi_wait()
292 u16 val) in mv88e61xx_reg_write() argument
302 val); in mv88e61xx_reg_write()
312 SMI_DATA_REG, val); in mv88e61xx_reg_write()
332 int val; in mv88e61xx_phy_wait() local
336 val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2, in mv88e61xx_phy_wait()
338 if (val >= 0 && (val & SMI_BUSY) == 0) in mv88e61xx_phy_wait()
403 int reg, u16 val) in mv88e61xx_phy_write() argument
[all …]
/openbmc/u-boot/arch/microblaze/include/asm/
H A Dasm.h9 #define NGET(val, fslnum) \ argument
10 __asm__ __volatile__ ("nget %0, rfsl" #fslnum :"=r" (val));
12 #define GET(val, fslnum) \ argument
13 __asm__ __volatile__ ("get %0, rfsl" #fslnum :"=r" (val));
15 #define NCGET(val, fslnum) \ argument
16 __asm__ __volatile__ ("ncget %0, rfsl" #fslnum :"=r" (val));
18 #define CGET(val, fslnum) \ argument
19 __asm__ __volatile__ ("cget %0, rfsl" #fslnum :"=r" (val));
21 #define NPUT(val, fslnum) \ argument
22 __asm__ __volatile__ ("nput %0, rfsl" #fslnum ::"r" (val));
[all …]
/openbmc/u-boot/arch/x86/include/asm/
H A Dcontrol_regs.h24 unsigned long val; in read_cr0() local
26 asm volatile ("movl %%cr0, %0" : "=r" (val) : : "memory"); in read_cr0()
27 return val; in read_cr0()
30 static inline void write_cr0(unsigned long val) in write_cr0() argument
32 asm volatile ("movl %0, %%cr0" : : "r" (val) : "memory"); in write_cr0()
37 unsigned long val; in read_cr2() local
39 asm volatile("mov %%cr2,%0\n\t" : "=r" (val) : : "memory"); in read_cr2()
40 return val; in read_cr2()
45 unsigned long val; in read_cr3() local
47 asm volatile("mov %%cr3,%0\n\t" : "=r" (val) : : "memory"); in read_cr3()
[all …]
H A Dmsr.h63 #define DECLARE_ARGS(val, low, high) unsigned low, high argument
64 #define EAX_EDX_VAL(val, low, high) ((low) | ((u64)(high) << 32)) argument
65 #define EAX_EDX_ARGS(val, low, high) "a" (low), "d" (high) argument
66 #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) argument
68 #define DECLARE_ARGS(val, low, high) unsigned long long val argument
69 #define EAX_EDX_VAL(val, low, high) (val) argument
70 #define EAX_EDX_ARGS(val, low, high) "A" (val) argument
71 #define EAX_EDX_RET(val, low, high) "=A" (val) argument
77 DECLARE_ARGS(val, low, high); in native_read_msr()
79 asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr)); in native_read_msr()
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/openbmc/u-boot/drivers/usb/phy/
H A Domap_usb_phy.c68 u32 val; in omap_usb_dpll_relock() local
72 val = readl(&phy_regs->pll_status); in omap_usb_dpll_relock()
73 if (val & PLL_LOCK) in omap_usb_dpll_relock()
81 u32 val; in omap_usb_dpll_lock() local
87 val = readl(&phy_regs->pll_config_1); in omap_usb_dpll_lock()
88 val &= ~PLL_REGN_MASK; in omap_usb_dpll_lock()
89 val |= dpll_params->n << PLL_REGN_SHIFT; in omap_usb_dpll_lock()
90 writel(val, &phy_regs->pll_config_1); in omap_usb_dpll_lock()
92 val = readl(&phy_regs->pll_config_2); in omap_usb_dpll_lock()
93 val &= ~PLL_SELFREQDCO_MASK; in omap_usb_dpll_lock()
[all …]
/openbmc/u-boot/arch/mips/include/asm/
H A Dmipsregs.h880 #define write_r10k_perf_cntr(counter,val) \ argument
885 : "r" (val), "i" (counter)); \
899 #define write_r10k_perf_cntl(counter,val) \ argument
904 : "r" (val), "i" (counter)); \
983 #define __write_ulong_c0_register(reg, sel, val) \ argument
986 __write_32bit_c0_register(reg, sel, val); \
988 __write_64bit_c0_register(reg, sel, val); \
1039 #define __write_64bit_c0_split(source, sel, val) \ argument
1050 : : "r" (val)); \
1060 : : "r" (val)); \
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/
H A Dpipe3-phy.c87 u32 val; in omap_pipe3_wait_lock() local
92 val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); in omap_pipe3_wait_lock()
93 if (val & PLL_LOCK) in omap_pipe3_wait_lock()
97 if (!(val & PLL_LOCK)) { in omap_pipe3_wait_lock()
107 u32 val; in omap_pipe3_dpll_program() local
116 val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); in omap_pipe3_dpll_program()
117 val &= ~PLL_REGN_MASK; in omap_pipe3_dpll_program()
118 val |= dpll_params->n << PLL_REGN_SHIFT; in omap_pipe3_dpll_program()
119 omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); in omap_pipe3_dpll_program()
121 val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); in omap_pipe3_dpll_program()
[all …]
/openbmc/qemu/hw/i386/
H A Dintel_iommu_internal.h132 #define VTD_TLB_DID(val) (((val) >> 32) & VTD_DOMAIN_ID_MASK) argument
135 #define VTD_IVA_ADDR(val) ((val) & ~0xfffULL) argument
136 #define VTD_IVA_AM(val) ((val) & 0x3fULL) argument
170 #define VTD_CCMD_DID(val) ((val) & VTD_DOMAIN_ID_MASK) argument
171 #define VTD_CCMD_SID(val) (((val) >> 16) & 0xffffULL) argument
172 #define VTD_CCMD_FM(val) (((val) >> 32) & 3ULL) argument
231 #define VTD_IQT_QT(dw_bit, val) (dw_bit ? (((val) >> 5) & 0x3fffULL) : \ argument
232 (((val) >> 4) & 0x7fffULL))
254 #define VTD_FSTS_FRI(val) ((((uint32_t)(val)) << 8) & VTD_FSTS_FRI_MASK) argument
267 #define VTD_FRCD_FR(val) (((val) & 0xffULL) << 32) argument
[all …]
/openbmc/u-boot/arch/sh/include/asm/
H A Dunaligned-sh4a.h96 static inline void __put_le16_noalign(u8 *p, u16 val) in __put_le16_noalign() argument
98 *p++ = val; in __put_le16_noalign()
99 *p++ = val >> 8; in __put_le16_noalign()
102 static inline void __put_le32_noalign(u8 *p, u32 val) in __put_le32_noalign() argument
104 __put_le16_noalign(p, val); in __put_le32_noalign()
105 __put_le16_noalign(p + 2, val >> 16); in __put_le32_noalign()
108 static inline void __put_le64_noalign(u8 *p, u64 val) in __put_le64_noalign() argument
110 __put_le32_noalign(p, val); in __put_le64_noalign()
111 __put_le32_noalign(p + 4, val >> 32); in __put_le64_noalign()
114 static inline void __put_be16_noalign(u8 *p, u16 val) in __put_be16_noalign() argument
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/openbmc/u-boot/drivers/usb/ulpi/
H A Dulpi.c33 u32 val, tval = ULPI_TEST_VALUE; in ulpi_integrity_check() local
42 val = ulpi_read(ulpi_vp, &ulpi->scratch); in ulpi_integrity_check()
43 if (val != tval) { in ulpi_integrity_check()
45 return val; in ulpi_integrity_check()
54 u32 val, id = 0; in ulpi_init() local
60 val = ulpi_read(ulpi_vp, reg - i); in ulpi_init()
61 if (val == ULPI_ERROR) in ulpi_init()
62 return val; in ulpi_init()
64 id = (id << 8) | val; in ulpi_init()
76 u32 val; in ulpi_select_transceiver() local
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/openbmc/u-boot/arch/arm/mach-exynos/
H A Ddmc_init_ddr3.c37 unsigned int val; in ddr3_mem_ctrl_init() local
51 val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) | in ddr3_mem_ctrl_init()
55 writel(val, &phy0_ctrl->phy_con39); in ddr3_mem_ctrl_init()
56 writel(val, &phy1_ctrl->phy_con39); in ddr3_mem_ctrl_init()
59 val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) | in ddr3_mem_ctrl_init()
61 writel(val, &phy0_ctrl->phy_con42); in ddr3_mem_ctrl_init()
62 writel(val, &phy1_ctrl->phy_con42); in ddr3_mem_ctrl_init()
89 val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) | in ddr3_mem_ctrl_init()
93 writel(val, &phy0_ctrl->phy_con12); in ddr3_mem_ctrl_init()
94 writel(val, &phy1_ctrl->phy_con12); in ddr3_mem_ctrl_init()
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/
H A Dmemconf.c19 u32 val = 0; in __uniphier_memconf_init() local
25 val |= SG_MEMCONF_CH0_NUM_1; in __uniphier_memconf_init()
29 val |= SG_MEMCONF_CH0_NUM_2; in __uniphier_memconf_init()
39 val |= SG_MEMCONF_CH0_SZ_64M; in __uniphier_memconf_init()
42 val |= SG_MEMCONF_CH0_SZ_128M; in __uniphier_memconf_init()
45 val |= SG_MEMCONF_CH0_SZ_256M; in __uniphier_memconf_init()
48 val |= SG_MEMCONF_CH0_SZ_512M; in __uniphier_memconf_init()
51 val |= SG_MEMCONF_CH0_SZ_1G; in __uniphier_memconf_init()
61 val |= SG_MEMCONF_CH1_NUM_1; in __uniphier_memconf_init()
65 val |= SG_MEMCONF_CH1_NUM_2; in __uniphier_memconf_init()
[all …]
/openbmc/u-boot/arch/arm/mach-imx/
H A Dcache.c14 u32 val; in enable_ca7_smp() local
17 asm volatile ("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(val)); in enable_ca7_smp()
18 val = (val >> 4); in enable_ca7_smp()
19 val &= 0xf; in enable_ca7_smp()
22 if (val == 0x7) { in enable_ca7_smp()
24 asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(val)); in enable_ca7_smp()
26 if (val & (1 << 6)) in enable_ca7_smp()
30 val |= (1 << 6); in enable_ca7_smp()
33 asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(val)); in enable_ca7_smp()
85 unsigned int val, cache_id; in v7_outer_cache_enable() local
[all …]
/openbmc/qemu/hw/virtio/
H A Dvirtio-config-io.c18 uint8_t val; in virtio_config_readb() local
20 if (addr + sizeof(val) > vdev->config_len) { in virtio_config_readb()
26 val = ldub_p(vdev->config + addr); in virtio_config_readb()
27 return val; in virtio_config_readb()
33 uint16_t val; in virtio_config_readw() local
35 if (addr + sizeof(val) > vdev->config_len) { in virtio_config_readw()
41 val = lduw_p(vdev->config + addr); in virtio_config_readw()
42 return val; in virtio_config_readw()
48 uint32_t val; in virtio_config_readl() local
50 if (addr + sizeof(val) > vdev->config_len) { in virtio_config_readl()
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/
H A Dpinmux-common.c161 u32 val; in pinmux_set_func() local
183 val = readl(reg); in pinmux_set_func()
184 val &= ~(3 << MUX_SHIFT(pin)); in pinmux_set_func()
185 val |= (mux << MUX_SHIFT(pin)); in pinmux_set_func()
186 writel(val, reg); in pinmux_set_func()
192 u32 val; in pinmux_set_pullupdown() local
198 val = readl(reg); in pinmux_set_pullupdown()
199 val &= ~(3 << PULL_SHIFT(pin)); in pinmux_set_pullupdown()
200 val |= (pupd << PULL_SHIFT(pin)); in pinmux_set_pullupdown()
201 writel(val, reg); in pinmux_set_pullupdown()
[all …]
/openbmc/u-boot/drivers/bios_emulator/
H A Dbesys.c143 u8 val = readb_le(BE_memaddr(addr)); in BE_rdb() local
144 return val; in BE_rdb()
165 u16 val = readw_le(base); in BE_rdw() local
166 return val; in BE_rdw()
187 u32 val = readl_le(base); in BE_rdl() local
188 return val; in BE_rdl()
201 void X86API BE_wrb(u32 addr, u8 val) in BE_wrb() argument
204 writeb_le(BE_memaddr(addr), val); in BE_wrb()
217 void X86API BE_wrw(u32 addr, u16 val) in BE_wrw() argument
221 writew_le(base, val); in BE_wrw()
[all …]
/openbmc/qemu/target/i386/tcg/system/
H A Dmisc_helper.c134 uint64_t val; in helper_wrmsr() local
139 val = ((uint32_t)env->regs[R_EAX]) | in helper_wrmsr()
144 env->sysenter_cs = val & 0xffff; in helper_wrmsr()
147 env->sysenter_esp = val; in helper_wrmsr()
150 env->sysenter_eip = val; in helper_wrmsr()
155 if (val & MSR_IA32_APICBASE_RESERVED) { in helper_wrmsr()
159 ret = cpu_set_apic_base(env_archcpu(env)->apic_state, val); in helper_wrmsr()
189 (val & update_mask)); in helper_wrmsr()
193 env->star = val; in helper_wrmsr()
196 env->pat = val; in helper_wrmsr()
[all …]
/openbmc/qemu/hw/audio/
H A Dhda-codec-common.h48 .val = ((AC_WID_AUD_OUT << AC_WCAP_TYPE_SHIFT) |
55 .val = QEMU_HDA_PCM_FORMATS,
58 .val = AC_SUPFMT_PCM,
61 .val = QEMU_HDA_AMP_NONE,
64 .val = QEMU_HDA_AMP_CAPS,
72 .val = ((AC_WID_AUD_IN << AC_WCAP_TYPE_SHIFT) |
80 .val = 1,
83 .val = QEMU_HDA_PCM_FORMATS,
86 .val = AC_SUPFMT_PCM,
89 .val = QEMU_HDA_AMP_CAPS,
[all …]
/openbmc/u-boot/drivers/usb/dwc3/
H A Dti_usb_phy.c135 u32 val; in ti_usb3_dpll_wait_lock() local
137 val = ti_usb3_readl(phy->pll_ctrl_base, PLL_STATUS); in ti_usb3_dpll_wait_lock()
138 if (val & PLL_LOCK) in ti_usb3_dpll_wait_lock()
147 u32 val; in ti_usb3_dpll_program() local
157 val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); in ti_usb3_dpll_program()
158 val &= ~PLL_REGN_MASK; in ti_usb3_dpll_program()
159 val |= dpll_params->n << PLL_REGN_SHIFT; in ti_usb3_dpll_program()
160 ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); in ti_usb3_dpll_program()
162 val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); in ti_usb3_dpll_program()
163 val &= ~PLL_SELFREQDCO_MASK; in ti_usb3_dpll_program()
[all …]
/openbmc/u-boot/drivers/phy/
H A Dti-pipe3-phy.c109 u32 val; in omap_pipe3_wait_lock() local
114 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS); in omap_pipe3_wait_lock()
115 if (val & PLL_LOCK) in omap_pipe3_wait_lock()
119 if (!(val & PLL_LOCK)) { in omap_pipe3_wait_lock()
129 u32 val; in omap_pipe3_dpll_program() local
138 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1); in omap_pipe3_dpll_program()
139 val &= ~PLL_REGN_MASK; in omap_pipe3_dpll_program()
140 val |= dpll_params->n << PLL_REGN_SHIFT; in omap_pipe3_dpll_program()
141 omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val); in omap_pipe3_dpll_program()
143 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2); in omap_pipe3_dpll_program()
[all …]
/openbmc/qemu/hw/ide/
H A Dsii3112.c46 uint64_t val; in sii3112_reg_read() local
50 val = d->i.bmdma[0].cmd; in sii3112_reg_read()
53 val = d->regs[0].swdata; in sii3112_reg_read()
56 val = d->i.bmdma[0].status; in sii3112_reg_read()
59 val = 0; in sii3112_reg_read()
62 val = bmdma_addr_ioport_ops.read(&d->i.bmdma[0], addr - 4, size); in sii3112_reg_read()
65 val = d->i.bmdma[1].cmd; in sii3112_reg_read()
68 val = d->regs[1].swdata; in sii3112_reg_read()
71 val = d->i.bmdma[1].status; in sii3112_reg_read()
74 val = 0; in sii3112_reg_read()
[all …]

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