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Searched refs:ufshcd_readl (Results 1 – 15 of 15) sorted by relevance

/openbmc/linux/drivers/ufs/host/
H A Dufs-qcom.h139 u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION); in ufs_qcom_get_controller_revision()
155 ufshcd_readl(hba, REG_UFS_CFG1); in ufs_qcom_assert_reset()
167 ufshcd_readl(hba, REG_UFS_CFG1); in ufs_qcom_deassert_reset()
H A Dcdns-pltfrm.c139 ufshcd_readl(hba, CDNS_UFS_REG_HCLKDIV); in cdns_ufs_set_hclkdiv()
240 data = ufshcd_readl(hba, CDNS_UFS_REG_PHY_XCFGD1); in cdns_ufs_m31_16nm_phy_initialization()
H A Dufs-qcom.c439 return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0)); in ufs_qcom_get_hs_gear()
497 ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL, in ufs_qcom_enable_hw_clk_gating()
501 ufshcd_readl(hba, REG_UFS_CFG2); in ufs_qcom_enable_hw_clk_gating()
591 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) { in ufs_qcom_cfg_timers()
597 ufshcd_readl(hba, REG_UFS_SYS1CLK_1US); in ufs_qcom_cfg_timers()
651 if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) != in ufs_qcom_cfg_timers()
1558 reg = ufshcd_readl(hba, REG_UFS_CFG1); in ufs_qcom_dump_dbg_regs()
1854 ufshcd_readl(hba, REG_UFS_CFG3) | 0x1F000, in ufs_qcom_config_esi()
H A Dufs-mediatek.c237 ufshcd_readl(hba, REG_UFS_XOUFS_CTRL) | 0x80, in ufs_mtk_hce_enable_notify()
305 value = ufshcd_readl(hba, REG_UFS_REFCLK_CTRL); in ufs_mtk_setup_ref_clk()
377 val = ufshcd_readl(hba, REG_UFS_PROBE); in ufs_mtk_wait_idle_state()
410 val = ufshcd_readl(hba, REG_UFS_PROBE); in ufs_mtk_wait_link_state()
960 host->ip_ver = ufshcd_readl(hba, REG_UFS_MTK_IP_VER); in ufs_mtk_init()
1223 ufshcd_writel(hba, ufshcd_readl(hba, REG_UFS_MEM_CFG) | 0x1, in ufs_mtk_link_set_hpm()
1239 (ufshcd_readl(hba, REG_UFS_XOUFS_CTRL) & ~0x100), in ufs_mtk_link_set_lpm()
H A Dufs-sprd.c53 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); in ufs_sprd_ctrl_uic_compl()
228 val = ufshcd_readl(hba, REG_CONTROLLER_ENABLE); in ufs_sprd_n6_key_acc_enable()
H A Dufs-renesas.c297 save[p->index] = ufshcd_readl(hba, p->reg) & p->mask; in ufs_renesas_reg_control()
H A Dufs-hisi.c235 reg = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER); in ufs_hisi_link_startup_pre_change()
H A Dufshcd-pci.c102 u32 hce = ufshcd_readl(hba, REG_CONTROLLER_ENABLE); in ufs_intel_hce_enable_notify()
H A Dufs-exynos.c299 enabled_vh = ufshcd_readl(hba, MHCTRL) & MHCTRL_EN_VH_MASK; in exynosauto_ufs_post_pwr_change()
1433 mbox = ufshcd_readl(hba, PH2VH_MBOX); in exynosauto_ufs_vh_wait_ph_ready()
/openbmc/linux/drivers/ufs/core/
H A Dufshcd-crypto.c172 cpu_to_le32(ufshcd_readl(hba, REG_UFS_CCAP)); in ufshcd_hba_init_crypto_capabilities()
202 cpu_to_le32(ufshcd_readl(hba, in ufshcd_hba_init_crypto_capabilities()
H A Dufshcd.c147 regs[pos / 4] = ufshcd_readl(hba, offset + pos); in ufshcd_dump_regs()
393 cmd = ufshcd_readl(hba, REG_UIC_COMMAND); in ufshcd_add_uic_command_trace()
396 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1), in ufshcd_add_uic_command_trace()
397 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2), in ufshcd_add_uic_command_trace()
398 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3)); in ufshcd_add_uic_command_trace()
441 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS); in ufshcd_add_command_trace()
717 while ((ufshcd_readl(hba, reg) & mask) != val) { in ufshcd_wait_for_register()
720 if ((ufshcd_readl(hba, reg) & mask) != val) in ufshcd_wait_for_register()
874 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3); in ufshcd_get_dme_attr_val()
4153 ufshcd_readl(hba, REG_INTERRUPT_ENABLE); in ufshcd_uic_pwr_ctrl()
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H A Dufs-mcq.c95 val = ufshcd_readl(hba, REG_UFS_MCQ_CFG); in ufshcd_mcq_config_mac()
394 ufshcd_writel(hba, ufshcd_readl(hba, REG_UFS_MEM_CFG) | 0x2, in ufshcd_mcq_enable_esi()
H A Dufshcd-priv.h121 return ufshcd_readl(hba, REG_UFS_VERSION); in ufshcd_vops_get_ufs_hci_version()
H A Dufs-sysfs.c172 ahit = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER); in auto_hibern8_show()
/openbmc/linux/include/ufs/
H A Dufshcd.h1220 #define ufshcd_readl(hba, reg) \ macro
1234 tmp = ufshcd_readl(hba, reg); in ufshcd_rmwl()