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Searched refs:timing_cfg_4 (Results 1 – 20 of 20) sorted by relevance

/openbmc/u-boot/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c101 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
133 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
165 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
197 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
229 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
261 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
293 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
325 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
/openbmc/u-boot/board/freescale/bsc9132qds/
H A Dspl_minimal.c38 __raw_writel(CONFIG_SYS_DDR_TIMING_4_800, &ddr->timing_cfg_4); in sdram_init()
58 __raw_writel(CONFIG_SYS_DDR_TIMING_4_1333, &ddr->timing_cfg_4); in sdram_init()
H A Dddr.c35 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
62 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
/openbmc/u-boot/board/freescale/p1010rdb/
H A Dddr.c38 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
65 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
/openbmc/u-boot/board/freescale/p1_twr/
H A Dddr.c44 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, in fixed_sdram()
/openbmc/u-boot/board/freescale/ls1043ardb/
H A Dddr.h87 .timing_cfg_4 = 0x00000002,
/openbmc/u-boot/drivers/ddr/fsl/
H A Darm_ddr_gen3.c107 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4); in fsl_ddr_set_memctl_regs()
H A Dmpc85xx_ddr_gen3.c130 out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4); in fsl_ddr_set_memctl_regs()
H A Dfsl_ddr_gen4.c159 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4); in fsl_ddr_set_memctl_regs()
H A Dctrl_regs.c1937 ddr->timing_cfg_4 = (0 in set_timing_cfg_4()
1945 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4); in set_timing_cfg_4()
H A Dinteractive.c658 CFG_REGS(timing_cfg_4), in print_fsl_memctl_config_regs()
749 CFG_REGS(timing_cfg_4), in fsl_ddr_regs_edit()
/openbmc/u-boot/board/freescale/bsc9131rdb/
H A Dspl_minimal.c45 __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); in sdram_init()
H A Dddr.c36 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
/openbmc/u-boot/board/Arcturus/ucp1020/
H A Dddr.c104 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, in fixed_sdram()
/openbmc/u-boot/board/freescale/ls1021aiot/
H A Dls1021aiot.c60 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); in ddrmc_init()
/openbmc/u-boot/board/freescale/p1_p2_rdb_pc/
H A Dddr.c236 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, in fixed_sdram()
/openbmc/u-boot/include/
H A Dfsl_immap.h50 u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */ member
H A Dfsl_ddr_sdram.h277 unsigned int timing_cfg_4; member
/openbmc/u-boot/board/freescale/mpc8569mds/
H A Dmpc8569mds.c251 out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); in fixed_sdram()
/openbmc/u-boot/board/freescale/ls1021atwr/
H A Dls1021atwr.c152 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); in ddrmc_init()