1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */
25614e71bSYork Sun /*
3c0c32af0SYork Sun * Copyright 2008-2016 Freescale Semiconductor, Inc.
4c0c32af0SYork Sun * Copyright 2017-2018 NXP Semiconductor
55614e71bSYork Sun */
65614e71bSYork Sun
75614e71bSYork Sun #ifndef FSL_DDR_MEMCTL_H
85614e71bSYork Sun #define FSL_DDR_MEMCTL_H
95614e71bSYork Sun
105614e71bSYork Sun /*
115614e71bSYork Sun * Pick a basic DDR Technology.
125614e71bSYork Sun */
135614e71bSYork Sun #include <ddr_spd.h>
1434e026f9SYork Sun #include <fsl_ddrc_version.h>
155614e71bSYork Sun
165614e71bSYork Sun #define SDRAM_TYPE_DDR1 2
175614e71bSYork Sun #define SDRAM_TYPE_DDR2 3
185614e71bSYork Sun #define SDRAM_TYPE_LPDDR1 6
195614e71bSYork Sun #define SDRAM_TYPE_DDR3 7
2034e026f9SYork Sun #define SDRAM_TYPE_DDR4 5
215614e71bSYork Sun
225614e71bSYork Sun #define DDR_BL4 4 /* burst length 4 */
235614e71bSYork Sun #define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */
245614e71bSYork Sun #define DDR_OTF 6 /* on-the-fly BC4 and BL8 */
255614e71bSYork Sun #define DDR_BL8 8 /* burst length 8 */
265614e71bSYork Sun
275614e71bSYork Sun #define DDR3_RTT_OFF 0
285614e71bSYork Sun #define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */
295614e71bSYork Sun #define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */
305614e71bSYork Sun #define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */
315614e71bSYork Sun #define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */
325614e71bSYork Sun #define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */
335614e71bSYork Sun
3419601dd9SYork Sun #define DDR4_RTT_OFF 0
3519601dd9SYork Sun #define DDR4_RTT_60_OHM 1 /* RZQ/4 */
3619601dd9SYork Sun #define DDR4_RTT_120_OHM 2 /* RZQ/2 */
3719601dd9SYork Sun #define DDR4_RTT_40_OHM 3 /* RZQ/6 */
3819601dd9SYork Sun #define DDR4_RTT_240_OHM 4 /* RZQ/1 */
3919601dd9SYork Sun #define DDR4_RTT_48_OHM 5 /* RZQ/5 */
4019601dd9SYork Sun #define DDR4_RTT_80_OHM 6 /* RZQ/3 */
4119601dd9SYork Sun #define DDR4_RTT_34_OHM 7 /* RZQ/7 */
4219601dd9SYork Sun
435614e71bSYork Sun #define DDR2_RTT_OFF 0
445614e71bSYork Sun #define DDR2_RTT_75_OHM 1
455614e71bSYork Sun #define DDR2_RTT_150_OHM 2
465614e71bSYork Sun #define DDR2_RTT_50_OHM 3
475614e71bSYork Sun
485614e71bSYork Sun #if defined(CONFIG_SYS_FSL_DDR1)
495614e71bSYork Sun #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1)
505614e71bSYork Sun typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
515614e71bSYork Sun #ifndef CONFIG_FSL_SDRAM_TYPE
525614e71bSYork Sun #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1
535614e71bSYork Sun #endif
545614e71bSYork Sun #elif defined(CONFIG_SYS_FSL_DDR2)
555614e71bSYork Sun #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3)
565614e71bSYork Sun typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
575614e71bSYork Sun #ifndef CONFIG_FSL_SDRAM_TYPE
585614e71bSYork Sun #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2
595614e71bSYork Sun #endif
605614e71bSYork Sun #elif defined(CONFIG_SYS_FSL_DDR3)
615614e71bSYork Sun typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
625614e71bSYork Sun #ifndef CONFIG_FSL_SDRAM_TYPE
635614e71bSYork Sun #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
645614e71bSYork Sun #endif
6534e026f9SYork Sun #elif defined(CONFIG_SYS_FSL_DDR4)
6634e026f9SYork Sun #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */
6734e026f9SYork Sun typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
6834e026f9SYork Sun #ifndef CONFIG_FSL_SDRAM_TYPE
6934e026f9SYork Sun #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR4
7034e026f9SYork Sun #endif
715614e71bSYork Sun #endif /* #if defined(CONFIG_SYS_FSL_DDR1) */
725614e71bSYork Sun
735614e71bSYork Sun #define FSL_DDR_ODT_NEVER 0x0
745614e71bSYork Sun #define FSL_DDR_ODT_CS 0x1
755614e71bSYork Sun #define FSL_DDR_ODT_ALL_OTHER_CS 0x2
765614e71bSYork Sun #define FSL_DDR_ODT_OTHER_DIMM 0x3
775614e71bSYork Sun #define FSL_DDR_ODT_ALL 0x4
785614e71bSYork Sun #define FSL_DDR_ODT_SAME_DIMM 0x5
795614e71bSYork Sun #define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6
805614e71bSYork Sun #define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7
815614e71bSYork Sun
825614e71bSYork Sun /* define bank(chip select) interleaving mode */
835614e71bSYork Sun #define FSL_DDR_CS0_CS1 0x40
845614e71bSYork Sun #define FSL_DDR_CS2_CS3 0x20
855614e71bSYork Sun #define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
865614e71bSYork Sun #define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)
875614e71bSYork Sun
885614e71bSYork Sun /* define memory controller interleaving mode */
895614e71bSYork Sun #define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0
905614e71bSYork Sun #define FSL_DDR_PAGE_INTERLEAVING 0x1
915614e71bSYork Sun #define FSL_DDR_BANK_INTERLEAVING 0x2
925614e71bSYork Sun #define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
936b1e1254SYork Sun #define FSL_DDR_256B_INTERLEAVING 0x8
945614e71bSYork Sun #define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA
955614e71bSYork Sun #define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC
965614e71bSYork Sun #define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD
975614e71bSYork Sun /* placeholder for 4-way interleaving */
985614e71bSYork Sun #define FSL_DDR_4WAY_1KB_INTERLEAVING 0x1A
995614e71bSYork Sun #define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C
1005614e71bSYork Sun #define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D
1015614e71bSYork Sun
1025614e71bSYork Sun #define SDRAM_CS_CONFIG_EN 0x80000000
1035614e71bSYork Sun
1045614e71bSYork Sun /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
1055614e71bSYork Sun */
1065614e71bSYork Sun #define SDRAM_CFG_MEM_EN 0x80000000
1075614e71bSYork Sun #define SDRAM_CFG_SREN 0x40000000
1085614e71bSYork Sun #define SDRAM_CFG_ECC_EN 0x20000000
1095614e71bSYork Sun #define SDRAM_CFG_RD_EN 0x10000000
1105614e71bSYork Sun #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
1115614e71bSYork Sun #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
1125614e71bSYork Sun #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
1135614e71bSYork Sun #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
1145614e71bSYork Sun #define SDRAM_CFG_DYN_PWR 0x00200000
1155614e71bSYork Sun #define SDRAM_CFG_DBW_MASK 0x00180000
1165614e71bSYork Sun #define SDRAM_CFG_DBW_SHIFT 19
1175614e71bSYork Sun #define SDRAM_CFG_32_BE 0x00080000
1185614e71bSYork Sun #define SDRAM_CFG_16_BE 0x00100000
1195614e71bSYork Sun #define SDRAM_CFG_8_BE 0x00040000
1205614e71bSYork Sun #define SDRAM_CFG_NCAP 0x00020000
1215614e71bSYork Sun #define SDRAM_CFG_2T_EN 0x00008000
1225614e71bSYork Sun #define SDRAM_CFG_BI 0x00000001
1235614e71bSYork Sun
124a7787b78STang Yuantian #define SDRAM_CFG2_FRC_SR 0x80000000
1255614e71bSYork Sun #define SDRAM_CFG2_D_INIT 0x00000010
126eb118807SShengzhou Liu #define SDRAM_CFG2_AP_EN 0x00000020
1275614e71bSYork Sun #define SDRAM_CFG2_ODT_CFG_MASK 0x00600000
1285614e71bSYork Sun #define SDRAM_CFG2_ODT_NEVER 0
1295614e71bSYork Sun #define SDRAM_CFG2_ODT_ONLY_WRITE 1
1305614e71bSYork Sun #define SDRAM_CFG2_ODT_ONLY_READ 2
1315614e71bSYork Sun #define SDRAM_CFG2_ODT_ALWAYS 3
1325614e71bSYork Sun
133a994b3deSShengzhou Liu #define SDRAM_INTERVAL_BSTOPRE 0x3FFF
1345614e71bSYork Sun #define TIMING_CFG_2_CPO_MASK 0x0F800000
1355614e71bSYork Sun
13634e026f9SYork Sun #if defined(CONFIG_SYS_FSL_DDR_VER) && \
13734e026f9SYork Sun (CONFIG_SYS_FSL_DDR_VER > FSL_DDR_VER_4_4)
1385614e71bSYork Sun #define RD_TO_PRE_MASK 0xf
1395614e71bSYork Sun #define RD_TO_PRE_SHIFT 13
1405614e71bSYork Sun #define WR_DATA_DELAY_MASK 0xf
1415614e71bSYork Sun #define WR_DATA_DELAY_SHIFT 9
1425614e71bSYork Sun #else
1435614e71bSYork Sun #define RD_TO_PRE_MASK 0x7
1445614e71bSYork Sun #define RD_TO_PRE_SHIFT 13
1455614e71bSYork Sun #define WR_DATA_DELAY_MASK 0x7
1465614e71bSYork Sun #define WR_DATA_DELAY_SHIFT 10
1475614e71bSYork Sun #endif
1485614e71bSYork Sun
149074596c0SShengzhou Liu /* DDR_EOR register */
150074596c0SShengzhou Liu #define DDR_EOR_RD_REOD_DIS 0x07000000
151074596c0SShengzhou Liu #define DDR_EOR_WD_REOD_DIS 0x00100000
152074596c0SShengzhou Liu
1535614e71bSYork Sun /* DDR_MD_CNTL */
1545614e71bSYork Sun #define MD_CNTL_MD_EN 0x80000000
1555614e71bSYork Sun #define MD_CNTL_CS_SEL_CS0 0x00000000
1565614e71bSYork Sun #define MD_CNTL_CS_SEL_CS1 0x10000000
1575614e71bSYork Sun #define MD_CNTL_CS_SEL_CS2 0x20000000
1585614e71bSYork Sun #define MD_CNTL_CS_SEL_CS3 0x30000000
1595614e71bSYork Sun #define MD_CNTL_CS_SEL_CS0_CS1 0x40000000
1605614e71bSYork Sun #define MD_CNTL_CS_SEL_CS2_CS3 0x50000000
1615614e71bSYork Sun #define MD_CNTL_MD_SEL_MR 0x00000000
1625614e71bSYork Sun #define MD_CNTL_MD_SEL_EMR 0x01000000
1635614e71bSYork Sun #define MD_CNTL_MD_SEL_EMR2 0x02000000
1645614e71bSYork Sun #define MD_CNTL_MD_SEL_EMR3 0x03000000
1655614e71bSYork Sun #define MD_CNTL_SET_REF 0x00800000
1665614e71bSYork Sun #define MD_CNTL_SET_PRE 0x00400000
1675614e71bSYork Sun #define MD_CNTL_CKE_CNTL_LOW 0x00100000
1685614e71bSYork Sun #define MD_CNTL_CKE_CNTL_HIGH 0x00200000
1695614e71bSYork Sun #define MD_CNTL_WRCW 0x00080000
1705614e71bSYork Sun #define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF)
1719f9f0093SYork Sun #define MD_CNTL_CS_SEL(x) (((x) & 0x7) << 28)
1729f9f0093SYork Sun #define MD_CNTL_MD_SEL(x) (((x) & 0xf) << 24)
1735614e71bSYork Sun
1745614e71bSYork Sun /* DDR_CDR1 */
1755614e71bSYork Sun #define DDR_CDR1_DHC_EN 0x80000000
176031acdbaSHou Zhiqiang #define DDR_CDR1_V0PT9_EN 0x40000000
1775614e71bSYork Sun #define DDR_CDR1_ODT_SHIFT 17
1785614e71bSYork Sun #define DDR_CDR1_ODT_MASK 0x6
1795614e71bSYork Sun #define DDR_CDR2_ODT_MASK 0x1
1805614e71bSYork Sun #define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
1815614e71bSYork Sun #define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
18234e026f9SYork Sun #define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8))
183a7787b78STang Yuantian #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
1847288c2c2SYork Sun #define DDR_CDR2_VREF_RANGE_2 0x00000040
1855614e71bSYork Sun
186eb118807SShengzhou Liu /* DDR ERR_DISABLE */
187eb118807SShengzhou Liu #define DDR_ERR_DISABLE_APED (1 << 8) /* Address parity error disable */
188eb118807SShengzhou Liu
189eb118807SShengzhou Liu /* Mode Registers */
190eb118807SShengzhou Liu #define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */
191eb118807SShengzhou Liu #define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */
192eb118807SShengzhou Liu
1935fc62fe5SShengzhou Liu /* DEBUG_26 register */
1945fc62fe5SShengzhou Liu #define DDR_CAS_TO_PRE_SUB_MASK 0x0000f000 /* CAS to preamble subtract value */
1955fc62fe5SShengzhou Liu #define DDR_CAS_TO_PRE_SUB_SHIFT 12
1965fc62fe5SShengzhou Liu
1974a68489eSShengzhou Liu /* DEBUG_29 register */
1984a68489eSShengzhou Liu #define DDR_TX_BD_DIS (1 << 10) /* Transmit Bit Deskew Disable */
1994a68489eSShengzhou Liu
200eb118807SShengzhou Liu
2015614e71bSYork Sun #if (defined(CONFIG_SYS_FSL_DDR_VER) && \
2025614e71bSYork Sun (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
20334e026f9SYork Sun #ifdef CONFIG_SYS_FSL_DDR3L
20434e026f9SYork Sun #define DDR_CDR_ODT_OFF 0x0
20534e026f9SYork Sun #define DDR_CDR_ODT_120ohm 0x1
20634e026f9SYork Sun #define DDR_CDR_ODT_200ohm 0x2
20734e026f9SYork Sun #define DDR_CDR_ODT_75ohm 0x3
20834e026f9SYork Sun #define DDR_CDR_ODT_60ohm 0x5
20934e026f9SYork Sun #define DDR_CDR_ODT_46ohm 0x7
21034e026f9SYork Sun #elif defined(CONFIG_SYS_FSL_DDR4)
21134e026f9SYork Sun #define DDR_CDR_ODT_OFF 0x0
21234e026f9SYork Sun #define DDR_CDR_ODT_100ohm 0x1
21334e026f9SYork Sun #define DDR_CDR_ODT_120OHM 0x2
21434e026f9SYork Sun #define DDR_CDR_ODT_80ohm 0x3
21534e026f9SYork Sun #define DDR_CDR_ODT_60ohm 0x4
21634e026f9SYork Sun #define DDR_CDR_ODT_40ohm 0x5
21734e026f9SYork Sun #define DDR_CDR_ODT_50ohm 0x6
21834e026f9SYork Sun #define DDR_CDR_ODT_30ohm 0x7
21934e026f9SYork Sun #else
2205614e71bSYork Sun #define DDR_CDR_ODT_OFF 0x0
2215614e71bSYork Sun #define DDR_CDR_ODT_120ohm 0x1
2225614e71bSYork Sun #define DDR_CDR_ODT_180ohm 0x2
2235614e71bSYork Sun #define DDR_CDR_ODT_75ohm 0x3
2245614e71bSYork Sun #define DDR_CDR_ODT_110ohm 0x4
2255614e71bSYork Sun #define DDR_CDR_ODT_60hm 0x5
2265614e71bSYork Sun #define DDR_CDR_ODT_70ohm 0x6
2275614e71bSYork Sun #define DDR_CDR_ODT_47ohm 0x7
22834e026f9SYork Sun #endif /* DDR3L */
2295614e71bSYork Sun #else
2305614e71bSYork Sun #define DDR_CDR_ODT_75ohm 0x0
2315614e71bSYork Sun #define DDR_CDR_ODT_55ohm 0x1
2325614e71bSYork Sun #define DDR_CDR_ODT_60ohm 0x2
2335614e71bSYork Sun #define DDR_CDR_ODT_50ohm 0x3
2345614e71bSYork Sun #define DDR_CDR_ODT_150ohm 0x4
2355614e71bSYork Sun #define DDR_CDR_ODT_43ohm 0x5
2365614e71bSYork Sun #define DDR_CDR_ODT_120ohm 0x6
2375614e71bSYork Sun #endif
2385614e71bSYork Sun
239a7787b78STang Yuantian #define DDR_INIT_ADDR_EXT_UIA (1 << 31)
240a7787b78STang Yuantian
2415614e71bSYork Sun /* Record of register values computed */
2425614e71bSYork Sun typedef struct fsl_ddr_cfg_regs_s {
2435614e71bSYork Sun struct {
2445614e71bSYork Sun unsigned int bnds;
2455614e71bSYork Sun unsigned int config;
2465614e71bSYork Sun unsigned int config_2;
2475614e71bSYork Sun } cs[CONFIG_CHIP_SELECTS_PER_CTRL];
2485614e71bSYork Sun unsigned int timing_cfg_3;
2495614e71bSYork Sun unsigned int timing_cfg_0;
2505614e71bSYork Sun unsigned int timing_cfg_1;
2515614e71bSYork Sun unsigned int timing_cfg_2;
2525614e71bSYork Sun unsigned int ddr_sdram_cfg;
2535614e71bSYork Sun unsigned int ddr_sdram_cfg_2;
25434e026f9SYork Sun unsigned int ddr_sdram_cfg_3;
2555614e71bSYork Sun unsigned int ddr_sdram_mode;
2565614e71bSYork Sun unsigned int ddr_sdram_mode_2;
2575614e71bSYork Sun unsigned int ddr_sdram_mode_3;
2585614e71bSYork Sun unsigned int ddr_sdram_mode_4;
2595614e71bSYork Sun unsigned int ddr_sdram_mode_5;
2605614e71bSYork Sun unsigned int ddr_sdram_mode_6;
2615614e71bSYork Sun unsigned int ddr_sdram_mode_7;
2625614e71bSYork Sun unsigned int ddr_sdram_mode_8;
26334e026f9SYork Sun unsigned int ddr_sdram_mode_9;
26434e026f9SYork Sun unsigned int ddr_sdram_mode_10;
26534e026f9SYork Sun unsigned int ddr_sdram_mode_11;
26634e026f9SYork Sun unsigned int ddr_sdram_mode_12;
26734e026f9SYork Sun unsigned int ddr_sdram_mode_13;
26834e026f9SYork Sun unsigned int ddr_sdram_mode_14;
26934e026f9SYork Sun unsigned int ddr_sdram_mode_15;
27034e026f9SYork Sun unsigned int ddr_sdram_mode_16;
2715614e71bSYork Sun unsigned int ddr_sdram_md_cntl;
2725614e71bSYork Sun unsigned int ddr_sdram_interval;
2735614e71bSYork Sun unsigned int ddr_data_init;
2745614e71bSYork Sun unsigned int ddr_sdram_clk_cntl;
2755614e71bSYork Sun unsigned int ddr_init_addr;
2765614e71bSYork Sun unsigned int ddr_init_ext_addr;
2775614e71bSYork Sun unsigned int timing_cfg_4;
2785614e71bSYork Sun unsigned int timing_cfg_5;
27934e026f9SYork Sun unsigned int timing_cfg_6;
28034e026f9SYork Sun unsigned int timing_cfg_7;
28134e026f9SYork Sun unsigned int timing_cfg_8;
28234e026f9SYork Sun unsigned int timing_cfg_9;
2835614e71bSYork Sun unsigned int ddr_zq_cntl;
2845614e71bSYork Sun unsigned int ddr_wrlvl_cntl;
2855614e71bSYork Sun unsigned int ddr_wrlvl_cntl_2;
2865614e71bSYork Sun unsigned int ddr_wrlvl_cntl_3;
2875614e71bSYork Sun unsigned int ddr_sr_cntr;
2885614e71bSYork Sun unsigned int ddr_sdram_rcw_1;
2895614e71bSYork Sun unsigned int ddr_sdram_rcw_2;
29034e026f9SYork Sun unsigned int ddr_sdram_rcw_3;
29134e026f9SYork Sun unsigned int ddr_sdram_rcw_4;
29234e026f9SYork Sun unsigned int ddr_sdram_rcw_5;
29334e026f9SYork Sun unsigned int ddr_sdram_rcw_6;
29434e026f9SYork Sun unsigned int dq_map_0;
29534e026f9SYork Sun unsigned int dq_map_1;
29634e026f9SYork Sun unsigned int dq_map_2;
29734e026f9SYork Sun unsigned int dq_map_3;
2985614e71bSYork Sun unsigned int ddr_eor;
2995614e71bSYork Sun unsigned int ddr_cdr1;
3005614e71bSYork Sun unsigned int ddr_cdr2;
3015614e71bSYork Sun unsigned int err_disable;
3025614e71bSYork Sun unsigned int err_int_en;
303b406731aSYork Sun unsigned int debug[64];
3045614e71bSYork Sun } fsl_ddr_cfg_regs_t;
3055614e71bSYork Sun
3065614e71bSYork Sun typedef struct memctl_options_partial_s {
3075614e71bSYork Sun unsigned int all_dimms_ecc_capable;
3085614e71bSYork Sun unsigned int all_dimms_tckmax_ps;
3095614e71bSYork Sun unsigned int all_dimms_burst_lengths_bitmask;
3105614e71bSYork Sun unsigned int all_dimms_registered;
3115614e71bSYork Sun unsigned int all_dimms_unbuffered;
31234e026f9SYork Sun /* unsigned int lowest_common_spd_caslat; */
3135614e71bSYork Sun unsigned int all_dimms_minimum_trcd_ps;
3145614e71bSYork Sun } memctl_options_partial_t;
3155614e71bSYork Sun
3165614e71bSYork Sun #define DDR_DATA_BUS_WIDTH_64 0
3175614e71bSYork Sun #define DDR_DATA_BUS_WIDTH_32 1
3185614e71bSYork Sun #define DDR_DATA_BUS_WIDTH_16 2
319ef87cab6SYork Sun #define DDR_CSWL_CS0 0x04000001
3205614e71bSYork Sun /*
3215614e71bSYork Sun * Generalized parameters for memory controller configuration,
3225614e71bSYork Sun * might be a little specific to the FSL memory controller
3235614e71bSYork Sun */
3245614e71bSYork Sun typedef struct memctl_options_s {
3255614e71bSYork Sun /*
3265614e71bSYork Sun * Memory organization parameters
3275614e71bSYork Sun *
3285614e71bSYork Sun * if DIMM is present in the system
3295614e71bSYork Sun * where DIMMs are with respect to chip select
3305614e71bSYork Sun * where chip selects are with respect to memory boundaries
3315614e71bSYork Sun */
3325614e71bSYork Sun unsigned int registered_dimm_en; /* use registered DIMM support */
3335614e71bSYork Sun
3345614e71bSYork Sun /* Options local to a Chip Select */
3355614e71bSYork Sun struct cs_local_opts_s {
3365614e71bSYork Sun unsigned int auto_precharge;
3375614e71bSYork Sun unsigned int odt_rd_cfg;
3385614e71bSYork Sun unsigned int odt_wr_cfg;
3395614e71bSYork Sun unsigned int odt_rtt_norm;
3405614e71bSYork Sun unsigned int odt_rtt_wr;
3415614e71bSYork Sun } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];
3425614e71bSYork Sun
3435614e71bSYork Sun /* Special configurations for chip select */
3445614e71bSYork Sun unsigned int memctl_interleaving;
3455614e71bSYork Sun unsigned int memctl_interleaving_mode;
3465614e71bSYork Sun unsigned int ba_intlv_ctl;
3475614e71bSYork Sun unsigned int addr_hash;
3485614e71bSYork Sun
3495614e71bSYork Sun /* Operational mode parameters */
3505614e71bSYork Sun unsigned int ecc_mode; /* Use ECC? */
3515614e71bSYork Sun /* Initialize ECC using memory controller? */
3525614e71bSYork Sun unsigned int ecc_init_using_memctl;
3535614e71bSYork Sun unsigned int dqs_config; /* Use DQS? maybe only with DDR2? */
3545614e71bSYork Sun /* SREN - self-refresh during sleep */
3555614e71bSYork Sun unsigned int self_refresh_in_sleep;
356e368c206SJoakim Tjernlund /* SR_IE - Self-refresh interrupt enable */
357e368c206SJoakim Tjernlund unsigned int self_refresh_interrupt_en;
3585614e71bSYork Sun unsigned int dynamic_power; /* DYN_PWR */
3595614e71bSYork Sun /* memory data width to use (16-bit, 32-bit, 64-bit) */
3605614e71bSYork Sun unsigned int data_bus_width;
3615614e71bSYork Sun unsigned int burst_length; /* BL4, OTF and BL8 */
3625614e71bSYork Sun /* On-The-Fly Burst Chop enable */
3635614e71bSYork Sun unsigned int otf_burst_chop_en;
3645614e71bSYork Sun /* mirrior DIMMs for DDR3 */
3655614e71bSYork Sun unsigned int mirrored_dimm;
3665614e71bSYork Sun unsigned int quad_rank_present;
367eb118807SShengzhou Liu unsigned int ap_en; /* address parity enable for RDIMM/DDR4-UDIMM */
3685614e71bSYork Sun unsigned int x4_en; /* enable x4 devices */
369c0c32af0SYork Sun unsigned int package_3ds;
3705614e71bSYork Sun
3715614e71bSYork Sun /* Global Timing Parameters */
3725614e71bSYork Sun unsigned int cas_latency_override;
3735614e71bSYork Sun unsigned int cas_latency_override_value;
3745614e71bSYork Sun unsigned int use_derated_caslat;
3755614e71bSYork Sun unsigned int additive_latency_override;
3765614e71bSYork Sun unsigned int additive_latency_override_value;
3775614e71bSYork Sun
3785614e71bSYork Sun unsigned int clk_adjust; /* */
37902fb2761SShengzhou Liu unsigned int cpo_override; /* override timing_cfg_2[CPO]*/
38002fb2761SShengzhou Liu unsigned int cpo_sample; /* optimize debug_29[24:31] */
3815614e71bSYork Sun unsigned int write_data_delay; /* DQS adjust */
3825614e71bSYork Sun
383ef87cab6SYork Sun unsigned int cswl_override;
3845614e71bSYork Sun unsigned int wrlvl_override;
3855614e71bSYork Sun unsigned int wrlvl_sample; /* Write leveling */
3865614e71bSYork Sun unsigned int wrlvl_start;
3875614e71bSYork Sun unsigned int wrlvl_ctl_2;
3885614e71bSYork Sun unsigned int wrlvl_ctl_3;
3895614e71bSYork Sun
3905614e71bSYork Sun unsigned int half_strength_driver_enable;
3915614e71bSYork Sun unsigned int twot_en;
3925614e71bSYork Sun unsigned int threet_en;
3935614e71bSYork Sun unsigned int bstopre;
3945614e71bSYork Sun unsigned int tfaw_window_four_activates_ps; /* tFAW -- FOUR_ACT */
3955614e71bSYork Sun
3965614e71bSYork Sun /* Rtt impedance */
3975614e71bSYork Sun unsigned int rtt_override; /* rtt_override enable */
3985614e71bSYork Sun unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */
3995614e71bSYork Sun unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */
4005614e71bSYork Sun
4015614e71bSYork Sun /* Automatic self refresh */
4025614e71bSYork Sun unsigned int auto_self_refresh_en;
4035614e71bSYork Sun unsigned int sr_it;
4045614e71bSYork Sun /* ZQ calibration */
4055614e71bSYork Sun unsigned int zq_en;
4065614e71bSYork Sun /* Write leveling */
4075614e71bSYork Sun unsigned int wrlvl_en;
4085614e71bSYork Sun /* RCW override for RDIMM */
4095614e71bSYork Sun unsigned int rcw_override;
4105614e71bSYork Sun unsigned int rcw_1;
4115614e71bSYork Sun unsigned int rcw_2;
412426230a6SYork Sun unsigned int rcw_3;
4135614e71bSYork Sun /* control register 1 */
4145614e71bSYork Sun unsigned int ddr_cdr1;
4155614e71bSYork Sun unsigned int ddr_cdr2;
4165614e71bSYork Sun
4175614e71bSYork Sun unsigned int trwt_override;
4185614e71bSYork Sun unsigned int trwt; /* read-to-write turnaround */
4195614e71bSYork Sun } memctl_options_t;
4205614e71bSYork Sun
4211d71efbbSYork Sun phys_size_t fsl_ddr_sdram(void);
4221d71efbbSYork Sun phys_size_t fsl_ddr_sdram_size(void);
4231d71efbbSYork Sun phys_size_t fsl_other_ddr_sdram(unsigned long long base,
4241d71efbbSYork Sun unsigned int first_ctrl,
4251d71efbbSYork Sun unsigned int num_ctrls,
4261d71efbbSYork Sun unsigned int dimm_slots_per_ctrl,
4271d71efbbSYork Sun int (*board_need_reset)(void),
4281d71efbbSYork Sun void (*board_reset)(void),
4291d71efbbSYork Sun void (*board_de_reset)(void));
4305614e71bSYork Sun extern int fsl_use_spd(void);
4311d71efbbSYork Sun void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
4325614e71bSYork Sun unsigned int ctrl_num, int step);
4335614e71bSYork Sun u32 fsl_ddr_get_intl3r(void);
4341d71efbbSYork Sun void print_ddr_info(unsigned int start_ctrl);
4355614e71bSYork Sun
__board_assert_mem_reset(void)4365614e71bSYork Sun static void __board_assert_mem_reset(void)
4375614e71bSYork Sun {
4385614e71bSYork Sun }
4395614e71bSYork Sun
__board_deassert_mem_reset(void)4405614e71bSYork Sun static void __board_deassert_mem_reset(void)
4415614e71bSYork Sun {
4425614e71bSYork Sun }
4435614e71bSYork Sun
4445614e71bSYork Sun void board_assert_mem_reset(void)
4455614e71bSYork Sun __attribute__((weak, alias("__board_assert_mem_reset")));
4465614e71bSYork Sun
4475614e71bSYork Sun void board_deassert_mem_reset(void)
4485614e71bSYork Sun __attribute__((weak, alias("__board_deassert_mem_reset")));
4495614e71bSYork Sun
__board_need_mem_reset(void)4505614e71bSYork Sun static int __board_need_mem_reset(void)
4515614e71bSYork Sun {
4525614e71bSYork Sun return 0;
4535614e71bSYork Sun }
4545614e71bSYork Sun
4555614e71bSYork Sun int board_need_mem_reset(void)
4565614e71bSYork Sun __attribute__((weak, alias("__board_need_mem_reset")));
4575614e71bSYork Sun
458a7787b78STang Yuantian #if defined(CONFIG_DEEP_SLEEP)
459a7787b78STang Yuantian void board_mem_sleep_setup(void);
460a7787b78STang Yuantian bool is_warm_boot(void);
461a7787b78STang Yuantian int fsl_dp_resume(void);
462a7787b78STang Yuantian #endif
463aade2004STang Yuantian
4645614e71bSYork Sun /*
4655614e71bSYork Sun * The 85xx boards have a common prototype for fixed_sdram so put the
4665614e71bSYork Sun * declaration here.
4675614e71bSYork Sun */
4685614e71bSYork Sun #ifdef CONFIG_MPC85xx
4695614e71bSYork Sun extern phys_size_t fixed_sdram(void);
4705614e71bSYork Sun #endif
4715614e71bSYork Sun
4725614e71bSYork Sun #if defined(CONFIG_DDR_ECC)
4735614e71bSYork Sun extern void ddr_enable_ecc(unsigned int dram_size);
4745614e71bSYork Sun #endif
4755614e71bSYork Sun
4765614e71bSYork Sun
4775614e71bSYork Sun typedef struct fixed_ddr_parm{
4785614e71bSYork Sun int min_freq;
4795614e71bSYork Sun int max_freq;
4805614e71bSYork Sun fsl_ddr_cfg_regs_t *ddr_settings;
4815614e71bSYork Sun } fixed_ddr_parm_t;
4823eace37eSSimon Glass
4833eace37eSSimon Glass /**
4843eace37eSSimon Glass * fsl_initdram() - Set up the SDRAM
4853eace37eSSimon Glass *
4863eace37eSSimon Glass * @return 0 if OK, -ve on error
4873eace37eSSimon Glass */
4883eace37eSSimon Glass int fsl_initdram(void);
4893eace37eSSimon Glass
4905614e71bSYork Sun #endif
491