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Searched refs:timing (Results 1 – 25 of 197) sorted by relevance

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/openbmc/u-boot/drivers/video/
H A Datmel_lcdfb.c32 struct display_timing timing; member
114 static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix, in atmel_fb_init() argument
134 value = (timing->hactive.typ * timing->vactive.typ * in atmel_fb_init()
140 value = get_lcdc_clk_rate(0) / timing->pixelclock.typ; in atmel_fb_init()
141 if (get_lcdc_clk_rate(0) % timing->pixelclock.typ) in atmel_fb_init()
156 if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH)) in atmel_fb_init()
158 if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH)) in atmel_fb_init()
164 value = (timing->vsync_len.typ - 1) << ATMEL_LCDC_VPW_OFFSET; in atmel_fb_init()
165 value |= timing->vback_porch.typ << ATMEL_LCDC_VBP_OFFSET; in atmel_fb_init()
166 value |= timing->vfront_porch.typ; in atmel_fb_init()
[all …]
H A Datmel_hlcdfb.c254 struct display_timing timing; member
294 struct display_timing *timing = &priv->timing; in atmel_hlcdc_init() local
325 value = priv->clk_rate / timing->pixelclock.typ; in atmel_hlcdc_init()
326 if (priv->clk_rate % timing->pixelclock.typ) in atmel_hlcdc_init()
330 if (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) in atmel_hlcdc_init()
357 if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH)) in atmel_hlcdc_init()
359 if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH)) in atmel_hlcdc_init()
385 value = LCDC_LCDCFG1_VSPW(timing->vsync_len.typ - 1); in atmel_hlcdc_init()
386 value |= LCDC_LCDCFG1_HSPW(timing->hsync_len.typ - 1); in atmel_hlcdc_init()
389 value = LCDC_LCDCFG2_VBPW(timing->vback_porch.typ); in atmel_hlcdc_init()
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H A Ddisplay-uclass.c22 const struct display_timing *timing) in display_enable() argument
30 ret = ops->enable(dev, panel_bpp, timing); in display_enable()
40 int display_read_timing(struct udevice *dev, struct display_timing *timing) in display_read_timing() argument
48 return ops->read_timing(dev, timing); in display_read_timing()
56 return edid_get_timing(buf, ret, timing, &panel_bits_per_colour); in display_read_timing()
H A Dtda19988.c369 const struct display_timing *timing) in tda19988_enable() argument
372 u8 div = 148500000 / timing->pixelclock.typ, reg; in tda19988_enable()
388 line_clocks = timing->hsync_len.typ + timing->hback_porch.typ + in tda19988_enable()
389 timing->hactive.typ + timing->hfront_porch.typ; in tda19988_enable()
390 lines = timing->vsync_len.typ + timing->vback_porch.typ + in tda19988_enable()
391 timing->vactive.typ + timing->vfront_porch.typ; in tda19988_enable()
442 if (timing->flags & DISPLAY_FLAGS_HSYNC_LOW) in tda19988_enable()
444 if (timing->flags & DISPLAY_FLAGS_VSYNC_LOW) in tda19988_enable()
450 timing->hfront_porch.typ + 3); in tda19988_enable()
452 timing->vfront_porch.typ + 1); in tda19988_enable()
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H A Dihs_video_out.c237 struct display_timing timing; in ihs_video_out_probe() local
260 timing.hactive.typ = 1024; in ihs_video_out_probe()
261 timing.vactive.typ = 768; in ihs_video_out_probe()
266 timing.hactive.typ = 720; in ihs_video_out_probe()
267 timing.vactive.typ = 400; in ihs_video_out_probe()
272 timing.hactive.typ = 640; in ihs_video_out_probe()
273 timing.vactive.typ = 480; in ihs_video_out_probe()
324 res = display_enable(priv->video_tx, 8, &timing); in ihs_video_out_probe()
/openbmc/u-boot/drivers/video/tegra124/
H A Ddisplay.c25 static int tegra_dc_calc_refresh(const struct display_timing *timing) in tegra_dc_calc_refresh() argument
28 int pclk = timing->pixelclock.typ; in tegra_dc_calc_refresh()
30 h_total = timing->hactive.typ + timing->hfront_porch.typ + in tegra_dc_calc_refresh()
31 timing->hback_porch.typ + timing->hsync_len.typ; in tegra_dc_calc_refresh()
32 v_total = timing->vactive.typ + timing->vfront_porch.typ + in tegra_dc_calc_refresh()
33 timing->vback_porch.typ + timing->vsync_len.typ; in tegra_dc_calc_refresh()
43 static void print_mode(const struct display_timing *timing) in print_mode() argument
45 int refresh = tegra_dc_calc_refresh(timing); in print_mode()
48 timing->hactive.typ, timing->vactive.typ, refresh / 1000, in print_mode()
49 refresh % 1000, timing->pixelclock.typ); in print_mode()
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H A Ddp.c482 const struct display_timing *timing, in tegra_dc_dp_calc_config() argument
507 if (!link_rate || !link_cfg->lane_count || !timing->pixelclock.typ || in tegra_dc_dp_calc_config()
511 if ((u64)timing->pixelclock.typ * link_cfg->bits_per_pixel >= in tegra_dc_dp_calc_config()
515 num_linkclk_line = (u32)(lldiv(link_rate * timing->hactive.typ, in tegra_dc_dp_calc_config()
516 timing->pixelclock.typ)); in tegra_dc_dp_calc_config()
518 ratio_f = (u64)timing->pixelclock.typ * link_cfg->bits_per_pixel * f; in tegra_dc_dp_calc_config()
598 num_symbols_per_line = (timing->hactive.typ * in tegra_dc_dp_calc_config()
619 link_cfg->hblank_sym = (int)lldiv(((uint64_t)timing->hback_porch.typ + in tegra_dc_dp_calc_config()
620 timing->hfront_porch.typ + timing->hsync_len.typ - 7) * in tegra_dc_dp_calc_config()
621 link_rate, timing->pixelclock.typ) - in tegra_dc_dp_calc_config()
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/openbmc/u-boot/board/xilinx/zynqmp/
H A Dtap_delays.c84 static void arasan_zynqmp_tap_sdr104(u8 deviceid, u8 timing, u8 bank) in arasan_zynqmp_tap_sdr104() argument
105 static void arasan_zynqmp_tap_hs(u8 deviceid, u8 timing, u8 bank) in arasan_zynqmp_tap_hs() argument
117 if (timing == MMC_TIMING_MMC_HS) in arasan_zynqmp_tap_hs()
133 if (timing == MMC_TIMING_MMC_HS) in arasan_zynqmp_tap_hs()
142 static void arasan_zynqmp_tap_ddr50(u8 deviceid, u8 timing, u8 bank) in arasan_zynqmp_tap_ddr50() argument
150 if (timing == MMC_TIMING_UHS_DDR50) in arasan_zynqmp_tap_ddr50()
158 if (timing == MMC_TIMING_UHS_DDR50) in arasan_zynqmp_tap_ddr50()
170 if (timing == MMC_TIMING_UHS_DDR50) in arasan_zynqmp_tap_ddr50()
178 if (timing == MMC_TIMING_UHS_DDR50) in arasan_zynqmp_tap_ddr50()
187 static void arasan_zynqmp_tap_sdr50(u8 deviceid, u8 timing, u8 bank) in arasan_zynqmp_tap_sdr50() argument
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/openbmc/u-boot/common/
H A Dedid.c82 static void decode_timing(u8 *buf, struct display_timing *timing) in decode_timing() argument
90 set_entry(&timing->pixelclock, (buf[0] + (buf[1] << 8)) * 10000); in decode_timing()
104 set_entry(&timing->hactive, ha); in decode_timing()
105 set_entry(&timing->hfront_porch, hso); in decode_timing()
106 set_entry(&timing->hback_porch, hbl - hso - hspw); in decode_timing()
107 set_entry(&timing->hsync_len, hspw); in decode_timing()
109 set_entry(&timing->vactive, va); in decode_timing()
110 set_entry(&timing->vfront_porch, vso); in decode_timing()
111 set_entry(&timing->vback_porch, vbl - vso - vspw); in decode_timing()
112 set_entry(&timing->vsync_len, vspw); in decode_timing()
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/openbmc/u-boot/drivers/video/stm32/
H A Dstm32_ltdc.c22 struct display_timing timing; member
215 struct display_timing *timing = &priv->timing; in stm32_ltdc_set_mode() local
221 hsync = timing->hsync_len.typ - 1; in stm32_ltdc_set_mode()
222 vsync = timing->vsync_len.typ - 1; in stm32_ltdc_set_mode()
223 acc_hbp = hsync + timing->hback_porch.typ; in stm32_ltdc_set_mode()
224 acc_vbp = vsync + timing->vback_porch.typ; in stm32_ltdc_set_mode()
225 acc_act_w = acc_hbp + timing->hactive.typ; in stm32_ltdc_set_mode()
226 acc_act_h = acc_vbp + timing->vactive.typ; in stm32_ltdc_set_mode()
227 total_w = acc_act_w + timing->hfront_porch.typ; in stm32_ltdc_set_mode()
228 total_h = acc_act_h + timing->vfront_porch.typ; in stm32_ltdc_set_mode()
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/openbmc/u-boot/drivers/mmc/
H A Dxenon_sdhci.c123 u8 timing; member
141 if ((priv->timing == MMC_TIMING_UHS_SDR50) || in xenon_mmc_phy_init()
142 (priv->timing == MMC_TIMING_UHS_SDR25) || in xenon_mmc_phy_init()
143 (priv->timing == MMC_TIMING_UHS_SDR12) || in xenon_mmc_phy_init()
144 (priv->timing == MMC_TIMING_SD_HS) || in xenon_mmc_phy_init()
145 (priv->timing == MMC_TIMING_LEGACY)) in xenon_mmc_phy_init()
230 if ((priv->timing == MMC_TIMING_MMC_HS400) || in xenon_mmc_phy_set()
231 (priv->timing == MMC_TIMING_MMC_HS200) || in xenon_mmc_phy_set()
232 (priv->timing == MMC_TIMING_UHS_SDR50) || in xenon_mmc_phy_set()
233 (priv->timing == MMC_TIMING_UHS_SDR104) || in xenon_mmc_phy_set()
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/openbmc/u-boot/drivers/video/rockchip/
H A Drk_mipi.c29 struct display_timing *timing) in rk_mipi_read_timing() argument
34 0, timing); in rk_mipi_read_timing()
79 const struct display_timing *timing) in rk_mipi_dsi_enable() argument
91 rk_mipi_dsi_write(regs, VID_HSA_TIME, timing->hsync_len.typ); in rk_mipi_dsi_enable()
92 rk_mipi_dsi_write(regs, VID_HBP_TIME, timing->hback_porch.typ); in rk_mipi_dsi_enable()
93 rk_mipi_dsi_write(regs, VID_HLINE_TIME, (timing->hsync_len.typ in rk_mipi_dsi_enable()
94 + timing->hback_porch.typ + timing->hactive.typ in rk_mipi_dsi_enable()
95 + timing->hfront_porch.typ)); in rk_mipi_dsi_enable()
96 rk_mipi_dsi_write(regs, VID_VSA_LINES, timing->vsync_len.typ); in rk_mipi_dsi_enable()
97 rk_mipi_dsi_write(regs, VID_VBP_LINES, timing->vback_porch.typ); in rk_mipi_dsi_enable()
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/openbmc/openbmc/meta-openembedded/meta-oe/recipes-graphics/gtkperf/gtkperf/
H A D0002-timing.c-Fix-format-security-errors.patch4 Subject: [PATCH 2/2] timing.c: Fix format-security errors
10 src/timing.c | 6 +++---
13 diff --git a/src/timing.c b/src/timing.c
15 --- a/src/timing.c
16 +++ b/src/timing.c
/openbmc/u-boot/drivers/usb/host/
H A Dehci-tegra.c302 const unsigned *timing; in get_pll_timing() local
304 timing = controller->pll_parameter + in get_pll_timing()
307 return timing; in get_pll_timing()
350 const unsigned *timing; in init_utmi_usb_controller() local
387 timing = get_pll_timing(controller); in init_utmi_usb_controller()
392 timing[PARAM_STABLE_COUNT] << in init_utmi_usb_controller()
395 timing[PARAM_ACTIVE_DELAY_COUNT] << in init_utmi_usb_controller()
402 timing[PARAM_ENABLE_DELAY_COUNT] << in init_utmi_usb_controller()
405 timing[PARAM_XTAL_FREQ_COUNT] << in init_utmi_usb_controller()
413 timing[PARAM_STABLE_COUNT] << in init_utmi_usb_controller()
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/openbmc/u-boot/drivers/video/meson/
H A Dmeson_dw_hdmi.c161 struct display_timing timing; in meson_dw_hdmi_read_edid() local
174 edid_get_timing(buf, ret, &timing, &panel_bits_per_colour); in meson_dw_hdmi_read_edid()
178 timing.hactive.typ, timing.hfront_porch.typ, in meson_dw_hdmi_read_edid()
179 timing.hback_porch.typ, timing.hsync_len.typ, in meson_dw_hdmi_read_edid()
180 timing.vactive.typ, timing.vfront_porch.typ, in meson_dw_hdmi_read_edid()
181 timing.vback_porch.typ, timing.vsync_len.typ); in meson_dw_hdmi_read_edid()
183 if (timing.flags & DISPLAY_FLAGS_INTERLACED) in meson_dw_hdmi_read_edid()
185 if (timing.flags & DISPLAY_FLAGS_DOUBLESCAN) in meson_dw_hdmi_read_edid()
187 if (timing.flags & DISPLAY_FLAGS_DOUBLECLK) in meson_dw_hdmi_read_edid()
189 if (timing.flags & DISPLAY_FLAGS_HSYNC_LOW) in meson_dw_hdmi_read_edid()
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H A Dmeson_vpu.c35 struct display_timing timing; in meson_vpu_setup_mode() local
40 ret = display_read_timing(disp, &timing); in meson_vpu_setup_mode()
46 uc_priv->xsize = timing.hactive.typ; in meson_vpu_setup_mode()
47 uc_priv->ysize = timing.vactive.typ; in meson_vpu_setup_mode()
49 ret = display_enable(disp, 0, &timing); in meson_vpu_setup_mode()
56 timing.flags = DISPLAY_FLAGS_INTERLACED; in meson_vpu_setup_mode()
77 meson_vpu_setup_plane(dev, timing.flags & DISPLAY_FLAGS_INTERLACED); in meson_vpu_setup_mode()
78 meson_vpu_setup_venc(dev, &timing, is_cvbs); in meson_vpu_setup_mode()
79 meson_vpu_setup_vclk(dev, &timing, is_cvbs); in meson_vpu_setup_mode()
/openbmc/u-boot/drivers/ram/
H A Dstm32_sdram.c161 struct stm32_sdram_timing *timing; in stm32_sdram_init() local
174 timing = params->bank_params[i].sdram_timing; in stm32_sdram_init()
196 writel(timing->trcd << FMC_SDTR_TRCD_SHIFT in stm32_sdram_init()
197 | timing->trp << FMC_SDTR_TRP_SHIFT in stm32_sdram_init()
198 | timing->twr << FMC_SDTR_TWR_SHIFT in stm32_sdram_init()
199 | timing->trc << FMC_SDTR_TRC_SHIFT in stm32_sdram_init()
200 | timing->tras << FMC_SDTR_TRAS_SHIFT in stm32_sdram_init()
201 | timing->txsr << FMC_SDTR_TXSR_SHIFT in stm32_sdram_init()
202 | timing->tmrd << FMC_SDTR_TMRD_SHIFT, in stm32_sdram_init()
206 writel(timing->trcd << FMC_SDTR_TRCD_SHIFT in stm32_sdram_init()
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/openbmc/u-boot/include/
H A Ddisplay.h32 int display_read_timing(struct udevice *dev, struct display_timing *timing);
43 const struct display_timing *timing);
61 int (*read_timing)(struct udevice *dev, struct display_timing *timing);
82 const struct display_timing *timing);
/openbmc/u-boot/drivers/video/sunxi/
H A Dsunxi_lcd.c21 struct display_timing timing; member
69 struct display_timing *timing) in sunxi_lcd_read_timing() argument
73 memcpy(timing, &priv->timing, sizeof(struct display_timing)); in sunxi_lcd_read_timing()
100 &priv->timing, &channel_bpp); in sunxi_lcd_probe()
118 0, &priv->timing)) { in sunxi_lcd_probe()
H A Dsunxi_display.c219 (struct edid_detailed_timing *)edid1.monitor_details.timing; in sunxi_hdmi_edid_get_mode()
616 struct display_timing *timing) in sunxi_ctfb_mode_to_display_timing() argument
618 timing->pixelclock.typ = mode->pixclock_khz * 1000; in sunxi_ctfb_mode_to_display_timing()
620 timing->hactive.typ = mode->xres; in sunxi_ctfb_mode_to_display_timing()
621 timing->hfront_porch.typ = mode->right_margin; in sunxi_ctfb_mode_to_display_timing()
622 timing->hback_porch.typ = mode->left_margin; in sunxi_ctfb_mode_to_display_timing()
623 timing->hsync_len.typ = mode->hsync_len; in sunxi_ctfb_mode_to_display_timing()
625 timing->vactive.typ = mode->yres; in sunxi_ctfb_mode_to_display_timing()
626 timing->vfront_porch.typ = mode->lower_margin; in sunxi_ctfb_mode_to_display_timing()
627 timing->vback_porch.typ = mode->upper_margin; in sunxi_ctfb_mode_to_display_timing()
[all …]
/openbmc/u-boot/board/samsung/common/
H A Dboard.c190 err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing, in decode_sromc()
236 smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) | in board_eth_init()
237 SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) | in board_eth_init()
238 SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) | in board_eth_init()
239 SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) | in board_eth_init()
240 SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) | in board_eth_init()
241 SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) | in board_eth_init()
242 SROMC_BC_PMC(config.timing[FDT_SROM_PMC]); in board_eth_init()
/openbmc/u-boot/doc/device-tree-bindings/memory-controllers/
H A Dst,stm32-fmc.txt18 - st,sdram-timing: timings for sdram, in this order:
27 include/dt-bindings/memory/stm32-sdram.h to define sdram control and timing
47 st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
55 st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
/openbmc/u-boot/arch/arm/dts/
H A Dast2600a1-evb.dts11 timing-phase = <0x000700bf>;
15 timing-phase = <0x01084747>;
/openbmc/u-boot/doc/device-tree-bindings/video/
H A Ddisplay-timing.txt1 display-timing bindings
14 timing subnode
19 - hfront-porch, hback-porch, hsync-len: horizontal display timing parameters
21 vfront-porch, vback-porch, vsync-len: vertical display timing parameters in
99 timing1: timing {
/openbmc/openbmc/poky/meta/recipes-devtools/python/python3/
H A D0001-Skip-failing-tests-due-to-load-variability-on-YP-AB.patch33 + @unittest.skip('timing related test, dependent on load')
41 + @unittest.skip('timing related test, dependent on load')
49 + @unittest.skip('timing related test, dependent on load')
61 + @unittest.skip('timing related test, dependent on load')
69 + @unittest.skip('timing related test, dependent on load')

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