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Searched refs:timing (Results 1 – 25 of 829) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/tegra/
H A Dmipi-phy.c28 timing->eot = 0; in mipi_dphy_timing_get_default()
50 timing->taget = 5 * timing->lpx; in mipi_dphy_timing_get_default()
51 timing->tago = 4 * timing->lpx; in mipi_dphy_timing_get_default()
52 timing->tasure = 2 * timing->lpx; in mipi_dphy_timing_get_default()
74 if (timing->clkprepare < 38 || timing->clkprepare > 95) in mipi_dphy_timing_validate()
77 if (timing->clksettle < 95 || timing->clksettle > 300) in mipi_dphy_timing_validate()
86 if (timing->clkprepare + timing->clkzero < 300) in mipi_dphy_timing_validate()
102 if (timing->hsprepare + timing->hszero < 145 + 10 * period) in mipi_dphy_timing_validate()
121 if (timing->taget != 5 * timing->lpx) in mipi_dphy_timing_validate()
124 if (timing->tago != 4 * timing->lpx) in mipi_dphy_timing_validate()
[all …]
/openbmc/linux/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy.c138 timing->clk_trail, timing->clk_prepare, timing->hs_exit, in msm_dsi_dphy_timing_calc()
139 timing->hs_zero, timing->hs_prepare, timing->hs_trail, in msm_dsi_dphy_timing_calc()
252 timing->clk_trail, timing->clk_prepare, timing->hs_exit, in msm_dsi_dphy_timing_calc_v2()
253 timing->hs_zero, timing->hs_prepare, timing->hs_trail, in msm_dsi_dphy_timing_calc_v2()
254 timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en, in msm_dsi_dphy_timing_calc_v2()
362 timing->clk_trail, timing->clk_prepare, timing->hs_exit, in msm_dsi_dphy_timing_calc_v3()
363 timing->hs_zero, timing->hs_prepare, timing->hs_trail, in msm_dsi_dphy_timing_calc_v3()
364 timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en, in msm_dsi_dphy_timing_calc_v3()
463 timing->clk_zero, timing->clk_trail, timing->clk_prepare, timing->hs_exit, in msm_dsi_dphy_timing_calc_v4()
464 timing->hs_zero, timing->hs_prepare, timing->hs_trail, timing->hs_rqst); in msm_dsi_dphy_timing_calc_v4()
[all …]
H A Ddsi_phy_20nm.c11 struct msm_dsi_dphy_timing *timing) in dsi_20nm_dphy_set_timing() argument
16 DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); in dsi_20nm_dphy_set_timing()
21 if (timing->clk_zero & BIT(8)) in dsi_20nm_dphy_set_timing()
25 DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); in dsi_20nm_dphy_set_timing()
27 DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero)); in dsi_20nm_dphy_set_timing()
33 DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst)); in dsi_20nm_dphy_set_timing()
35 DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) | in dsi_20nm_dphy_set_timing()
38 DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get)); in dsi_20nm_dphy_set_timing()
70 struct msm_dsi_dphy_timing *timing = &phy->timing; in dsi_20nm_phy_enable() local
78 if (msm_dsi_dphy_timing_calc(timing, clk_req)) { in dsi_20nm_phy_enable()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_validation.c41 uint32_t pxl_clk = timing->pix_clk_100hz; in get_tmds_output_pixel_clock_100hz()
57 const struct dc_crtc_timing *timing, in dp_active_dongle_validate_timing() argument
77 switch (timing->pixel_encoding) { in dp_active_dongle_validate_timing()
94 switch (timing->display_color_depth) { in dp_active_dongle_validate_timing()
115 switch (timing->timing_3d_format) { in dp_active_dongle_validate_timing()
129 if (timing->flags.DSC && !timing->dsc_cfg.is_frl) in dp_active_dongle_validate_timing()
262 const struct dc_crtc_timing *timing) in dp_validate_mode_timing() argument
277 timing->h_addressable == (uint32_t) 640 && in dp_validate_mode_timing()
278 timing->v_addressable == (uint32_t) 480) in dp_validate_mode_timing()
314 const struct dc_crtc_timing *timing) in link_validate_mode_timing() argument
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/openbmc/linux/drivers/clk/tegra/
H A Dclk-tegra124-emc.c154 if (timing) { in emc_determine_rate()
222 timing->parent_rate, __clk_get_name(timing->parent)); in emc_set_timing()
225 clk_get_rate(timing->parent) != timing->parent_rate) { in emc_set_timing()
235 err = clk_set_rate(timing->parent, timing->parent_rate); in emc_set_timing()
238 __clk_get_name(timing->parent), timing->parent_rate, in emc_set_timing()
250 div = timing->parent_rate / (timing->rate / 2) - 2; in emc_set_timing()
304 return timing; in get_backup_timing()
315 return timing; in get_backup_timing()
350 if (!timing) { in emc_set_rate()
357 clk_get_rate(timing->parent) != timing->parent_rate) { in emc_set_rate()
[all …]
/openbmc/u-boot/drivers/video/
H A Datmel_lcdfb.c32 struct display_timing timing; member
134 value = (timing->hactive.typ * timing->vactive.typ * in atmel_fb_init()
166 value |= timing->vfront_porch.typ; in atmel_fb_init()
179 value |= timing->vactive.typ - 1; in atmel_fb_init()
211 struct display_timing timing; in lcd_ctrl_init() local
213 timing.flags = 0; in lcd_ctrl_init()
248 struct display_timing *timing = &priv->timing; in atmel_fb_lcd_probe() local
257 uc_priv->xsize = timing->hactive.typ; in atmel_fb_lcd_probe()
258 uc_priv->ysize = timing->vactive.typ; in atmel_fb_lcd_probe()
271 struct display_timing *timing = &priv->timing; in atmel_fb_ofdata_to_platdata() local
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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
H A Dtiming.c33 u32 timing = 0; in nvbios_timingTe() local
42 if (timing) { in nvbios_timingTe()
43 *ver = nvbios_rd08(bios, timing + 0); in nvbios_timingTe()
46 *hdr = nvbios_rd08(bios, timing + 1); in nvbios_timingTe()
47 *cnt = nvbios_rd08(bios, timing + 2); in nvbios_timingTe()
48 *len = nvbios_rd08(bios, timing + 3); in nvbios_timingTe()
51 return timing; in nvbios_timingTe()
53 *hdr = nvbios_rd08(bios, timing + 1); in nvbios_timingTe()
58 return timing; in nvbios_timingTe()
74 if (timing && idx < *cnt) { in nvbios_timingEe()
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/openbmc/u-boot/drivers/video/tegra124/
H A Ddisplay.c28 int pclk = timing->pixelclock.typ; in tegra_dc_calc_refresh()
30 h_total = timing->hactive.typ + timing->hfront_porch.typ + in tegra_dc_calc_refresh()
31 timing->hback_porch.typ + timing->hsync_len.typ; in tegra_dc_calc_refresh()
32 v_total = timing->vactive.typ + timing->vfront_porch.typ + in tegra_dc_calc_refresh()
33 timing->vback_porch.typ + timing->vsync_len.typ; in tegra_dc_calc_refresh()
48 timing->hactive.typ, timing->vactive.typ, refresh / 1000, in print_mode()
56 print_mode(timing); in update_display_mode()
63 writel(timing->vsync_len.typ << 16 | timing->hsync_len.typ, in update_display_mode()
72 writel(timing->hactive.typ | (timing->vactive.typ << 16), in update_display_mode()
233 writel(((timing->vactive.typ << 16) | timing->hactive.typ), in update_window()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_optc.c44 return optc1_is_two_pixels_per_containter(timing); in optc201_is_two_pixels_per_containter()
76 const struct dc_crtc_timing *timing) in optc201_validate_timing() argument
83 ASSERT(timing != NULL); in optc201_validate_timing()
85 v_blank = (timing->v_total - timing->v_addressable - in optc201_validate_timing()
86 timing->v_border_top - timing->v_border_bottom); in optc201_validate_timing()
88 h_blank = (timing->h_total - timing->h_addressable - in optc201_validate_timing()
89 timing->h_border_right - in optc201_validate_timing()
90 timing->h_border_left); in optc201_validate_timing()
105 if (timing->h_total > optc1->max_h_total || in optc201_validate_timing()
106 timing->v_total > optc1->max_v_total) in optc201_validate_timing()
[all …]
/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_encoder_phys_vid.c45 memset(timing, 0, sizeof(*timing)); in drm_mode_to_intf_timing_params()
74 timing->xres = timing->width; in drm_mode_to_intf_timing_params()
75 timing->yres = timing->height; in drm_mode_to_intf_timing_params()
96 timing->h_back_porch += timing->h_front_porch; in drm_mode_to_intf_timing_params()
98 timing->v_back_porch += timing->v_front_porch; in drm_mode_to_intf_timing_params()
110 timing->width = timing->width >> 1; in drm_mode_to_intf_timing_params()
111 timing->xres = timing->xres >> 1; in drm_mode_to_intf_timing_params()
112 timing->h_back_porch = timing->h_back_porch >> 1; in drm_mode_to_intf_timing_params()
122 timing->h_back_porch + timing->h_front_porch + in get_horizontal_total()
131 timing->v_back_porch + timing->v_front_porch + in get_vertical_total()
[all …]
/openbmc/linux/drivers/video/fbdev/via/
H A Dvia_modesetting.c22 raw.hor_total = timing->hor_total / 8 - 5; in via_set_primary_timing()
23 raw.hor_addr = timing->hor_addr / 8 - 1; in via_set_primary_timing()
27 raw.hor_sync_end = timing->hor_sync_end / 8; in via_set_primary_timing()
28 raw.ver_total = timing->ver_total - 2; in via_set_primary_timing()
29 raw.ver_addr = timing->ver_addr - 1; in via_set_primary_timing()
31 raw.ver_blank_end = timing->ver_blank_end - 1; in via_set_primary_timing()
33 raw.ver_sync_end = timing->ver_sync_end - 1; in via_set_primary_timing()
80 raw.hor_total = timing->hor_total - 1; in via_set_secondary_timing()
81 raw.hor_addr = timing->hor_addr - 1; in via_set_secondary_timing()
86 raw.ver_total = timing->ver_total - 1; in via_set_secondary_timing()
[all …]
/openbmc/linux/drivers/gpu/drm/sti/
H A Dsti_awg_utils.c122 struct awg_timing *timing) in awg_generate_line_signal() argument
127 if (timing->trailing_pixels > 0) { in awg_generate_line_signal()
129 val = timing->blanking_level; in awg_generate_line_signal()
137 val = timing->blanking_level; in awg_generate_line_signal()
143 val = timing->active_pixels - 1; in awg_generate_line_signal()
147 val = timing->blanking_level; in awg_generate_line_signal()
156 struct awg_timing *timing) in sti_awg_generate_code_data_enable_mode() argument
161 if (timing->trailing_lines > 0) { in sti_awg_generate_code_data_enable_mode()
163 val = timing->blanking_level; in sti_awg_generate_code_data_enable_mode()
182 if (timing->blanking_lines > 0) { in sti_awg_generate_code_data_enable_mode()
[all …]
/openbmc/linux/drivers/video/fbdev/
H A Dgbefb.c503 if (timing) { in compute_gbe_timing()
510 (timing->pll_n << timing->pll_p); in compute_gbe_timing()
515 timing->fields_sec = 1000 * timing->cfreq / timing->htotal * in compute_gbe_timing()
519 timing->hblank_end = timing->htotal; in compute_gbe_timing()
522 timing->vblank_end = timing->vtotal; in compute_gbe_timing()
581 temp = timing->vblank_start - timing->vblank_end - 1; in gbe_set_timing_info()
594 timing->htotal - (20 - timing->hblank_end)); in gbe_set_timing_info()
984 var->left_margin = timing.htotal - timing.hsync_end; in gbefb_check_var()
985 var->right_margin = timing.hsync_start - timing.width; in gbefb_check_var()
986 var->upper_margin = timing.vtotal - timing.vsync_end; in gbefb_check_var()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dsc/
H A Ddc_dsc.c63 if (!timing->flags.DSC) { in apply_128b_132b_stream_overhead()
94 if (timing->flags.DSC) in dc_bandwidth_in_kbps_from_timing()
96 timing->dsc_cfg.bits_per_pixel, in dc_bandwidth_in_kbps_from_timing()
97 timing->dsc_cfg.num_slices_h, in dc_bandwidth_in_kbps_from_timing()
98 timing->dsc_cfg.is_dp); in dc_bandwidth_in_kbps_from_timing()
125 kbps = timing->pix_clk_100hz / 10; in dc_bandwidth_in_kbps_from_timing()
128 if (timing->flags.Y_ONLY != 1) { in dc_bandwidth_in_kbps_from_timing()
865 pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right; in setup_dsc_config()
866 pic_height = timing->v_addressable + timing->v_border_top + timing->v_border_bottom; in setup_dsc_config()
1048 timing, in setup_dsc_config()
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramnv50.c143 timing[0], timing[1], timing[2], timing[3]); in nv50_ram_timing_calc()
145 timing[4], timing[5], timing[6], timing[7]); in nv50_ram_timing_calc()
389 ram_mask(hwsq, timing[3], 0xffffffff, timing[3]); in nv50_ram_calc()
390 ram_mask(hwsq, timing[1], 0xffffffff, timing[1]); in nv50_ram_calc()
391 ram_mask(hwsq, timing[6], 0xffffffff, timing[6]); in nv50_ram_calc()
392 ram_mask(hwsq, timing[7], 0xffffffff, timing[7]); in nv50_ram_calc()
393 ram_mask(hwsq, timing[8], 0xffffffff, timing[8]); in nv50_ram_calc()
394 ram_mask(hwsq, timing[0], 0xffffffff, timing[0]); in nv50_ram_calc()
395 ram_mask(hwsq, timing[2], 0xffffffff, timing[2]); in nv50_ram_calc()
396 ram_mask(hwsq, timing[4], 0xffffffff, timing[4]); in nv50_ram_calc()
[all …]
/openbmc/linux/drivers/media/i2c/
H A Dbt819.c60 struct timing { struct
70 static struct timing timing_data[] = { argument
175 struct timing *timing = &timing_data[(decoder->norm & V4L2_STD_525_60) ? 1 : 0]; in bt819_init() local
181 ((timing->hactive >> 8) & 0x03); in bt819_init()
186 init[0x08 * 2 - 1] = timing->hscale >> 8; in bt819_init()
238 struct timing *timing = NULL; in bt819_s_std() local
253 timing = &timing_data[1]; in bt819_s_std()
262 timing = &timing_data[0]; in bt819_s_std()
269 (((timing->vdelay >> 8) & 0x03) << 6) | in bt819_s_std()
271 (((timing->hdelay >> 8) & 0x03) << 2) | in bt819_s_std()
[all …]
/openbmc/linux/drivers/memory/tegra/
H A Dtegra124-emc.c587 if (!timing) { in tegra_emc_find_timing()
592 return timing; in tegra_emc_find_timing()
606 if (!timing) in tegra_emc_prepare_timing_change()
746 val = timing->emc_cfg_2; in tegra_emc_prepare_timing_change()
830 if (!timing) in tegra_emc_complete_timing_change()
875 emc->last_timing = *timing; in tegra_emc_complete_timing_change()
893 timing->emc_mode_1 = 0; in emc_read_current_timing()
894 timing->emc_mode_2 = 0; in emc_read_current_timing()
895 timing->emc_mode_4 = 0; in emc_read_current_timing()
934 timing->rate = value; in load_one_timing_from_dt()
[all …]
/openbmc/u-boot/board/xilinx/zynqmp/
H A Dtap_delays.c117 if (timing == MMC_TIMING_MMC_HS) in arasan_zynqmp_tap_hs()
133 if (timing == MMC_TIMING_MMC_HS) in arasan_zynqmp_tap_hs()
150 if (timing == MMC_TIMING_UHS_DDR50) in arasan_zynqmp_tap_ddr50()
158 if (timing == MMC_TIMING_UHS_DDR50) in arasan_zynqmp_tap_ddr50()
170 if (timing == MMC_TIMING_UHS_DDR50) in arasan_zynqmp_tap_ddr50()
178 if (timing == MMC_TIMING_UHS_DDR50) in arasan_zynqmp_tap_ddr50()
209 switch (timing) { in arasan_zynqmp_set_tapdelay()
211 arasan_zynqmp_tap_hs(deviceid, timing, bank); in arasan_zynqmp_set_tapdelay()
214 arasan_zynqmp_tap_sdr50(deviceid, timing, bank); in arasan_zynqmp_set_tapdelay()
218 arasan_zynqmp_tap_sdr104(deviceid, timing, bank); in arasan_zynqmp_set_tapdelay()
[all …]
/openbmc/u-boot/common/
H A Dedid.c104 set_entry(&timing->hactive, ha); in decode_timing()
105 set_entry(&timing->hfront_porch, hso); in decode_timing()
107 set_entry(&timing->hsync_len, hspw); in decode_timing()
109 set_entry(&timing->vactive, va); in decode_timing()
110 set_entry(&timing->vfront_porch, vso); in decode_timing()
112 set_entry(&timing->vsync_len, vspw); in decode_timing()
114 timing->flags = 0; in decode_timing()
130 timing->pixelclock.typ, in decode_timing()
195 decode_timing((u8 *)desc, timing); in edid_get_timing()
216 timing->hdmi_monitor = false; in edid_get_timing()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_timing_generator_v.c246 timing->v_front_porch; in dce110_timing_generator_v_program_blanking()
250 timing->h_front_porch; in dce110_timing_generator_v_program_blanking()
262 timing->h_total - 1, in dce110_timing_generator_v_program_blanking()
271 timing->v_total - 1, in dce110_timing_generator_v_program_blanking()
279 tmp = timing->h_total - in dce110_timing_generator_v_program_blanking()
289 timing->h_border_left + timing->h_border_right; in dce110_timing_generator_v_program_blanking()
302 tmp = timing->v_total - (v_sync_start + timing->v_border_top); in dce110_timing_generator_v_program_blanking()
310 tmp = tmp + timing->v_addressable + timing->v_border_top + in dce110_timing_generator_v_program_blanking()
325 timing->h_sync_width, in dce110_timing_generator_v_program_blanking()
351 timing->v_sync_width, in dce110_timing_generator_v_program_blanking()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_resource_helpers.c465 struct dc_crtc_timing *timing = NULL; in get_frame_rate_at_max_stretch_100hz() local
479 timing = &fpo_candidate_stream->timing; in get_frame_rate_at_max_stretch_100hz()
480 if (timing == NULL) in get_frame_rate_at_max_stretch_100hz()
485 sec_per_100_lines = timing->pix_clk_100hz / timing->h_total + 1; in get_frame_rate_at_max_stretch_100hz()
487 curr_v_blank = timing->v_total - timing->v_addressable; in get_frame_rate_at_max_stretch_100hz()
489 stretched_frame_pix_cnt = (v_stretch_max + timing->v_total) * timing->h_total; in get_frame_rate_at_max_stretch_100hz()
525 timing = &fpo_candidate_stream->timing; in get_refresh_rate()
526 if (timing == NULL) in get_refresh_rate()
529 h_v_total = timing->h_total * timing->v_total; in get_refresh_rate()
655 pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1); in dcn32_subvp_drr_admissable()
[all …]
/openbmc/u-boot/drivers/video/stm32/
H A Dstm32_ltdc.c22 struct display_timing timing; member
215 struct display_timing *timing = &priv->timing; in stm32_ltdc_set_mode() local
221 hsync = timing->hsync_len.typ - 1; in stm32_ltdc_set_mode()
222 vsync = timing->vsync_len.typ - 1; in stm32_ltdc_set_mode()
223 acc_hbp = hsync + timing->hback_porch.typ; in stm32_ltdc_set_mode()
224 acc_vbp = vsync + timing->vback_porch.typ; in stm32_ltdc_set_mode()
381 &priv->timing); in stm32_ltdc_probe()
396 priv->timing.pixelclock.typ, rate); in stm32_ltdc_probe()
403 priv->crop_w = priv->timing.hactive.typ; in stm32_ltdc_probe()
404 priv->crop_h = priv->timing.vactive.typ; in stm32_ltdc_probe()
[all …]
/openbmc/linux/drivers/ata/
H A Dpata_triflex.c76 u32 timing = 0; in triflex_load_timing() local
88 timing = 0x0103;break; in triflex_load_timing()
90 timing = 0x0203;break; in triflex_load_timing()
92 timing = 0x0808;break; in triflex_load_timing()
96 timing = 0x0F0F;break; in triflex_load_timing()
98 timing = 0x0202;break; in triflex_load_timing()
100 timing = 0x0204;break; in triflex_load_timing()
102 timing = 0x0404;break; in triflex_load_timing()
104 timing = 0x0508;break; in triflex_load_timing()
106 timing = 0x0808;break; in triflex_load_timing()
[all …]
/openbmc/u-boot/drivers/mmc/
H A Dxenon_sdhci.c123 u8 timing; member
145 (priv->timing == MMC_TIMING_LEGACY)) in xenon_mmc_phy_init()
344 priv->timing = MMC_TIMING_UHS_DDR50; in xenon_sdhci_set_ios_post()
346 priv->timing = MMC_TIMING_UHS_SDR25; in xenon_sdhci_set_ios_post()
348 priv->timing = MMC_TIMING_UHS_SDR50; in xenon_sdhci_set_ios_post()
351 priv->timing = MMC_TIMING_LEGACY; in xenon_sdhci_set_ios_post()
353 priv->timing = MMC_TIMING_SD_HS; in xenon_sdhci_set_ios_post()
358 priv->timing = MMC_TIMING_MMC_DDR52; in xenon_sdhci_set_ios_post()
360 priv->timing = MMC_TIMING_LEGACY; in xenon_sdhci_set_ios_post()
362 priv->timing = MMC_TIMING_MMC_HS; in xenon_sdhci_set_ios_post()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_stream.c106 memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg)); in dc_stream_construct()
107 stream->timing.dsc_cfg.num_slices_h = 0; in dc_stream_construct()
314 stream->timing.v_total * stream->timing.h_total - (uint64_t)1); in is_subvp_high_refresh_candidate()
370 ((stream->timing.pix_clk_100hz * 100) / stream->timing.v_total / stream->timing.h_total) < 120) in dc_stream_set_cursor_attributes()
373 ((stream->timing.pix_clk_100hz * 100) / stream->timing.v_total / stream->timing.h_total) < 120) in dc_stream_set_cursor_attributes()
762 stream->timing.pix_clk_100hz / 10, in dc_stream_log()
763 stream->timing.h_total, in dc_stream_log()
764 stream->timing.v_total, in dc_stream_log()
765 stream->timing.pixel_encoding, in dc_stream_log()
773 stream->timing.flags.DSC, in dc_stream_log()
[all …]

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