| /openbmc/u-boot/arch/arm/mach-sunxi/dram_timings/ |
| H A D | ddr2_v3s.c | 29 u8 tcksre = 5; in mctl_set_timing_params() local
66 writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) | in mctl_set_timing_params()
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| H A D | lpddr3_stock.c | 29 u8 tcksre = 5; in mctl_set_timing_params() local
65 writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) | in mctl_set_timing_params()
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| H A D | ddr3_1333.c | 29 u8 tcksre = 5; in mctl_set_timing_params() local
69 writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) | in mctl_set_timing_params()
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| /openbmc/u-boot/arch/arm/mach-imx/mx6/ |
| H A D | ddr.c | 998 u8 tcke, tcksrx, tcksre, trrd; in mx6_lpddr2_cfg() local
1050 tcksre = DIV_ROUND_UP(15000, clkper); in mx6_lpddr2_cfg()
1051 tcksrx = tcksre; in mx6_lpddr2_cfg()
1082 debug("tcksre=%d\n", tcksre); in mx6_lpddr2_cfg()
1204 (tcksre & 0x7); in mx6_lpddr2_cfg()
1228 u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd; in mx6_ddr3_cfg() local
1328 tcksre = DIV_ROUND_UP(max(5 * clkper, 10000), clkper); in mx6_ddr3_cfg()
1330 tcksrx = tcksre; in mx6_ddr3_cfg()
1349 debug("tcksre=%d\n", tcksre); in mx6_ddr3_cfg()
1505 (tcksre & 0x7); in mx6_ddr3_cfg()
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| /openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | sdram.h | 69 u32 tcksre; member
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| H A D | sdram_rk3036.h | 66 u32 tcksre; member
263 u32 tcksre; member
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| H A D | sdram_rk322x.h | 102 u32 tcksre; member
228 u32 tcksre; member
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| H A D | ddr_rk3368.h | 70 u32 tcksre; member
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| H A D | ddr_rk3288.h | 65 u32 tcksre; member
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| /openbmc/u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun8i_a33.c | 113 u8 tcksre = 5; in auto_set_timing_para() local
148 reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0); in auto_set_timing_para()
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| H A D | dram_sun8i_a83t.c | 113 u8 tcksre = 5; in auto_set_timing_para() local
180 reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0); in auto_set_timing_para()
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| H A D | dram_sun50i_h6.c | 214 u8 tcksre = 5; in mctl_set_timing_lpddr3() local
252 writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke, in mctl_set_timing_lpddr3()
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| H A D | dram_sun6i.c | 228 writel(MCTL_TCKSRE, &mctl_ctl->tcksre); in mctl_channel_init()
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| /openbmc/u-boot/arch/arm/include/asm/arch-sunxi/ |
| H A D | dram_sun6i.h | 93 u32 tcksre; /* 0x124 */ member
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| /openbmc/u-boot/drivers/ddr/fsl/ |
| H A D | ctrl_regs.c | 2000 unsigned int txpr, tcksre, tcksrx; in set_timing_cfg_7() local
2005 tcksre = max(5U, picos_to_mclk(ctrl_num, 10000)); in set_timing_cfg_7()
2026 if (tcksre <= 19) in set_timing_cfg_7()
2027 cksre = tcksre - 5; in set_timing_cfg_7()
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| /openbmc/linux/arch/mips/include/asm/octeon/ |
| H A D | cvmx-lmcx-defs.h | 2597 uint64_t tcksre:4; member
2617 uint64_t tcksre:4;
2626 uint64_t tcksre:4; member
2646 uint64_t tcksre:4;
2654 uint64_t tcksre:4; member
2674 uint64_t tcksre:4;
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| /openbmc/u-boot/doc/device-tree-bindings/clock/ |
| H A D | rockchip,rk3288-dmc.txt | 79 tcksre
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| /openbmc/u-boot/drivers/ram/rockchip/ |
| H A D | dmc-rk3368.c | 511 pctl_timing->tcksre = max(5u, ps_to_tCK(10000, freq)); in pctl_calc_timings()
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