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Searched refs:sysreg (Results 1 – 23 of 23) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Dsystem.c13 struct exynos5_sysreg *sysreg = in exynos5_set_usbhost_mode() local
18 setbits_le32(&sysreg->usb20phy_cfg, in exynos5_set_usbhost_mode()
21 clrbits_le32(&sysreg->usb20phy_cfg, in exynos5_set_usbhost_mode()
34 struct exynos4_sysreg *sysreg = in exynos4_set_system_display() local
43 cfg = readl(&sysreg->display_ctrl); in exynos4_set_system_display()
45 writel(cfg, &sysreg->display_ctrl); in exynos4_set_system_display()
50 struct exynos5_sysreg *sysreg = in exynos5_set_system_display() local
59 cfg = readl(&sysreg->disp1blk_cfg); in exynos5_set_system_display()
61 writel(cfg, &sysreg->disp1blk_cfg); in exynos5_set_system_display()
/openbmc/qemu/target/arm/hvf/
H A Dtrace-events1 … op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2) "unhandled sysreg read at pc=0x%"PRI…
2 … op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2) "unhandled sysreg write at pc=0x%"PR…
6 …, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2, uint64_t val) "sysreg read 0x%08x (op0=%…
7 …, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2, uint64_t val) "sysreg write 0x%08x (op0=…
H A Dhvf.c160 #define SYSREG_OP0(sysreg) ((sysreg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK) argument
163 #define SYSREG_OP1(sysreg) ((sysreg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK) argument
166 #define SYSREG_CRN(sysreg) ((sysreg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK) argument
169 #define SYSREG_CRM(sysreg) ((sysreg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK) argument
172 #define SYSREG_OP2(sysreg) ((sysreg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK) argument
/openbmc/qemu/hw/misc/
H A Dmchp_pfsoc_sysreg.c87 memory_region_init_io(&s->sysreg, OBJECT(dev), in mchp_pfsoc_sysreg_realize()
91 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sysreg); in mchp_pfsoc_sysreg_realize()
H A Dmeson.build148 system_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-sysreg.c'))
H A Dtrace-events126 # msf2-sysreg.c
127 msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) "msf2-sysreg write: addr 0x%08" PRI…
128 msf2_sysreg_read(uint64_t offset, uint32_t val) "msf2-sysreg read: addr 0x%08" PRIx64 " data 0x%08"…
/openbmc/qemu/include/hw/misc/
H A Dmchp_pfsoc_sysreg.h32 MemoryRegion sysreg; member
/openbmc/qemu/hw/arm/
H A Dmsf2-soc.c68 object_initialize_child(obj, "sysreg", &s->sysreg, TYPE_MSF2_SYSREG); in m2sxxx_soc_initfn()
173 dev = DEVICE(&s->sysreg); in m2sxxx_soc_realize()
176 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp)) { in m2sxxx_soc_realize()
/openbmc/qemu/include/hw/arm/
H A Dmsf2-soc.h63 MSF2SysregState sysreg; member
/openbmc/qemu/target/arm/
H A Dcpu-sysregs.h40 int get_sysreg_idx(ARMSysRegs sysreg);
H A Dkvm.c223 static uint64_t idregs_sysreg_to_kvm_reg(ARMSysRegs sysreg) in idregs_sysreg_to_kvm_reg() argument
225 return ARM64_SYS_REG((sysreg & CP_REG_ARM64_SYSREG_OP0_MASK) >> CP_REG_ARM64_SYSREG_OP0_SHIFT, in idregs_sysreg_to_kvm_reg()
226 (sysreg & CP_REG_ARM64_SYSREG_OP1_MASK) >> CP_REG_ARM64_SYSREG_OP1_SHIFT, in idregs_sysreg_to_kvm_reg()
227 (sysreg & CP_REG_ARM64_SYSREG_CRN_MASK) >> CP_REG_ARM64_SYSREG_CRN_SHIFT, in idregs_sysreg_to_kvm_reg()
228 (sysreg & CP_REG_ARM64_SYSREG_CRM_MASK) >> CP_REG_ARM64_SYSREG_CRM_SHIFT, in idregs_sysreg_to_kvm_reg()
229 (sysreg & CP_REG_ARM64_SYSREG_OP2_MASK) >> CP_REG_ARM64_SYSREG_OP2_SHIFT); in idregs_sysreg_to_kvm_reg()
H A Dcpu64.c51 int get_sysreg_idx(ARMSysRegs sysreg) in get_sysreg_idx() argument
53 switch (sysreg) { in get_sysreg_idx()
/openbmc/qemu/include/hw/xtensa/
H A Dxtensa-isa.h737 const char *xtensa_sysreg_name(xtensa_isa isa, xtensa_sysreg sysreg);
742 int xtensa_sysreg_number(xtensa_isa isa, xtensa_sysreg sysreg);
751 int xtensa_sysreg_is_user(xtensa_isa isa, xtensa_sysreg sysreg);
/openbmc/qemu/target/xtensa/
H A Dxtensa-isa.c266 isa->sysreg_lookup_table[n].u.sysreg = n; in xtensa_isa_init()
1562 return result->u.sysreg; in xtensa_sysreg_lookup_name()
1566 const char *xtensa_sysreg_name(xtensa_isa isa, xtensa_sysreg sysreg) in xtensa_sysreg_name() argument
1570 CHECK_SYSREG(intisa, sysreg, NULL); in xtensa_sysreg_name()
1571 return intisa->sysregs[sysreg].name; in xtensa_sysreg_name()
1575 int xtensa_sysreg_number(xtensa_isa isa, xtensa_sysreg sysreg) in xtensa_sysreg_number() argument
1579 CHECK_SYSREG(intisa, sysreg, XTENSA_UNDEFINED); in xtensa_sysreg_number()
1580 return intisa->sysregs[sysreg].number; in xtensa_sysreg_number()
1584 int xtensa_sysreg_is_user(xtensa_isa isa, xtensa_sysreg sysreg) in xtensa_sysreg_is_user() argument
1588 CHECK_SYSREG(intisa, sysreg, XTENSA_UNDEFINED); in xtensa_sysreg_is_user()
[all …]
H A Dxtensa-isa-internal.h161 xtensa_sysreg sysreg; /* Internal sysreg number. */ member
/openbmc/qemu/include/hw/riscv/
H A Dmicrochip_pfsoc.h54 MchpPfSoCSysregState sysreg; member
/openbmc/qemu/hw/riscv/
H A Dmicrochip_pfsoc.c174 object_initialize_child(obj, "sysreg", &s->sysreg, in microchip_pfsoc_soc_instance_init()
304 sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp); in microchip_pfsoc_soc_realize()
305 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0, in microchip_pfsoc_soc_realize()
307 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sysreg), 0, in microchip_pfsoc_soc_realize()
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Dcpu.h292 SAMSUNG_BASE(sysreg, SYSREG_BASE)
/openbmc/openbmc/poky/meta/recipes-kernel/linux/
H A Dkernel-devsrc.bb199 cp -a --parents arch/arm64/tools/gen-sysreg.awk $kerneldir/build/ 2>/dev/null || :
200 cp -a --parents arch/arm64/tools/sysreg $kerneldir/build/ 2>/dev/null || :
209 if [ -e $kerneldir/build/arch/arm64/tools/gen-sysreg.awk ]; then
210 … sed -i -e "s,#!.*awk.*,#!${USRBINPATH}/env awk," $kerneldir/build/arch/arm64/tools/gen-sysreg.awk
260 cp -a --parents arch/arm/tools/gen-sysreg.awk $kerneldir/build/ 2>/dev/null || :
/openbmc/qemu/target/arm/tcg/
H A Dm-nocp.decode37 # M-profile VLDR/VSTR to sysreg
/openbmc/u-boot/drivers/misc/
H A DKconfig68 a sysreg driver.
/openbmc/qemu/hw/intc/
H A Dtrace-events244 nvic_sysreg_read(uint64_t addr, uint32_t value, unsigned size) "NVIC sysreg read addr 0x%" PRIx64 "…
245 nvic_sysreg_write(uint64_t addr, uint32_t value, unsigned size) "NVIC sysreg write addr 0x%" PRIx64…
/openbmc/qemu/
H A DMAINTAINERS1173 F: hw/misc/msf2-sysreg.c
1177 F: include/hw/misc/msf2-sysreg.h