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Searched refs:status_bit (Results 1 – 9 of 9) sorted by relevance

/openbmc/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.h146 u32 status_bit; /* 0: gate is disabled; 0: gatge is enabled */ member
177 .status_bit = (_status_bit), \
189 .status_bit = (_status_bit), \
200 .status_bit = (_status_bit), \
211 .status_bit = (_status_bit), \
221 .status_bit = (_status_bit), \
H A Dclk-core.c138 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1); in peri_clk_enable()
150 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0); in peri_clk_enable()
348 if (!!(reg & (1 << cd->gate.status_bit)) == !!enable) in bus_clk_enable()
361 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, in bus_clk_enable()
/openbmc/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-core.h146 u32 status_bit; /* 0: gate is disabled; 0: gatge is enabled */ member
177 .status_bit = (_status_bit), \
189 .status_bit = (_status_bit), \
200 .status_bit = (_status_bit), \
211 .status_bit = (_status_bit), \
221 .status_bit = (_status_bit), \
H A Dclk-core.c138 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1); in peri_clk_enable()
150 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0); in peri_clk_enable()
348 if (!!(reg & (1 << cd->gate.status_bit)) == !!enable) in bus_clk_enable()
361 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, in bus_clk_enable()
/openbmc/u-boot/arch/arm/mach-snapdragon/
H A Dclock-snapdragon.c35 if (readl(base + gpll0->status) & gpll0->status_bit) in clk_enable_gpll0()
40 while ((readl(base + gpll0->status) & gpll0->status_bit) == 0) in clk_enable_gpll0()
H A Dclock-snapdragon.h16 int status_bit; member
H A Dclock-apq8096.c32 .status_bit = GPLL0_STATUS_ACTIVE,
H A Dclock-apq8016.c40 .status_bit = GPLL0_STATUS_ACTIVE,
/openbmc/u-boot/drivers/mmc/
H A Dsunxi_mmc.c309 const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY : in mmc_trans_data_by_cpu() local
326 while (readl(&priv->reg->status) & status_bit) { in mmc_trans_data_by_cpu()