| /openbmc/qemu/tests/tcg/xtensa/ |
| H A D | test_shift.S | 119 srl \dst, \src
126 srl \dst, \src
137 test srl
138 tests_shift srl, 0xa3c51249
140 tests_shift srl, 0x49a3c512
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| /openbmc/u-boot/arch/mips/lib/ |
| H A D | cache_init.S | 51 srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
59 srl \sz, $1, \off + MIPS_CONF1_DA_SHF - MIPS_CONF1_DA_SHF
67 srl $1, $1, \off + MIPS_CONF1_DS_SHF - MIPS_CONF1_DA_SHF
192 srl R_L2_LINE, t0, MIPS_CONF2_SL_SHF
198 srl t1, t0, MIPS_CONF2_SA_SHF
203 srl t1, t0, MIPS_CONF2_SS_SHF
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| /openbmc/u-boot/arch/mips/include/asm/ |
| H A D | asm.h | 277 #define INT_SRL srl
315 #define LONG_SRL srl
365 #define PTR_SRL srl
|
| /openbmc/qemu/tests/tcg/alpha/system/ |
| H A D | boot.S | 244 srl mask, 1, mask
248 srl divisor, 1, divisor
|
| /openbmc/qemu/tests/tcg/mips/include/ |
| H A D | wrappers_msa.h | 721 DO_MSA__WD__WS_WT(SRL_B, srl.b)
722 DO_MSA__WD__WS_WT(SRL_H, srl.h)
723 DO_MSA__WD__WS_WT(SRL_W, srl.w)
724 DO_MSA__WD__WS_WT(SRL_D, srl.d)
|
| /openbmc/qemu/tests/tcg/s390x/ |
| H A D | shift.c | 62 DEFINE_SHIFT_SINGLE_2(srl, 0x035);
|
| /openbmc/u-boot/arch/mips/mach-ath79/ar933x/ |
| H A D | lowlevel_init.S | 262 srl t1, t1, 3
|
| /openbmc/u-boot/board/imgtec/malta/ |
| H A D | lowlevel_init.S | 33 srl t0, t0, MALTA_REVISION_CORID_SHF
|
| /openbmc/u-boot/arch/mips/mach-mt7620/ |
| H A D | lowlevel_init.S | 195 srl t9, t9, 16
|
| /openbmc/qemu/target/microblaze/ |
| H A D | insns.decode | 246 srl 100100 ..... ..... 00000 000 0100 0001 @typea0
|
| /openbmc/qemu/target/openrisc/ |
| H A D | disas.c | 67 INSN(srl, "r%d, r%d, r%d", a->d, a->a, a->b)
|
| /openbmc/qemu/disas/ |
| H A D | microblaze.c | 105 …andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16, wic, wdc, wdcclear, wdcflush, … enumerator
337 …O_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000041, OPCODE_MASK_H34, srl, logical_inst },
|
| /openbmc/openbmc/poky/meta/recipes-connectivity/openssl/ |
| H A D | openssl_3.5.0.bb | 223 find apps test -name \*.srl -exec install -m644 -D {} ${D}${PTEST_PATH}/{} \;
|
| /openbmc/qemu/target/s390x/tcg/ |
| H A D | insn-data.h.inc | 828 C(0x8800, SRL, RS_a, Z, r1_32u, sh, new, r1_32, srl, 0)
829 C(0xebde, SRLK, RSY_a, DO, r3_32u, sh, new, r1_32, srl, 0)
830 C(0xeb0c, SRLG, RSY_a, Z, r3_o, sh, r1, 0, srl, 0)
838 C(0x8c00, SRDL, RS_a, Z, r1_D32, sh, new, r1_D32, srl, 0)
|
| /openbmc/qemu/target/riscv/ |
| H A D | insn32.decode | 165 srl 0000000 ..... ..... 101 ..... 0110011 @r
|
| /openbmc/qemu/target/xtensa/core-fsf/ |
| H A D | xtensa-modules.c.inc | 8034 { "srl", 68 /* xt_iclass_shiftt */,
8915 return 107; /* srl */
|
| /openbmc/qemu/tcg/loongarch64/ |
| H A D | tcg-insn-defs.c.inc | 1500 /* Emits the `srl.w d, j, k` instruction. */
1521 /* Emits the `srl.d d, j, k` instruction. */
|
| /openbmc/qemu/target/xtensa/core-dc232b/ |
| H A D | xtensa-modules.c.inc | 11080 { "srl", 70 /* xt_iclass_shiftt */,
12456 return 109; /* srl */
|
| /openbmc/qemu/target/xtensa/core-lx106/ |
| H A D | xtensa-modules.c.inc | 6073 { "srl", ICLASS_xt_iclass_shiftt,
|
| /openbmc/qemu/target/xtensa/core-sample_controller/ |
| H A D | xtensa-modules.c.inc | 8937 { "srl", ICLASS_xt_iclass_shiftt,
|
| /openbmc/qemu/target/xtensa/core-dc233c/ |
| H A D | xtensa-modules.c.inc | 11723 { "srl", ICLASS_xt_iclass_shiftt,
|
| /openbmc/qemu/target/xtensa/core-de212/ |
| H A D | xtensa-modules.c.inc | 11083 { "srl", ICLASS_xt_iclass_shiftt,
|
| /openbmc/qemu/target/xtensa/core-de233_fpu/ |
| H A D | xtensa-modules.c.inc | 16348 { "srl", ICLASS_xt_iclass_shiftt,
|
| /openbmc/qemu/target/mips/tcg/ |
| H A D | msa_helper.c | 5472 MSA_BINOP_IMMU_DF(srli, srl) in MSA_BINOP_IMMU_DF()
|
| /openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/ |
| H A D | xtensa-modules.c.inc | 27095 { "srl", ICLASS_xt_iclass_shiftt,
|