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Searched refs:sdmax_rlcx_rb_base (Results 1 – 18 of 18) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_arcturus.c178 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); in kgd_arcturus_hqd_sdma_load()
H A Damdgpu_amdkfd_gc_9_4_3.c113 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); in kgd_gfx_v9_4_3_hqd_sdma_load()
H A Damdgpu_amdkfd_gfx_v8.c302 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); in kgd_hqd_sdma_load()
H A Damdgpu_amdkfd_gfx_v10_3.c413 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); in hqd_sdma_load_v10_3()
H A Damdgpu_amdkfd_gfx_v11.c398 WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_BASE, m->sdmax_rlcx_rb_base); in hqd_sdma_load_v11()
H A Damdgpu_amdkfd_gfx_v10.c427 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); in kgd_hqd_sdma_load()
H A Damdgpu_amdkfd_gfx_v9.c440 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); in kgd_hqd_sdma_load()
H A Dsdma_v5_2.c794 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8); in sdma_v5_2_mqd_init()
H A Dsdma_v6_0.c829 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8); in sdma_v6_0_mqd_init()
H A Dsdma_v5_0.c946 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8); in sdma_v5_0_mqd_init()
/openbmc/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager_vi.c370 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
H A Dkfd_mqd_manager_v10.c374 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
H A Dkfd_mqd_manager_v11.c434 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
H A Dkfd_mqd_manager_v9.c469 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
/openbmc/linux/drivers/gpu/drm/amd/include/
H A Dvi_structs.h29 uint32_t sdmax_rlcx_rb_base; member
H A Dv9_structs.h29 uint32_t sdmax_rlcx_rb_base; member
H A Dv11_structs.h544 uint32_t sdmax_rlcx_rb_base; // offset: 1 (0x1) member
H A Dv10_structs.h545 uint32_t sdmax_rlcx_rb_base; member