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Searched refs:sdclk (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dcdns,sdhci.yaml92 cdns,phy-dll-delay-sdclk:
94 Value of the delay introduced on the sdclk output for all modes except
100 cdns,phy-dll-delay-sdclk-hsmmc:
102 Value of the delay introduced on the sdclk output for HS200, HS400 and
155 cdns,phy-dll-delay-sdclk = <0>;
H A Dmarvell,xenon-sdhci.yaml230 clocks = <&sdclk 0>, <&axi_clk 0>;
272 clocks = <&sdclk 0>;
/openbmc/u-boot/drivers/ram/
H A Dstm32_sdram.c114 u8 sdclk; member
178 writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT in stm32_sdram_init()
/openbmc/u-boot/arch/arm/dts/
H A Duniphier-ld11.dtsi442 cdns,phy-dll-delay-sdclk = <21>;
443 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
H A Duniphier-pxs3.dtsi362 cdns,phy-dll-delay-sdclk = <21>;
363 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
H A Duniphier-ld20.dtsi571 cdns,phy-dll-delay-sdclk = <21>;
572 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
/openbmc/u-boot/board/freescale/b4860qds/
H A Db4860qds.c1112 static int serdes_refclock(u8 sw, u8 sdclk) in serdes_refclock() argument
1118 if (sdclk == 1) { in serdes_refclock()
/openbmc/linux/arch/arm64/boot/dts/socionext/
H A Duniphier-ld11.dtsi462 cdns,phy-dll-delay-sdclk = <21>;
463 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
H A Duniphier-ld20.dtsi598 cdns,phy-dll-delay-sdclk = <21>;
599 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
H A Duniphier-pxs3.dtsi420 cdns,phy-dll-delay-sdclk = <21>;
421 cdns,phy-dll-delay-sdclk-hsmmc = <21>;