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Searched refs:rtsr (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/drivers/rtc/
H A Drtc-sa1100.c50 unsigned int rtsr; in sa1100_rtc_interrupt() local
55 rtsr = readl_relaxed(info->rtsr); in sa1100_rtc_interrupt()
57 writel_relaxed(0, info->rtsr); in sa1100_rtc_interrupt()
60 if (rtsr & (RTSR_ALE | RTSR_HZE)) { in sa1100_rtc_interrupt()
64 writel_relaxed((RTSR_AL | RTSR_HZ) & (rtsr >> 2), info->rtsr); in sa1100_rtc_interrupt()
73 writel_relaxed(RTSR_AL | RTSR_HZ, info->rtsr); in sa1100_rtc_interrupt()
77 if (rtsr & RTSR_AL) in sa1100_rtc_interrupt()
78 rtsr &= ~RTSR_ALE; in sa1100_rtc_interrupt()
79 writel_relaxed(rtsr & (RTSR_ALE | RTSR_HZE), info->rtsr); in sa1100_rtc_interrupt()
82 if (rtsr & RTSR_AL) in sa1100_rtc_interrupt()
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H A Drtc-pxa.c111 u32 rtsr; in rtsr_clear_bits() local
113 rtsr = rtc_readl(pxa_rtc, RTSR); in rtsr_clear_bits()
114 rtsr &= ~RTSR_TRIG_MASK; in rtsr_clear_bits()
115 rtsr &= ~mask; in rtsr_clear_bits()
116 rtc_writel(pxa_rtc, RTSR, rtsr); in rtsr_clear_bits()
121 u32 rtsr; in rtsr_set_bits() local
123 rtsr = rtc_readl(pxa_rtc, RTSR); in rtsr_set_bits()
124 rtsr &= ~RTSR_TRIG_MASK; in rtsr_set_bits()
125 rtsr |= mask; in rtsr_set_bits()
126 rtc_writel(pxa_rtc, RTSR, rtsr); in rtsr_set_bits()
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H A Drtc-at91rm9200.c379 unsigned int rtsr; in at91_rtc_interrupt() local
384 rtsr = at91_rtc_read(AT91_RTC_SR) & at91_rtc_read_imr(); in at91_rtc_interrupt()
385 if (rtsr) { /* this interrupt is shared! Is it ours? */ in at91_rtc_interrupt()
386 if (rtsr & AT91_RTC_ALARM) in at91_rtc_interrupt()
388 if (rtsr & AT91_RTC_SECEV) { in at91_rtc_interrupt()
392 if (rtsr & AT91_RTC_ACKUPD) in at91_rtc_interrupt()
395 at91_rtc_write(AT91_RTC_SCCR, rtsr); /* clear status reg */ in at91_rtc_interrupt()
H A Drtc-sa1100.h14 void __iomem *rtsr; member
/openbmc/qemu/hw/misc/
H A Dstm32l4x5_exti.c86 s->rtsr[bank] = 0x00000000; in stm32l4x5_exti_reset_hold()
123 if ((level && extract32(s->rtsr[bank], irq, 1)) || in stm32l4x5_exti_set_irq()
149 r = s->rtsr[bank]; in stm32l4x5_exti_read()
195 s->rtsr[bank] = val64 & configurable_mask(bank); in stm32l4x5_exti_write()
265 VMSTATE_UINT32_ARRAY(rtsr, Stm32l4x5ExtiState, EXTI_NUM_REGISTER),
/openbmc/linux/drivers/irqchip/
H A Dirq-stm32-exti.c332 unsigned int type, u32 *rtsr, u32 *ftsr) in stm32_exti_set_type() argument
338 *rtsr |= mask; in stm32_exti_set_type()
342 *rtsr &= ~mask; in stm32_exti_set_type()
346 *rtsr |= mask; in stm32_exti_set_type()
362 u32 rtsr, ftsr; in stm32_irq_set_type() local
375 rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst); in stm32_irq_set_type()
378 err = stm32_exti_set_type(d, type, &rtsr, &ftsr); in stm32_irq_set_type()
382 irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst); in stm32_irq_set_type()
566 u32 rtsr, ftsr; in stm32_exti_h_set_type() local
579 rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst); in stm32_exti_h_set_type()
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/openbmc/qemu/hw/arm/
H A Dstrongarm.c257 uint32_t rtsr; member
269 qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL); in strongarm_rtc_int_update()
270 qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ); in strongarm_rtc_int_update()
283 if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) { in strongarm_rtc_timer_update()
289 if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) { in strongarm_rtc_timer_update()
301 s->rtsr |= RTSR_AL; in strongarm_rtc_alarm_tick()
309 s->rtsr |= RTSR_HZ; in strongarm_rtc_hz_tick()
323 return s->rtsr; in strongarm_rtc_read()
352 old_rtsr = s->rtsr; in strongarm_rtc_write()
353 s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) | in strongarm_rtc_write()
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/openbmc/qemu/include/hw/misc/
H A Dstm32l4x5_exti.h43 uint32_t rtsr[EXTI_NUM_REGISTER]; member
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dimmap_85xx.h1148 u32 rtsr; member