257     uint32_t rtsr;  member
269     qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL);  in strongarm_rtc_int_update()
270     qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ);  in strongarm_rtc_int_update()
283     if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) {  in strongarm_rtc_timer_update()
289     if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) {  in strongarm_rtc_timer_update()
301     s->rtsr |= RTSR_AL;  in strongarm_rtc_alarm_tick()
309     s->rtsr |= RTSR_HZ;  in strongarm_rtc_hz_tick()
323         return s->rtsr;  in strongarm_rtc_read()
352         old_rtsr = s->rtsr;  in strongarm_rtc_write()
353         s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) |  in strongarm_rtc_write()
354                   (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ)));  in strongarm_rtc_write()
356         if (s->rtsr != old_rtsr) {  in strongarm_rtc_write()
394     s->rtsr = 0;  in strongarm_rtc_init()
443         VMSTATE_UINT32(rtsr, StrongARMRTCState),