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Searched refs:rs1 (Results 1 – 25 of 63) sorted by relevance

123

/openbmc/linux/arch/riscv/net/
H A Dbpf_jit.h229 static inline u32 rv_r_insn(u8 funct7, u8 rs2, u8 rs1, u8 funct3, u8 rd, in rv_r_insn() argument
232 return (funct7 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) | in rv_r_insn()
236 static inline u32 rv_i_insn(u16 imm11_0, u8 rs1, u8 funct3, u8 rd, u8 opcode) in rv_i_insn() argument
238 return (imm11_0 << 20) | (rs1 << 15) | (funct3 << 12) | (rd << 7) | in rv_i_insn()
242 static inline u32 rv_s_insn(u16 imm11_0, u8 rs2, u8 rs1, u8 funct3, u8 opcode) in rv_s_insn() argument
246 return (imm11_5 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) | in rv_s_insn()
250 static inline u32 rv_b_insn(u16 imm12_1, u8 rs2, u8 rs1, u8 funct3, u8 opcode) in rv_b_insn() argument
255 return (imm12 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) | in rv_b_insn()
274 static inline u32 rv_amo_insn(u8 funct5, u8 aq, u8 rl, u8 rs2, u8 rs1, in rv_amo_insn() argument
279 return rv_r_insn(funct7, rs2, rs1, funct3, rd, opcode); in rv_amo_insn()
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H A Dbpf_jit_comp32.c571 const s8 *rs1 = bpf_get_reg64(src1, tmp1, ctx); in emit_branch_r64() local
587 emit(rv_bne(hi(rs1), hi(rs2), NO_JUMP(1)), ctx); in emit_branch_r64()
588 emit(rv_bne(lo(rs1), lo(rs2), NO_JUMP(0)), ctx); in emit_branch_r64()
591 emit(rv_bgtu(hi(rs1), hi(rs2), JUMP(2)), ctx); in emit_branch_r64()
592 emit(rv_bltu(hi(rs1), hi(rs2), NO_JUMP(1)), ctx); in emit_branch_r64()
593 emit(rv_bleu(lo(rs1), lo(rs2), NO_JUMP(0)), ctx); in emit_branch_r64()
596 emit(rv_bltu(hi(rs1), hi(rs2), JUMP(2)), ctx); in emit_branch_r64()
597 emit(rv_bgtu(hi(rs1), hi(rs2), NO_JUMP(1)), ctx); in emit_branch_r64()
598 emit(rv_bgeu(lo(rs1), lo(rs2), NO_JUMP(0)), ctx); in emit_branch_r64()
601 emit(rv_bgtu(hi(rs1), hi(rs2), JUMP(2)), ctx); in emit_branch_r64()
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/openbmc/qemu/target/riscv/
H A Dfpu_helper.c121 static uint64_t do_fmadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2, in do_fmadd_h() argument
124 float16 frs1 = check_nanbox_h(env, rs1); in do_fmadd_h()
131 static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2, in do_fmadd_s() argument
134 float32 frs1 = check_nanbox_s(env, rs1); in do_fmadd_s()
218 uint64_t helper_fadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) in helper_fadd_s() argument
220 float32 frs1 = check_nanbox_s(env, rs1); in helper_fadd_s()
225 uint64_t helper_fsub_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) in helper_fsub_s() argument
227 float32 frs1 = check_nanbox_s(env, rs1); in helper_fsub_s()
232 uint64_t helper_fmul_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) in helper_fmul_s() argument
234 float32 frs1 = check_nanbox_s(env, rs1); in helper_fmul_s()
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H A Dcrypto_helper.c31 target_ulong rs1, target_ulong rs2, in aes32_operation() argument
52 res = rs1 ^ mixed; in aes32_operation()
57 target_ulong HELPER(aes32esmi)(target_ulong rs1, target_ulong rs2, in HELPER()
60 return aes32_operation(shamt, rs1, rs2, true, true); in HELPER()
63 target_ulong HELPER(aes32esi)(target_ulong rs1, target_ulong rs2, in HELPER()
66 return aes32_operation(shamt, rs1, rs2, true, false); in HELPER()
69 target_ulong HELPER(aes32dsmi)(target_ulong rs1, target_ulong rs2, in HELPER()
72 return aes32_operation(shamt, rs1, rs2, false, true); in HELPER()
75 target_ulong HELPER(aes32dsi)(target_ulong rs1, target_ulong rs2, in HELPER()
78 return aes32_operation(shamt, rs1, rs2, false, false); in HELPER()
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H A Dinsn16.decode56 &r rd rs1 rs2 !extern
57 &i imm rs1 rd !extern
58 &s imm rs1 rs2 !extern
60 &b imm rs2 rs1 !extern
62 &shift shamt rs1 rd !extern
63 &r2 rd rs1 !extern
64 &r2_s rs1 rs2 !extern
70 @cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd
71 @ci ... . ..... ..... .. &i imm=%imm_ci rs1=%rd %rd
72 @cl_q ... . ..... ..... .. &i imm=%uimm_cl_q rs1=%rs1_3 rd=%rs2_3
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H A Dbitmanip_helper.c27 target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2) in HELPER()
33 result ^= (rs1 << i); in HELPER()
40 target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2) in HELPER()
46 result ^= (rs1 >> (TARGET_LONG_BITS - i - 1)); in HELPER()
58 target_ulong HELPER(brev8)(target_ulong rs1) in HELPER()
60 target_ulong x = rs1; in HELPER()
84 target_ulong HELPER(unzip)(target_ulong rs1) in HELPER()
86 target_ulong x = rs1; in HELPER()
95 target_ulong HELPER(zip)(target_ulong rs1) in HELPER()
97 target_ulong x = rs1; in HELPER()
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H A Dxthead.decode16 %rs1 15:5
26 &r rd rs1 rs2 !extern
27 &r2 rd rs1 !extern
28 &shift shamt rs1 rd !extern
29 &th_bfext msb lsb rs1 rd
31 &th_memidx rd rs1 rs2 imm2
32 &th_meminc rd rs1 imm5 imm2
35 @sfence_vm ....... ..... ..... ... ..... ....... %rs1
36 @rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
37 @r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
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H A Dinsn32.decode22 %rs1 15:5
46 &b imm rs2 rs1
47 &i imm rs1 rd
49 &r rd rs1 rs2
50 &r2 rd rs1
51 &r2_s rs1 rs2
52 &s imm rs1 rs2
54 &shift shamt rs1 rd
55 &atomic aq rl rs2 rs1 rd
56 &rmrr vm rd rs1 rs2
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H A DXVentanaCondOps.decode14 %rs1 15:5
18 &r rd rs1 rs2 !extern
21 @r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
/openbmc/linux/arch/sparc/kernel/
H A Dvisemul.c140 static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2, in maybe_flush_windows() argument
143 if (rs2 >= 16 || rs1 >= 16 || rd >= 16) { in maybe_flush_windows()
296 unsigned long orig_rs1, rs1, orig_rs2, rs2, rd_val; in edge() local
300 orig_rs1 = rs1 = fetch_reg(RS1(insn), regs); in edge()
304 rs1 = rs1 & 0xffffffff; in edge()
311 left = edge8_tab[rs1 & 0x7].left; in edge()
316 left = edge8_tab_l[rs1 & 0x7].left; in edge()
322 left = edge16_tab[(rs1 >> 1) & 0x3].left; in edge()
328 left = edge16_tab_l[(rs1 >> 1) & 0x3].left; in edge()
334 left = edge32_tab[(rs1 >> 2) & 0x1].left; in edge()
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H A Dunaligned_32.c72 static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2, in maybe_flush_windows() argument
75 if(rs2 >= 16 || rs1 >= 16 || rd >= 16) { in maybe_flush_windows()
139 unsigned int rs1 = (insn >> 14) & 0x1f; in compute_effective_address() local
144 maybe_flush_windows(rs1, 0, rd); in compute_effective_address()
145 return (fetch_reg(rs1, regs) + sign_extend_imm13(insn)); in compute_effective_address()
147 maybe_flush_windows(rs1, rs2, rd); in compute_effective_address()
148 return (fetch_reg(rs1, regs) + fetch_reg(rs2, regs)); in compute_effective_address()
155 unsigned int rs1 = (insn >> 14) & 0x1f; in safe_compute_effective_address() local
160 maybe_flush_windows(rs1, 0, rd); in safe_compute_effective_address()
161 return (safe_fetch_reg(rs1, regs) + sign_extend_imm13(insn)); in safe_compute_effective_address()
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/openbmc/qemu/tests/tcg/tricore/asm/
H A Dmacros.h102 #define TEST_D_D(insn, num, result, rs1) \ argument
104 LI(DREG_RS1, rs1); \
108 #define TEST_D_D_PSW(insn, num, result, psw, rs1) \ argument
110 LI(DREG_RS1, rs1); \
115 #define TEST_D_DDD(insn, num, result, rs1, rs2, rs3) \ argument
117 LI(DREG_RS1, rs1); \
124 #define TEST_D_DD_PSW(insn, num, result, psw, rs1, rs2) \ argument
126 LI(DREG_RS1, rs1); \
132 #define TEST_D_DDD_PSW(insn, num, result, psw, rs1, rs2, rs3) \ argument
134 LI(DREG_RS1, rs1); \
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H A Dtest_insert.S5 # insn num result rs1 imm1 rs2 imm2
9 # insn num result rs1 imm1 imm2 imm3
14 # insn num result rs1 rs2 pos width
18 # insn num result rs1 imm1 rs2_h rs2_l
/openbmc/qemu/target/sparc/
H A Dinsns.decode17 BPr 00 a:1 0 cond:3 011 .. - rs1:5 .............. i=%d16
38 &r_r_ri rd rs1 rs2_or_imm imm:bool
39 @n_r_ri .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri rd=0
40 @r_r_ri .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri
42 &r_r_ri_cc rd rs1 rs2_or_imm imm:bool cc:bool
43 @r_r_ri_cc .. rd:5 . cc:1 .... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc
44 @r_r_ri_cc0 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=0
45 @r_r_ri_cc1 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=1
47 &r_r_r rd rs1 rs2
48 @r_r_r .. rd:5 ...... rs1:5 . ........ rs2:5 &r_r_r
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/openbmc/linux/arch/riscv/include/asm/
H A Dinsn-def.h25 .macro insn_r, opcode, func3, func7, rd, rs1, rs2
26 .insn r \opcode, \func3, \func7, \rd, \rs1, \rs2
29 .macro insn_i, opcode, func3, rd, rs1, simm12
30 .insn i \opcode, \func3, \rd, \rs1, \simm12
37 .macro insn_r, opcode, func3, func7, rd, rs1, rs2
42 (.L__gpr_num_\rs1 << INSN_R_RS1_SHIFT) | \
46 .macro insn_i, opcode, func3, rd, rs1, simm12
50 (.L__gpr_num_\rs1 << INSN_I_RS1_SHIFT) | \
63 #define __INSN_R(opcode, func3, func7, rd, rs1, rs2) \ argument
64 ".insn r " opcode ", " func3 ", " func7 ", " rd ", " rs1 ", " rs2 "\n"
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/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvzfh.c.inc52 t0 = get_gpr(ctx, a->rs1, EXT_NONE);
75 t0 = get_gpr(ctx, a->rs1, EXT_NONE);
93 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
110 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
127 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
144 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
161 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
177 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
193 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
209 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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H A Dtrans_rvd.c.inc65 addr = get_address(ctx, a->rs1, a->imm);
89 addr = get_address(ctx, a->rs1, a->imm);
110 REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3);
113 TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
128 REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3);
131 TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
146 REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3);
149 TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
164 REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3);
167 TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
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H A Dtrans_rvf.c.inc56 addr = get_address(ctx, a->rs1, a->imm);
78 addr = get_address(ctx, a->rs1, a->imm);
101 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
118 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
135 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
152 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
169 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
185 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
201 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
217 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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H A Dtrans_rvzfa.c.inc74 tcg_gen_movi_i64(dest, fli_s_table[a->rs1]);
123 tcg_gen_movi_i64(dest, fli_d_table[a->rs1]);
173 tcg_gen_movi_i64(dest, fli_h_table[a->rs1]);
187 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
204 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
221 TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
238 TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
255 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
272 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
289 TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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H A Dtrans_xthead.c.inc87 * If !zext_offs, then the address is rs1 + (rs2 << imm2).
88 * If zext_offs, then the address is rs1 + (zext(rs2[31:0]) << imm2).
90 static TCGv get_th_address_indexed(DisasContext *ctx, int rs1, int rs2,
103 return get_address_indexed(ctx, rs1, offs);
110 * alternative encoding: while sh[123] applies the shift to rs1,
162 TCGv source = get_gpr(ctx, a->rs1, EXT_ZERO);
187 TCGv src1 = get_gpr(ctx, a->rs1, ext);
314 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
325 /* th.mveqz: "if (rs2 == 0) rd = rs1;" */
332 /* th.mvnez: "if (rs2 != 0) rd = rs1;" */
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H A Dtrans_rvi.c.inc102 tcg_gen_addi_tl(target_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm);
123 * return from functions (i.e. rs1 == xRA || rs1 == xT0) are not
125 * branch are not tracked. rs1 == xT2 is a sw guarded branch.
127 if (a->rs1 != xRA && a->rs1 != xT0 && a->rs1 != xT2) {
219 TCGv src1 = get_gpr(ctx, a->rs1, EXT_SIGN);
224 TCGv src1h = get_gprh(ctx, a->rs1);
287 TCGv addr = get_address(ctx, a->rs1, a->imm);
297 TCGv src1l = get_gpr(ctx, a->rs1, EXT_NONE);
394 TCGv addr = get_address(ctx, a->rs1, a->imm);
407 TCGv src1l = get_gpr(ctx, a->rs1, EXT_NONE);
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H A Dtrans_rvzicbo.c.inc34 TCGv src = get_address(ctx, a->rs1, 0);
43 TCGv src = get_address(ctx, a->rs1, 0);
52 TCGv src = get_address(ctx, a->rs1, 0);
61 TCGv src = get_address(ctx, a->rs1, 0);
H A Dtrans_rvv.c.inc162 static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
172 if (rd == 0 && rs1 == 0) {
175 } else if (rs1 == 0) {
179 s1 = get_gpr(s, rs1, EXT_ZERO);
215 return do_vsetvl(s, a->rd, a->rs1, s2);
221 return do_vsetvl(s, a->rd, a->rs1, s2);
226 TCGv s1 = tcg_constant_tl(a->rs1);
625 static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
635 base = get_gpr(s, rs1, EXT_NONE);
707 return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
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/openbmc/u-boot/post/lib_powerpc/
H A Dcpu_asm.h142 #define ASM_12(opcode, rd, rs1, rs2) ((opcode) + \ argument
144 ((rs1) << 16) + \
150 #define ASM_12X(opcode, rd, rs1, rs2) ((opcode) + \ argument
151 ((rs1) << 21) + \
154 #define ASM_2C(opcode, cr, rs1, rs2) ((opcode) + \ argument
156 ((rs1) << 16) + \
162 #define ASM_122(opcode, rd, rs1, rs2, imm1, imm2) \ argument
164 ((rs1) << 21) + \
202 #define ASM_LSWX(rd, rs1, rs2) ASM_12(OP_LSWX, rd, rs1, rs2) argument
204 #define ASM_STSWX(rd, rs1, rs2) ASM_12(OP_STSWX, rd, rs1, rs2) argument
/openbmc/linux/arch/riscv/kernel/probes/
H A Dsimulate-insn.c227 u32 rs1 = (opcode >> 7) & 0x1f; in simulate_c_jr_jalr() local
229 if (rs1 == 0) /* C.JR is only valid when rs1 != x0 */ in simulate_c_jr_jalr()
232 if (!rv_insn_reg_get_val(regs, rs1, &jump_addr)) in simulate_c_jr_jalr()
263 u32 rs1; in simulate_c_bnez_beqz() local
266 rs1 = 0x8 | ((opcode >> 7) & 0x7); in simulate_c_bnez_beqz()
268 if (!rv_insn_reg_get_val(regs, rs1, &rs1_val)) in simulate_c_bnez_beqz()

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