Revision tags: v9.1.0 |
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#
5e54b439 |
| 02-Aug-2024 |
LIU Zhiwei <zhiwei_liu@linux.alibaba.com> |
target/riscv: Relax fld alignment requirement
According to the risc-v specification: "FLD and FSD are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN≥64.
target/riscv: Relax fld alignment requirement
According to the risc-v specification: "FLD and FSD are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN≥64."
We currently implement fld as MO_ATOM_IFALIGN when XLEN < 64, which does not violate the rules. But it will hide some problems. So relax it to MO_ATOM_NONE.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240802072417.659-4-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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30d24145 |
| 02-Aug-2024 |
LIU Zhiwei <zhiwei_liu@linux.alibaba.com> |
target/riscv: Add MXLEN check for F/D/Q applies to zama16b
Zama16b loads and stores of no more than MXLEN bits defined in the F, D, and Q extensions.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.ali
target/riscv: Add MXLEN check for F/D/Q applies to zama16b
Zama16b loads and stores of no more than MXLEN bits defined in the F, D, and Q extensions.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240802072417.659-3-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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b19bbf2c |
| 02-Aug-2024 |
LIU Zhiwei <zhiwei_liu@linux.alibaba.com> |
target/riscv: Remove redundant insn length check for zama16b
Compressed encodings also applies to zama16b. https://github.com/riscv/riscv-isa-manual/pull/1557
Suggested-by: Alistair Francis <alista
target/riscv: Remove redundant insn length check for zama16b
Compressed encodings also applies to zama16b. https://github.com/riscv/riscv-isa-manual/pull/1557
Suggested-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240802072417.659-2-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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#
a60ce58f |
| 09-Jul-2024 |
LIU Zhiwei <zhiwei_liu@linux.alibaba.com> |
target/riscv: Support Zama16b extension
Zama16b is the property that misaligned load/stores/atomics within a naturally aligned 16-byte region are atomic.
According to the specification, Zama16b app
target/riscv: Support Zama16b extension
Zama16b is the property that misaligned load/stores/atomics within a naturally aligned 16-byte region are atomic.
According to the specification, Zama16b applies only to AMOs, loads and stores defined in the base ISAs, and loads and stores of no more than XLEN bits defined in the F, D, and Q extensions. Thus it should not apply to zacas or RVC instructions.
For an instruction in that set, if all accessed bytes lie within 16B granule, the instruction will not raise an exception for reasons of address alignment, and the instruction will give rise to only one memory operation for the purposes of RVWMO—i.e., it will execute atomically.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240709113652.1239-6-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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ad75a51e |
| 13-Sep-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Rename cpu_env to tcg_env
Allow the name 'cpu_env' to be used for something else.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@li
tcg: Rename cpu_env to tcg_env
Allow the name 'cpu_env' to be used for something else.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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d33e39f9 |
| 17-May-2023 |
Weiwei Li <liweiwei@iscas.ac.cn> |
target/riscv: Update check for Zca/Zcf/Zcd
Even though Zca/Zcf/Zcd can be included by C/F/D, however, their priv version is higher than the priv version of C/F/D. So if we use check for them instead
target/riscv: Update check for Zca/Zcf/Zcd
Even though Zca/Zcf/Zcd can be included by C/F/D, however, their priv version is higher than the priv version of C/F/D. So if we use check for them instead of check for C/F/D totally, it will trigger new problem when we try to disable the extensions based on the configured priv version.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230517135714.211809-7-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Revision tags: v8.0.0 |
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#
c4935b58 |
| 07-Mar-2023 |
Weiwei Li <liweiwei@iscas.ac.cn> |
target/riscv: add support for Zcd extension
Separate c_fld/c_fsd from fld/fsd to add additional check for c.fld{sp}/c.fsd{sp} which is useful for zcmp/zcmt to reuse their encodings.
Signed-off-by:
target/riscv: add support for Zcd extension
Separate c_fld/c_fsd from fld/fsd to add additional check for c.fld{sp}/c.fsd{sp} which is useful for zcmp/zcmt to reuse their encodings.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307081403.61950-5-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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f4344296 |
| 25-Feb-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/riscv: Drop tcg_temp_free
Translators are no longer required to free tcg temporaries.
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicr
target/riscv: Drop tcg_temp_free
Translators are no longer required to free tcg temporaries.
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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f008a2d2 |
| 20-Jan-2023 |
Anup Patel <apatel@ventanamicro.com> |
target/riscv: Ensure opcode is saved for all relevant instructions
We should call decode_save_opc() for all relevant instructions which can potentially generate a virtual instruction fault or a gues
target/riscv: Ensure opcode is saved for all relevant instructions
We should call decode_save_opc() for all relevant instructions which can potentially generate a virtual instruction fault or a guest page fault because generating transformed instruction upon guest page fault expects opcode to be available. Without this, hypervisor will see transformed instruction as zero in htinst CSR for guest MMIO emulation which makes MMIO emulation in hypervisor slow and also breaks nested virtualization.
Fixes: a9814e3e08d2 ("target/riscv: Minimize the calls to decode_save_opc") Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230120125950.2246378-5-apatel@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Revision tags: v7.2.0, v7.0.0 |
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026e73fa |
| 10-Feb-2022 |
Weiwei Li <liweiwei@iscas.ac.cn> |
target/riscv: add support for zdinx
-- update extension check REQUIRE_ZDINX_OR_D -- update double float point register read/write
Co-authored-by: ardxwe <ardxwe@gmail.com> Signed-off-by: Weiwei
target/riscv: add support for zdinx
-- update extension check REQUIRE_ZDINX_OR_D -- update double float point register read/write
Co-authored-by: ardxwe <ardxwe@gmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220211043920.28981-5-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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4302bef9 |
| 20-Jan-2022 |
LIU Zhiwei <zhiwei_liu@c-sky.com> |
target/riscv: Calculate address according to XLEN
Define one common function to compute a canonical address from a register plus offset. Merge gen_pm_adjust_address into this function.
Signed-off-b
target/riscv: Calculate address according to XLEN
Define one common function to compute a canonical address from a register plus offset. Merge gen_pm_adjust_address into this function.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-14-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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fc313c64 |
| 06-Jan-2022 |
Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> |
exec/memop: Adding signedness to quad definitions
Renaming defines for quad in their various forms so that their signedness is now explicit. Done using git grep as suggested by Philippe, with a bit
exec/memop: Adding signedness to quad definitions
Renaming defines for quad in their various forms so that their signedness is now explicit. Done using git grep as suggested by Philippe, with a bit of hand edition to keep assignments aligned.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Revision tags: v6.2.0 |
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#
c655df7f |
| 25-Oct-2021 |
Alexey Baturo <baturo.alexey@gmail.com> |
target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@
target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211025173609.2724490-7-space.monkey.delivers@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Revision tags: v6.1.0 |
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#
7976837f |
| 23-Aug-2021 |
Richard Henderson <richard.henderson@linaro.org> |
target/riscv: Use {get,dest}_gpr for RVD
Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wd
target/riscv: Use {get,dest}_gpr for RVD
Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-23-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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#
867c8196 |
| 23-Aug-2021 |
Richard Henderson <richard.henderson@linaro.org> |
target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr
We will require the context to handle RV64 word operations.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng
target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr
We will require the context to handle RV64 word operations.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-5-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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#
a648df38 |
| 28-May-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging # gpg: Signature made Thu 27 May 2021 04:06:17 BST # gpg: using RSA key EF04965B398D6211
Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging # gpg: Signature made Thu 27 May 2021 04:06:17 BST # gpg: using RSA key EF04965B398D6211 # gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 215D 46F4 8246 689E C77F 3562 EF04 965B 398D 6211 * remotes/jasowang/tags/net-pull-request: tap-bsd: Remove special casing for older OpenBSD releases virtio-net: failover: add missing remove_migration_state_change_notifier() hw/net/imx_fec: return 0xffff when accessing non-existing PHY Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
6c769690 |
| 21-May-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/vsementsov/tags/pull-simplebench-2021-05-04' into staging scripts/simplebench improvements for 2021-05-04 # gpg: Signature made Tue 04 May 2021
Merge remote-tracking branch 'remotes/vsementsov/tags/pull-simplebench-2021-05-04' into staging scripts/simplebench improvements for 2021-05-04 # gpg: Signature made Tue 04 May 2021 09:45:15 BST # gpg: using RSA key 8B9C26CDB2FD147C880E86A1561F24C1F19F79FB # gpg: Good signature from "Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8B9C 26CD B2FD 147C 880E 86A1 561F 24C1 F19F 79FB * remotes/vsementsov/tags/pull-simplebench-2021-05-04: MAINTAINERS: update Benchmark util: add git tree simplebench/bench-backup: add --drop-caches argument simplebench/bench-backup: add --count and --no-initial-run simplebench/bench-backup: support qcow2 source files simplebench/bench_block_job: handle error in BLOCK_JOB_COMPLETED simplebench/bench-backup: add target-cache argument simplebench/bench-backup: add --compressed option simplebench: bench_one(): support count=1 simplebench: bench_one(): add slow_limit argument Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
da9076f3 |
| 21-May-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2021-05-11' into staging nbd patches for 2021-05-11 - fix fd passing to qemu-storage-daemon --nbd-server # gpg: Si
Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2021-05-11' into staging nbd patches for 2021-05-11 - fix fd passing to qemu-storage-daemon --nbd-server # gpg: Signature made Tue 11 May 2021 20:26:22 BST # gpg: using RSA key 71C2CC22B1C4602927D2F3AAA7A16B4A2527436A # gpg: Good signature from "Eric Blake <eblake@redhat.com>" [full] # gpg: aka "Eric Blake (Free Software Programmer) <ebb9@byu.net>" [full] # gpg: aka "[jpeg image of size 6874]" [full] # Primary key fingerprint: 71C2 CC22 B1C4 6029 27D2 F3AA A7A1 6B4A 2527 436A * remotes/ericb/tags/pull-nbd-2021-05-11: sockets: update SOCKET_ADDRESS_TYPE_FD listen(2) backlog Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
a1362f39 |
| 20-May-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/bsdimp/tags/pull-bsd-user-20210511' into staging pull-bsd-user-20210511 is the next round of cleanups to bsd-user in merging the bsd-user fork into
Merge remote-tracking branch 'remotes/bsdimp/tags/pull-bsd-user-20210511' into staging pull-bsd-user-20210511 is the next round of cleanups to bsd-user in merging the bsd-user fork into qemu. It contains a number of style commits, as well as 3 commits that start to change things: Some unused files are deleted, building the sparc and sparc64 targets are removed, and a structure is renamed. The next set of pull requests will start to execute the following plan: 1. Move existing code around to have a structure similar to the bsd-user fork. 2. Incrementally merge groups of system calls, focused on making x86 work. 3. Once the groups of system calls are all merged, additional platforms will be added back. 4. Concurrently, as changes are requested as part of the merge happen, those changes will be merged into the fork. An experimental merge to tip of master is under test and is what will be updated. 5. Eventually, there will be no diference, and the bsd-user fork will only be a staging area for cutting-edge features prior to upstreaming into qemu mainline. The bsd-user code in qemu has a lot of style issues. This cleans up a number in the files touched. However, the checkpatch.pl detects some incremental issues in the commits. The following are expected, but are corrected in later hashes in this branch. MAINTAINERS does not need to be updated, since all the files added or deleted are covered under existing regexp in MAINTAINERS. Checking all commits since f9a576a818044133f8564e0d243ebd97df0b3280... d60c3b932e2fa06aba5d7aa1c451b5d287095dc8:101: ERROR: consider using qemu_strtol in preference to strtol d60c3b932e2fa06aba5d7aa1c451b5d287095dc8:142: ERROR: braces {} are necessary for all arms of this statement d60c3b932e2fa06aba5d7aa1c451b5d287095dc8:145: ERROR: braces {} are necessary for all arms of this statement total: 3 errors, 0 warnings, 119 lines checked b4bebeee1dee8d333bfa105a6c28fec5eb34b147:148: WARNING: line over 80 characters b4bebeee1dee8d333bfa105a6c28fec5eb34b147:330: ERROR: braces {} are necessary for all arms of this statement b4bebeee1dee8d333bfa105a6c28fec5eb34b147:340: ERROR: braces {} are necessary for all arms of this statement b4bebeee1dee8d333bfa105a6c28fec5eb34b147:381: ERROR: space prohibited between function name and open parenthesis '(' b4bebeee1dee8d333bfa105a6c28fec5eb34b147:390: ERROR: spaces required around that '<' (ctx:VxV) b4bebeee1dee8d333bfa105a6c28fec5eb34b147:408: WARNING: Block comments use a leading /* on a separate line b4bebeee1dee8d333bfa105a6c28fec5eb34b147:409: WARNING: Block comments use * on subsequent lines b4bebeee1dee8d333bfa105a6c28fec5eb34b147:409: WARNING: Block comments use a trailing */ on a separate line b4bebeee1dee8d333bfa105a6c28fec5eb34b147:441: WARNING: line over 80 characters b4bebeee1dee8d333bfa105a6c28fec5eb34b147:445: WARNING: line over 80 characters b4bebeee1dee8d333bfa105a6c28fec5eb34b147:502: ERROR: line over 90 characters b4bebeee1dee8d333bfa105a6c28fec5eb34b147:551: ERROR: space required after that ',' (ctx:VxV) b4bebeee1dee8d333bfa105a6c28fec5eb34b147:552: ERROR: space required after that ',' (ctx:VxV) b4bebeee1dee8d333bfa105a6c28fec5eb34b147:587: ERROR: space required after that ';' (ctx:VxV) b4bebeee1dee8d333bfa105a6c28fec5eb34b147:623: ERROR: suspect code indent for conditional statements (12, 14) total: 9 errors, 6 warnings, 664 lines checked 86545e7afe3f822b8561c7ceee7540fc3b19c3f0:31: ERROR: space required after that ';' (ctx:VxV) 86545e7afe3f822b8561c7ceee7540fc3b19c3f0:40: ERROR: space required after that ';' (ctx:VxV) total: 2 errors, 0 warnings, 60 lines checked Use of uninitialized value $acpi_testexpected in string eq at scripts/checkpatch.pl line 1529. 65d58c91ef1a15ad945ece367983437576f8e82b:22: WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? total: 0 errors, 1 warnings, 14 lines checked Use of uninitialized value $acpi_testexpected in string eq at scripts/checkpatch.pl line 1529. f8ce39701b5be032fb3f9c05e8adb4055f70eec2:21: WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? total: 0 errors, 1 warnings, 0 lines checked FAIL one or more commits failed scripts/checkpatch.pl Cleaning up file based variables ERROR: Job failed: exit code 1 # gpg: Signature made Wed 12 May 2021 17:40:34 BST # gpg: using RSA key 2035F894B00AA3CF7CCDE1B76C1CD1287DB01100 # gpg: Good signature from "Warner Losh <wlosh@netflix.com>" [unknown] # gpg: aka "Warner Losh <imp@bsdimp.com>" [unknown] # gpg: aka "Warner Losh <imp@freebsd.org>" [unknown] # gpg: aka "Warner Losh <imp@village.org>" [unknown] # gpg: aka "Warner Losh <wlosh@bsdimp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 2035 F894 B00A A3CF 7CCD E1B7 6C1C D128 7DB0 1100 * remotes/bsdimp/tags/pull-bsd-user-20210511: bsd-user: rename linux_binprm to bsd_binprm bsd-user: Stop building the sparc targets bsd-user: remove target_signal.h, it's unused bsd-user: style tweak: keyword space ( bsd-user: style tweak: Remove #if 0'd code bsd-user: style tweak: keyword space ( bsd-user: style tweak: keyword space ( bsd-user: whitespace changes bsd-user: use qemu_strtoul in preference to strtol bsd-user: style tweak: use {} consistently in for / if / else statements bsd-user: style tweak: use {} for all if statements, format else correctly bsd-user: style tweak: don't assign in if statements bsd-user: style tweak: Use preferred block comments bsd-user: style tweak: remove spacing after '*' and add after } bsd-user: style tweak: move extern to header file bsd-user: Remove commented out code bsd-user: style tweak: Use preferred block comments bsd-user: style tweak: Remove #if 0'd code bsd-user: style tweak: use C not C++ comments bsd-user: whitespace changes Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
6005ee07 |
| 16-May-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging pc,pci,virtio: bugfixes, improvements Fixes all over the place. Faster boot for virtio. ioeventfd support f
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging pc,pci,virtio: bugfixes, improvements Fixes all over the place. Faster boot for virtio. ioeventfd support for mmio. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Fri 14 May 2021 15:27:13 BST # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: Fix build with 64 bits time_t vhost-vdpa: Make vhost_vdpa_get_device_id() static hw/virtio: enable ioeventfd configuring for mmio hw/smbios: support for type 41 (onboard devices extended information) checkpatch: Fix use of uninitialized value virtio-scsi: Configure all host notifiers in a single MR transaction virtio-scsi: Set host notifiers and callbacks separately virtio-blk: Configure all host notifiers in a single MR transaction virtio-blk: Fix rollback path in virtio_blk_data_plane_start() pc-dimm: remove unnecessary get_vmstate_memory_region() method amd_iommu: fix wrong MMIO operations virtio-net: Constify VirtIOFeature feature_sizes[] virtio-blk: Constify VirtIOFeature feature_sizes[] hw/virtio: Pass virtio_feature_get_config_size() a const argument x86: acpi: use offset instead of pointer when using build_header() amd_iommu: Fix pte_override_page_mask() Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # hw/arm/virt.c
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499063d0 |
| 14-May-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/cminyard/tags/for-qemu-6.1-v1' into staging Add a bus multiplexer device This patch set adds a bus multiplexer and the necessary infrastructure
Merge remote-tracking branch 'remotes/cminyard/tags/for-qemu-6.1-v1' into staging Add a bus multiplexer device This patch set adds a bus multiplexer and the necessary infrastructure in the I2C code to allow it to work. These are common on systems with lots of I2C devices, like an IPMI BMC. # gpg: Signature made Thu 13 May 2021 22:48:07 BST # gpg: using RSA key FD0D5CE67CE0F59A6688268661F38C90919BFF81 # gpg: Good signature from "Corey Minyard <cminyard@mvista.com>" [unknown] # gpg: aka "Corey Minyard <minyard@acm.org>" [unknown] # gpg: aka "Corey Minyard <corey@minyard.net>" [unknown] # gpg: aka "Corey Minyard <minyard@mvista.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: FD0D 5CE6 7CE0 F59A 6688 2686 61F3 8C90 919B FF81 * remotes/cminyard/tags/for-qemu-6.1-v1: hw/i2c: add pca954x i2c-mux switch hw/i2c: move search to i2c_scan_bus method hw/i2c: add match method for device search hw/i2c: name I2CNode list in I2CBus Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2d3fc4e2 |
| 13-May-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2021-05-12' into staging Miscellaneous patches for 2021-05-12 # gpg: Signature made Wed 12 May 2021 17:22:15 BST # gp
Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2021-05-12' into staging Miscellaneous patches for 2021-05-12 # gpg: Signature made Wed 12 May 2021 17:22:15 BST # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-misc-2021-05-12: Drop the deprecated unicore32 target Drop the deprecated lm32 target block: Drop the sheepdog block driver Remove the deprecated moxie target monitor/qmp: fix race on CHR_EVENT_CLOSED without OOB Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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dab59ce0 |
| 13-May-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/philmd/tags/pflash-20210511' into staging Parallel NOR Flash patches queue - Simplify memory layout when no pflash_cfi02 mapping requested
Merge remote-tracking branch 'remotes/philmd/tags/pflash-20210511' into staging Parallel NOR Flash patches queue - Simplify memory layout when no pflash_cfi02 mapping requested # gpg: Signature made Tue 11 May 2021 17:12:58 BST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd/tags/pflash-20210511: hw/block/pflash_cfi02: Do not create aliases when not necessary hw/block/pflash_cfi02: Set romd mode in pflash_cfi02_realize() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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3e9f48bc |
| 12-May-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210511' into staging A large collection of RISC-V fixes, improvements and features - Clenaup some left ove
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210511' into staging A large collection of RISC-V fixes, improvements and features - Clenaup some left over v1.9 code - Documentation improvements - Support for the shakti_c machine - Internal cleanup of the CSR accesses - Updates to the OpenTitan platform - Support for the virtio-vga - Fix for the saturate subtract in vector extensions - Experimental support for the ePMP spec - A range of other internal code cleanups and bug fixes # gpg: Signature made Tue 11 May 2021 11:17:10 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20210511: (42 commits) target/riscv: Fix the RV64H decode comment target/riscv: Consolidate RV32/64 16-bit instructions target/riscv: Consolidate RV32/64 32-bit instructions target/riscv: Remove an unused CASE_OP_32_64 macro target/riscv: Remove the unused HSTATUS_WPRI macro target/riscv: Remove the hardcoded SATP_MODE macro target/riscv: Remove the hardcoded MSTATUS_SD macro target/riscv: Remove the hardcoded HGATP_MODE macro target/riscv: Remove the hardcoded SSTATUS_SD macro target/riscv: Remove the hardcoded RVXLEN macro target/riscv: fix a typo with interrupt names fpu/softfloat: set invalid excp flag for RISC-V muladd instructions hw/riscv: Fix OT IBEX reset vector target/riscv: fix exception index on instruction access fault target/riscv: fix vrgather macro index variable type bug target/riscv: Add ePMP support for the Ibex CPU target/riscv/pmp: Remove outdated comment target/riscv: Add a config option for ePMP target/riscv: Implementation of enhanced PMP (ePMP) target/riscv: Add ePMP CSR access functions ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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daf866b6 |
| 23-Apr-2021 |
Alistair Francis <alistair.francis@wdc.com> |
target/riscv: Consolidate RV32/64 32-bit instructions This patch removes the insn32-64.decode decode file and consolidates the instructions into the general RISC-V insn32.decode decode t
target/riscv: Consolidate RV32/64 32-bit instructions This patch removes the insn32-64.decode decode file and consolidates the instructions into the general RISC-V insn32.decode decode tree. This means that all of the instructions are avaliable in both the 32-bit and 64-bit builds. This also means that we run a check to ensure we are running a 64-bit softmmu before we execute the 64-bit only instructions. This allows us to include the 32-bit instructions in the 64-bit build, while also ensuring that 32-bit only software can not execute the instructions. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: db709360e2be47d2f9c6483ab973fe4791aefa77.1619234854.git.alistair.francis@wdc.com
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