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Searched refs:reg_val (Results 1 – 25 of 43) sorted by relevance

12

/openbmc/u-boot/drivers/mtd/nand/raw/
H A Darasan_nfc.c266 u32 reg_val; in arasan_nand_select_chip() local
268 reg_val = readl(&arasan_nand_base->memadr_reg2); in arasan_nand_select_chip()
270 reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS0_MASK; in arasan_nand_select_chip()
271 writel(reg_val, &arasan_nand_base->memadr_reg2); in arasan_nand_select_chip()
273 reg_val |= ARASAN_NAND_MEM_ADDR2_CS1_MASK; in arasan_nand_select_chip()
274 writel(reg_val, &arasan_nand_base->memadr_reg2); in arasan_nand_select_chip()
280 u32 reg_val; in arasan_nand_enable_ecc() local
282 reg_val = readl(&arasan_nand_base->cmd_reg); in arasan_nand_enable_ecc()
283 reg_val |= ARASAN_NAND_CMD_ECC_ON_MASK; in arasan_nand_enable_ecc()
285 writel(reg_val, &arasan_nand_base->cmd_reg); in arasan_nand_enable_ecc()
[all …]
H A Dtegra_nand.c117 u32 reg_val; in nand_waitfor_cmd_completion() local
128 reg_val = readl(&reg->dma_mst_ctrl); in nand_waitfor_cmd_completion()
136 running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE | in nand_waitfor_cmd_completion()
138 if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE)) in nand_waitfor_cmd_completion()
207 int reg_val; in nand_dev_ready() local
212 reg_val = readl(&info->reg->status); in nand_dev_ready()
213 if (reg_val & STATUS_RBSY0) in nand_dev_ready()
239 u32 reg_val; in nand_clear_interrupt_status() local
242 reg_val = readl(&reg->isr); in nand_clear_interrupt_status()
243 writel(reg_val, &reg->isr); in nand_clear_interrupt_status()
[all …]
H A Dkmeter1_nand.c50 u8 reg_val = read_mode(); in kpn_nand_hwcontrol() local
53 reg_val = reg_val & ~(KPN_ALE + KPN_CLE); in kpn_nand_hwcontrol()
56 reg_val = reg_val | KPN_CLE; in kpn_nand_hwcontrol()
58 reg_val = reg_val | KPN_ALE; in kpn_nand_hwcontrol()
60 reg_val = reg_val & ~KPN_CE1N; in kpn_nand_hwcontrol()
62 reg_val = reg_val | KPN_CE1N; in kpn_nand_hwcontrol()
64 write_mode(reg_val); in kpn_nand_hwcontrol()
/openbmc/u-boot/drivers/video/tegra124/
H A Dsor.c62 u32 reg_val = tegra_sor_readl(sor, reg); in tegra_sor_write_field() local
63 reg_val &= ~mask; in tegra_sor_write_field()
64 reg_val |= val; in tegra_sor_write_field()
65 tegra_sor_writel(sor, reg, reg_val); in tegra_sor_write_field()
93 u32 reg_val = 0; in tegra_dc_sor_poll_register() local
98 reg_val = tegra_sor_readl(sor, reg); in tegra_dc_sor_poll_register()
99 if (((reg_val & mask) == exp_val)) in tegra_dc_sor_poll_register()
105 reg, reg_val, mask, exp_val); in tegra_dc_sor_poll_register()
113 u32 reg_val; in tegra_dc_sor_set_power_state() local
118 reg_val = pu_pd ? PWR_NORMAL_STATE_PU : in tegra_dc_sor_set_power_state()
[all …]
/openbmc/u-boot/arch/arm/mach-imx/mx7/
H A Dddr.c114 u32 reg_val, field_val; in imx_ddr_size() local
118 reg_val = readl(&ddrc_regs->mstr); in imx_ddr_size()
119 field_val = (reg_val & MSTR_DATA_BUS_WIDTH_MASK) >> MSTR_DATA_BUS_WIDTH_SHIFT; in imx_ddr_size()
122 field_val = (reg_val & MSTR_DATA_ACTIVE_RANKS_MASK) >> MSTR_DATA_ACTIVE_RANKS_SHIFT; in imx_ddr_size()
127 reg_val = readl(&ddrc_regs->addrmap2); in imx_ddr_size()
128 field_val = (reg_val & ADDRMAP2_COL_B2_MASK) >> ADDRMAP2_COL_B2_SHIFT; in imx_ddr_size()
131 field_val = (reg_val & ADDRMAP2_COL_B3_MASK) >> ADDRMAP2_COL_B3_SHIFT; in imx_ddr_size()
134 field_val = (reg_val & ADDRMAP2_COL_B4_MASK) >> ADDRMAP2_COL_B4_SHIFT; in imx_ddr_size()
137 field_val = (reg_val & ADDRMAP2_COL_B5_MASK) >> ADDRMAP2_COL_B5_SHIFT; in imx_ddr_size()
140 reg_val = readl(&ddrc_regs->addrmap3); in imx_ddr_size()
[all …]
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun4i.c66 u32 reg_val; in mctl_ddr3_reset() local
69 reg_val = readl(&timer->cpu_cfg); in mctl_ddr3_reset()
71 if ((reg_val & CPU_CFG_CHIP_VER_MASK) != in mctl_ddr3_reset()
239 u32 reg_val; in mctl_setup_dram_clock() local
246 reg_val = readl(&ccm->pll5_cfg); in mctl_setup_dram_clock()
247 reg_val &= ~CCM_PLL5_CTRL_M_MASK; /* set M to 0 (x1) */ in mctl_setup_dram_clock()
248 reg_val &= ~CCM_PLL5_CTRL_K_MASK; /* set K to 0 (x1) */ in mctl_setup_dram_clock()
249 reg_val &= ~CCM_PLL5_CTRL_N_MASK; /* set N to 0 (x0) */ in mctl_setup_dram_clock()
250 reg_val &= ~CCM_PLL5_CTRL_P_MASK; /* set P to 0 (x1) */ in mctl_setup_dram_clock()
253 reg_val |= CCM_PLL5_CTRL_P(1); in mctl_setup_dram_clock()
[all …]
H A Dcpu_info.c118 uint32_t reg_val; in sun8i_efuse_read() local
120 reg_val = readl(SUNXI_SIDC_BASE + SIDC_PRCTL); in sun8i_efuse_read()
121 reg_val &= ~(((0x1ff) << 16) | 0x3); in sun8i_efuse_read()
122 reg_val |= (offset << 16); in sun8i_efuse_read()
123 writel(reg_val, SUNXI_SIDC_BASE + SIDC_PRCTL); in sun8i_efuse_read()
125 reg_val &= ~(((0xff) << 8) | 0x3); in sun8i_efuse_read()
126 reg_val |= (SIDC_OP_LOCK << 8) | 0x2; in sun8i_efuse_read()
127 writel(reg_val, SUNXI_SIDC_BASE + SIDC_PRCTL); in sun8i_efuse_read()
131 reg_val &= ~(((0x1ff) << 16) | ((0xff) << 8) | 0x3); in sun8i_efuse_read()
132 writel(reg_val, SUNXI_SIDC_BASE + SIDC_PRCTL); in sun8i_efuse_read()
[all …]
H A Ddram_sun8i_a33.c90 u32 reg_val; in auto_set_timing_para() local
138 reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0); in auto_set_timing_para()
139 writel(reg_val, &mctl_ctl->dramtmg0); in auto_set_timing_para()
140 reg_val = (txp << 16) | (trtp << 8) | (trc << 0); in auto_set_timing_para()
141 writel(reg_val, &mctl_ctl->dramtmg1); in auto_set_timing_para()
142 reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0); in auto_set_timing_para()
143 writel(reg_val, &mctl_ctl->dramtmg2); in auto_set_timing_para()
144 reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0); in auto_set_timing_para()
145 writel(reg_val, &mctl_ctl->dramtmg3); in auto_set_timing_para()
146 reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0); in auto_set_timing_para()
[all …]
H A Ddram_sun8i_a83t.c90 u32 reg_val; in auto_set_timing_para() local
170 reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0); in auto_set_timing_para()
171 writel(reg_val, &mctl_ctl->dramtmg0); in auto_set_timing_para()
172 reg_val = (txp << 16) | (trtp << 8) | (trc << 0); in auto_set_timing_para()
173 writel(reg_val, &mctl_ctl->dramtmg1); in auto_set_timing_para()
174 reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0); in auto_set_timing_para()
175 writel(reg_val, &mctl_ctl->dramtmg2); in auto_set_timing_para()
176 reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0); in auto_set_timing_para()
177 writel(reg_val, &mctl_ctl->dramtmg3); in auto_set_timing_para()
178 reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0); in auto_set_timing_para()
[all …]
H A Ddram_sunxi_dw.c281 u32 reg_val; in mctl_h3_zq_calibration_quirk() local
289 reg_val = readl(&mctl_ctl->zqdr[0]); in mctl_h3_zq_calibration_quirk()
290 reg_val &= (0x1f << 16) | (0x1f << 0); in mctl_h3_zq_calibration_quirk()
291 reg_val |= reg_val << 8; in mctl_h3_zq_calibration_quirk()
292 writel(reg_val, &mctl_ctl->zqdr[0]); in mctl_h3_zq_calibration_quirk()
294 reg_val = readl(&mctl_ctl->zqdr[1]); in mctl_h3_zq_calibration_quirk()
295 reg_val &= (0x1f << 16) | (0x1f << 0); in mctl_h3_zq_calibration_quirk()
296 reg_val |= reg_val << 8; in mctl_h3_zq_calibration_quirk()
297 writel(reg_val, &mctl_ctl->zqdr[1]); in mctl_h3_zq_calibration_quirk()
298 writel(reg_val, &mctl_ctl->zqdr[2]); in mctl_h3_zq_calibration_quirk()
/openbmc/u-boot/drivers/usb/musb-new/
H A Dsunxi.c97 static u32 USBC_WakeUp_ClearChangeDetect(u32 reg_val) in USBC_WakeUp_ClearChangeDetect() argument
99 u32 temp = reg_val; in USBC_WakeUp_ClearChangeDetect()
110 u32 reg_val; in USBC_EnableIdPullUp() local
112 reg_val = musb_readl(base, USBC_REG_o_ISCR); in USBC_EnableIdPullUp()
113 reg_val |= BIT(USBC_BP_ISCR_ID_PULLUP_EN); in USBC_EnableIdPullUp()
114 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val); in USBC_EnableIdPullUp()
115 musb_writel(base, USBC_REG_o_ISCR, reg_val); in USBC_EnableIdPullUp()
120 u32 reg_val; in USBC_EnableDpDmPullUp() local
122 reg_val = musb_readl(base, USBC_REG_o_ISCR); in USBC_EnableDpDmPullUp()
123 reg_val |= BIT(USBC_BP_ISCR_DPDM_PULLUP_EN); in USBC_EnableDpDmPullUp()
[all …]
/openbmc/u-boot/include/
H A Dbitfield.h48 static inline uint bitfield_extract(uint reg_val, uint shift, uint width) in bitfield_extract() argument
50 return (reg_val & bitfield_mask(shift, width)) >> shift; in bitfield_extract()
57 static inline uint bitfield_replace(uint reg_val, uint shift, uint width, in bitfield_replace() argument
62 return (reg_val & ~mask) | ((bitfield_val << shift) & mask); in bitfield_replace()
72 static inline uint bitfield_extract_by_mask(uint reg_val, uint mask) in bitfield_extract_by_mask() argument
76 return (reg_val & mask) >> shift; in bitfield_extract_by_mask()
83 static inline uint bitfield_replace_by_mask(uint reg_val, uint mask, in bitfield_replace_by_mask() argument
88 return (reg_val & ~mask) | ((bitfield_val << shift) & mask); in bitfield_replace_by_mask()
/openbmc/u-boot/drivers/net/phy/
H A Dmscc.c287 u16 reg_val; in vsc8584_cmd() local
297 reg_val = bus->read(bus, phy, MDIO_DEVAD_NONE, in vsc8584_cmd()
300 (reg_val & PROC_CMD_NCOMPLETED) && in vsc8584_cmd()
301 !(reg_val & PROC_CMD_FAILED)); in vsc8584_cmd()
306 if (reg_val & PROC_CMD_FAILED) in vsc8584_cmd()
308 if (reg_val & PROC_CMD_NCOMPLETED) in vsc8584_cmd()
1010 u16 reg_val; in mscc_vsc8531_vsc8541_init_scripts() local
1020 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17); in mscc_vsc8531_vsc8541_init_scripts()
1021 reg_val = bitfield_replace(reg_val, MSCC_PHY_TR_LINKDETCTRL_POS, in mscc_vsc8531_vsc8541_init_scripts()
1025 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
[all …]
/openbmc/u-boot/drivers/mmc/
H A Daspeed_sdhci_ic.c46 u32 reg_val; in aspeed_sdhci_irq_probe() local
66 reg_val = readl(sdhci_ctrl_base + SDHCI140_SLOT_0_CAP_REG_1_OFFSET); in aspeed_sdhci_irq_probe()
68 reg_val |= BIT(26); in aspeed_sdhci_irq_probe()
69 writel(reg_val, sdhci_ctrl_base + SDHCI140_SLOT_0_MIRROR_OFFSET); in aspeed_sdhci_irq_probe()
70 reg_val = readl(sdhci_ctrl_base + SDHCI240_SLOT_0_CAP_REG_1_OFFSET); in aspeed_sdhci_irq_probe()
72 reg_val |= BIT(26); in aspeed_sdhci_irq_probe()
73 writel(reg_val, sdhci_ctrl_base + SDHCI240_SLOT_0_MIRROR_OFFSET); in aspeed_sdhci_irq_probe()
/openbmc/openbmc/meta-quanta/meta-gbs/recipes-gbs/gbs-sysinit/files/
H A Dgbs-sysinit.sh33 reg_val=$(devmem ${WD1RCR_ADDR} 32)
35 reg_val=$(printf "0x%08x" $((reg_val & ~0xff0000)))
36 echo "Setting WD1RCR_ADDR to ${reg_val}"
37 devmem "${WD1RCR_ADDR}" 32 "${reg_val}"
39 reg_val=$(devmem ${CORSTC_ADDR} 32)
41 reg_val=$(printf "0x%08x" $((reg_val & ~0xff0000)))
42 echo "Setting CORSTC_ADDR to ${reg_val}"
43 devmem "${CORSTC_ADDR}" 32 "${reg_val}"
/openbmc/u-boot/arch/arm/mach-omap2/
H A Dvc.c101 u32 reg_val; in omap_vc_bypass_send_value() local
108 reg_val = sa << PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT | in omap_vc_bypass_send_value()
111 writel(reg_val, (*prcm)->prm_vc_val_bypass); in omap_vc_bypass_send_value()
114 writel(reg_val | PRM_VC_VAL_BYPASS_VALID_BIT, in omap_vc_bypass_send_value()
119 reg_val = readl((*prcm)->prm_vc_val_bypass) & in omap_vc_bypass_send_value()
121 if (!reg_val) in omap_vc_bypass_send_value()
/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dmv_ddr_plat.c248 u32 reg_val = data; in dunit_write() local
251 dunit_read(addr, MASK_ALL_BITS, &reg_val); in dunit_write()
252 reg_val &= (~mask); in dunit_write()
253 reg_val |= (data & mask); in dunit_write()
256 reg_write(addr, reg_val); in dunit_write()
574 u32 reg_val; in is_prfa_done() local
582 dunit_read(PHY_REG_FILE_ACCESS_REG, MASK_ALL_BITS, &reg_val); in is_prfa_done()
583 reg_val >>= PRFA_REQ_OFFS; in is_prfa_done()
584 reg_val &= PRFA_REQ_MASK; in is_prfa_done()
585 } while (reg_val == PRFA_REQ_ENA); /* request pending */ in is_prfa_done()
[all …]
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/a38x/
H A Dsys_env_lib.h109 #define REF_CLK_SELECTOR_VAL_PEX0(reg_val) (reg_val >> 2) & 0x1 argument
110 #define REF_CLK_SELECTOR_VAL_PEX1(reg_val) (reg_val >> 3) & 0x1 argument
111 #define REF_CLK_SELECTOR_VAL_PEX2(reg_val) (reg_val >> 30) & 0x1 argument
112 #define REF_CLK_SELECTOR_VAL_PEX3(reg_val) (reg_val >> 31) & 0x1 argument
113 #define REF_CLK_SELECTOR_VAL(reg_val) (reg_val & 0x1) argument
/openbmc/u-boot/drivers/power/regulator/
H A Dsandbox.c82 uint8_t reg_val; in out_get_value() local
93 ret = pmic_read(dev->parent, reg, &reg_val, 1); in out_get_value()
101 reg_val); in out_get_value()
109 uint8_t reg_val; in out_set_value() local
127 reg_val = VAL2REG(range[dev->driver_data - 1].min, in out_set_value()
132 ret = pmic_write(dev->parent, reg, &reg_val, 1); in out_set_value()
144 uint8_t reg_val; in out_get_mode() local
152 ret = pmic_read(dev->parent, reg, &reg_val, 1); in out_get_mode()
159 if (reg_val == uc_pdata->mode[i].register_value) in out_get_mode()
170 int reg_val = -1; in out_set_mode() local
[all …]
/openbmc/u-boot/drivers/spi/
H A Daspeed_spi.c514 u32 reg_val; in aspeed_spi_timing_calibration() local
529 reg_val = flash->ce_ctrl_fread & CE_CTRL_FREQ_MASK; in aspeed_spi_timing_calibration()
530 writel(reg_val, &priv->regs->ce_ctrl[cs]); in aspeed_spi_timing_calibration()
597 reg_val = readl(&priv->regs->ce_ctrl[cs]); in aspeed_spi_timing_calibration()
598 reg_val = (reg_val & CE_CTRL_FREQ_MASK) | CE_G6_CTRL_CLOCK_FREQ(hclk_div); in aspeed_spi_timing_calibration()
599 writel(reg_val, &priv->regs->ce_ctrl[cs]); in aspeed_spi_timing_calibration()
1245 u32 reg_val; in aspeed_spi_fill_FQCD() local
1249 reg_val = readl(&priv->regs->fully_qualified_cmd[i]); in aspeed_spi_fill_FQCD()
1250 if ((u8)(reg_val & 0xff) == cmd || in aspeed_spi_fill_FQCD()
1251 (u8)((reg_val & 0xff00) >> 8) == cmd) { in aspeed_spi_fill_FQCD()
[all …]
/openbmc/u-boot/board/sunxi/
H A Dahci.c19 u32 reg_val; in sunxi_ahci_phy_init() local
42 reg_val = readl(reg_base + AHCI_PHYCS0R) & (0x7 << 28); in sunxi_ahci_phy_init()
43 if (reg_val == (0x2 << 28)) in sunxi_ahci_phy_init()
56 reg_val = readl(reg_base + AHCI_PHYCS2R) & (0x1 << 24); in sunxi_ahci_phy_init()
57 if (reg_val == 0x0) in sunxi_ahci_phy_init()
/openbmc/u-boot/arch/arm/mach-exynos/
H A Dlowlevel_init.c66 uint32_t val, reg_val; in low_power_start() local
68 reg_val = readl(EXYNOS5420_SPARE_BASE); in low_power_start()
69 if (reg_val != CPU_RST_FLAG_VAL) { in low_power_start()
74 reg_val = readl(CONFIG_PHY_IRAM_BASE + 0x4); in low_power_start()
75 if (reg_val != (uint32_t)&low_power_start) { in low_power_start()
/openbmc/u-boot/arch/arm/mach-zynq/
H A Dslcr.c127 u32 reg_val; in zynq_slcr_devcfg_disable() local
135 reg_val = readl(&slcr_base->lvl_shftr_en); in zynq_slcr_devcfg_disable()
136 reg_val &= ~0xF; in zynq_slcr_devcfg_disable()
137 writel(reg_val, &slcr_base->lvl_shftr_en); in zynq_slcr_devcfg_disable()
/openbmc/openbmc/meta-facebook/meta-catalina/recipes-phosphor/state/phosphor-state-manager/clemente/
H A Dpower-cmd28 local reg_val=""
30 if ! reg_val="$(i2ctransfer -y -f 14 w1@0x12 0x01 r1)"; then
40 if (( (reg_val & 0x02) == 0x02 )); then
/openbmc/u-boot/drivers/w1/
H A Dmxc_w1.c131 u16 reg_val; in mxc_w1_reset() local
136 reg_val = readw(&pdata->regs->control); in mxc_w1_reset()
137 } while (reg_val & MXC_W1_CONTROL_RPP); in mxc_w1_reset()
139 return !(reg_val & MXC_W1_CONTROL_PST); in mxc_w1_reset()

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