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Searched refs:reg_state (Results 1 – 8 of 8) sorted by relevance

/openbmc/qemu/hw/cxl/
H A Dcxl-component-utils.c211 static void ras_init_common(uint32_t *reg_state, uint32_t *write_msk) in ras_init_common() argument
217 stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_STATUS, 0); in ras_init_common()
220 stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff); in ras_init_common()
222 stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff); in ras_init_common()
224 stl_le_p(reg_state + R_CXL_RAS_COR_ERR_STATUS, 0); in ras_init_common()
226 stl_le_p(reg_state + R_CXL_RAS_COR_ERR_MASK, 0x7f); in ras_init_common()
229 stl_le_p(reg_state + R_CXL_RAS_ERR_CAP_CTRL, 0x200); in ras_init_common()
232 static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk, in hdm_init_common() argument
239 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, DECODER_COUNT, in hdm_init_common()
241 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 1); in hdm_init_common()
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H A Dcxl-device-utils.c114 static void mailbox_mem_writel(uint32_t *reg_state, hwaddr offset, in mailbox_mem_writel() argument
130 reg_state[offset / sizeof(*reg_state)] = value; in mailbox_mem_writel()
133 static void mailbox_mem_writeq(uint64_t *reg_state, hwaddr offset, in mailbox_mem_writeq() argument
152 reg_state[offset / sizeof(*reg_state)] = value; in mailbox_mem_writeq()
/openbmc/qemu/tests/tcg/i386/
H A Dtest-mmx.c28 } reg_state; typedef
34 reg_state *init;
37 reg_state initI;
38 reg_state initF32;
39 reg_state initF64;
64 static void dump_regs(reg_state *s, int ff) in dump_regs()
76 static void compare_state(const reg_state *a, const reg_state *b) in compare_state()
145 reg_state result; in run_test()
146 reg_state *init = t->init; in run_test()
266 static void init_all(reg_state *s) in init_all()
H A Dtest-avx.c21 } reg_state; typedef
27 reg_state *init;
30 reg_state initI;
31 reg_state initF16;
32 reg_state initF32;
33 reg_state initF64;
52 static void dump_regs(reg_state *s) in dump_regs()
64 static void compare_state(const reg_state *a, const reg_state *b) in compare_state()
141 reg_state result; in run_test()
142 reg_state *init = t->init; in run_test()
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/openbmc/qemu/hw/pci-bridge/
H A Dcxl_downstream.c38 uint32_t *reg_state = dsp->cxl_cstate.crb.cache_mem_registers; in latch_registers() local
41 cxl_component_register_init_common(reg_state, write_msk, in latch_registers()
H A Dcxl_upstream.c89 uint32_t *reg_state = usp->cxl_cstate.crb.cache_mem_registers; in latch_registers() local
92 cxl_component_register_init_common(reg_state, write_msk, in latch_registers()
94 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 8); in latch_registers()
H A Dcxl_root_port.c101 uint32_t *reg_state = crp->cxl_cstate.crb.cache_mem_registers; in latch_registers() local
104 cxl_component_register_init_common(reg_state, write_msk, CXL2_ROOT_PORT); in latch_registers()
/openbmc/qemu/include/hw/cxl/
H A Dcxl_component.h256 void cxl_component_register_init_common(uint32_t *reg_state,