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Searched refs:reg_set (Results 1 – 14 of 14) sorted by relevance

/openbmc/u-boot/drivers/phy/marvell/
H A Dcomphy_cp110.c114 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, in comphy_pcie_power_up()
118 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, in comphy_pcie_power_up()
130 reg_set((void __iomem *)DFX_DEV_GEN_CTRL12, in comphy_pcie_power_up()
147 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_pcie_power_up()
154 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_pcie_power_up()
172 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); in comphy_pcie_power_up()
182 reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask); in comphy_pcie_power_up()
198 reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask); in comphy_pcie_power_up()
200 reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG1_REG, in comphy_pcie_power_up()
204 reg_set(hpipe_addr + HPIPE_DFE_CTRL_28_REG, in comphy_pcie_power_up()
[all …]
H A Dcomphy_a3700.c205 reg_set(PCIE_REF_CLK_ADDR, 0x1342, 0xFFFFFFFF); in comphy_pcie_power_up()
265 reg_set(rh_vsreg_addr, reg, 0xFFFFFFFF); in reg_set_indirect()
266 reg_set(rh_vsreg_data, data, mask); in reg_set_indirect()
314 reg_set(rh_vs0_a, vsata_ctrl_reg, 0xFFFFFFFF); in comphy_sata_power_up()
315 reg_set(rh_vs0_d, bs_phy_pu_pll, bs_phy_pu_pll); in comphy_sata_power_up()
321 reg_set(rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF); in comphy_sata_power_up()
370 reg_set(USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0); in comphy_usb3_power_up()
376 reg_set(USB3_CTRPUL_VAL_REG, 0x8 << 24, rb_usb3_ctr_100ns); in comphy_usb3_power_up()
486 reg_set(rh_vsreg_addr, in comphy_usb3_power_up()
516 reg_set(USB32_CTRL_BASE, in comphy_usb3_power_up()
[all …]
H A Dcomphy_mux.c106 reg_set(selector_base, value, mask); in comphy_mux_reg_write()
H A Dcomphy_core.h106 static inline void reg_set(void __iomem *addr, u32 data, u32 mask) in reg_set() function
/openbmc/qemu/hw/intc/
H A Dexynos4210_combiner.c71 VMSTATE_UINT32_ARRAY(reg_set, Exynos4210CombinerState,
125 val = s->reg_set[offset >> 2]; in exynos4210_combiner_read()
201 s->reg_set[offset >> 2] = val; in exynos4210_combiner_write()
290 memset(&s->reg_set, 0, sizeof(s->reg_set)); in exynos4210_combiner_reset()
292 s->reg_set[0xC0 >> 2] = 0x01010101; in exynos4210_combiner_reset()
293 s->reg_set[0xC4 >> 2] = 0x01010101; in exynos4210_combiner_reset()
294 s->reg_set[0xD0 >> 2] = 0x01010101; in exynos4210_combiner_reset()
295 s->reg_set[0xD4 >> 2] = 0x01010101; in exynos4210_combiner_reset()
/openbmc/u-boot/arch/arm/cpu/arm926ejs/mxs/
H A Diomux.c62 writel(1 << bp, &mxs_reg->reg_set); in mxs_iomux_setup_pad()
74 writel(1 << bp, &mxs_reg->reg_set); in mxs_iomux_setup_pad()
/openbmc/u-boot/drivers/pinctrl/aspeed/
H A Dpinctrl-aspeed.h3 u32 reg_set; member
H A Dpinctrl_ast2500.c199 clrbits_le32((u32)ctrl_reg + descs->offset, descs->reg_set); in ast2500_pinctrl_group_set()
201 setbits_le32((u32)ctrl_reg + descs->offset, descs->reg_set); in ast2500_pinctrl_group_set()
H A Dpinctrl_ast2400.c204 clrbits_le32((u32)ctrl_reg + descs->offset, descs->reg_set); in ast2400_pinctrl_group_set()
206 setbits_le32((u32)ctrl_reg + descs->offset, descs->reg_set); in ast2400_pinctrl_group_set()
H A Dpinctrl_ast2600.c517 descs->reg_set); in ast2600_pinctrl_group_set()
520 descs->reg_set); in ast2600_pinctrl_group_set()
/openbmc/u-boot/drivers/gpio/
H A Dmxs_gpio.c72 writel(1 << PAD_PIN(gpio), &reg->reg_set); in gpio_set_value()
98 writel(1 << PAD_PIN(gpio), &reg->reg_set); in gpio_direction_output()
/openbmc/qemu/include/hw/intc/
H A Dexynos4210_combiner.h50 uint32_t reg_set[IIC_REGSET_SIZE]; member
/openbmc/u-boot/drivers/usb/host/
H A Dehci-mxs.c65 pll_offset = offsetof(struct mxs_register_32, reg_set); in ehci_mxs_toggle_clock()
71 dig_offset = offsetof(struct mxs_register_32, reg_set); in ehci_mxs_toggle_clock()
/openbmc/u-boot/arch/arm/mach-imx/
H A Dmisc.c56 writel(MXS_BLOCK_SFTRST, &reg->reg_set); in mxs_reset_block()