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Searched refs:reg_offset (Results 1 – 25 of 393) sorted by relevance

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/openbmc/linux/drivers/mfd/
H A Dsec-irq.c21 .reg_offset = 0,
25 .reg_offset = 0,
29 .reg_offset = 0,
33 .reg_offset = 0,
37 .reg_offset = 0,
41 .reg_offset = 0,
45 .reg_offset = 0,
49 .reg_offset = 0,
53 .reg_offset = 1,
57 .reg_offset = 1,
[all …]
H A Dda9052-irq.c37 .reg_offset = 0,
41 .reg_offset = 0,
45 .reg_offset = 0,
49 .reg_offset = 0,
53 .reg_offset = 0,
57 .reg_offset = 0,
61 .reg_offset = 0,
65 .reg_offset = 0,
69 .reg_offset = 1,
73 .reg_offset = 1,
[all …]
H A Dwm5110-tables.c328 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1
331 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1
334 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ6_EINT1
337 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ5_EINT1
340 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ4_EINT1
343 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ3_EINT1
346 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1
359 .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
362 .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1
519 .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
[all …]
H A Dtps65910.c54 .reg_offset = 0,
58 .reg_offset = 0,
62 .reg_offset = 0,
66 .reg_offset = 0,
70 .reg_offset = 0,
74 .reg_offset = 0,
78 .reg_offset = 0,
82 .reg_offset = 0,
88 .reg_offset = 1,
92 .reg_offset = 1,
[all …]
H A Dpalmas.c74 .reg_offset = 1,
78 .reg_offset = 1,
82 .reg_offset = 1,
86 .reg_offset = 1,
90 .reg_offset = 1,
94 .reg_offset = 1,
98 .reg_offset = 1,
102 .reg_offset = 1,
107 .reg_offset = 2,
111 .reg_offset = 2,
[all …]
H A Dcs47l24-tables.c46 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1
49 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1
52 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ6_EINT1
55 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ5_EINT1
58 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ4_EINT1
61 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ3_EINT1
64 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1
67 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1
77 .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1
98 .reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1
[all …]
H A Dmax8907.c115 { .reg_offset = 0, .mask = 1 << 0, },
116 { .reg_offset = 0, .mask = 1 << 1, },
117 { .reg_offset = 0, .mask = 1 << 2, },
118 { .reg_offset = 1, .mask = 1 << 0, },
119 { .reg_offset = 1, .mask = 1 << 1, },
120 { .reg_offset = 1, .mask = 1 << 2, },
121 { .reg_offset = 1, .mask = 1 << 3, },
122 { .reg_offset = 1, .mask = 1 << 4, },
123 { .reg_offset = 1, .mask = 1 << 5, },
124 { .reg_offset = 1, .mask = 1 << 6, },
[all …]
H A Dwm8994-irq.c28 .reg_offset = 1,
32 .reg_offset = 1,
36 .reg_offset = 1,
40 .reg_offset = 1,
44 .reg_offset = 1,
48 .reg_offset = 1,
52 .reg_offset = 1,
56 .reg_offset = 1,
60 .reg_offset = 1,
64 .reg_offset = 1,
[all …]
H A Das3722.c89 .reg_offset = 1,
93 .reg_offset = 1,
97 .reg_offset = 1,
101 .reg_offset = 1,
105 .reg_offset = 1,
109 .reg_offset = 1,
113 .reg_offset = 1,
117 .reg_offset = 1,
123 .reg_offset = 2,
127 .reg_offset = 2,
[all …]
H A Dmax14577.c193 { .reg_offset = 0, .mask = MAX14577_INT1_ADC_MASK, },
200 { .reg_offset = 1, .mask = MAX14577_INT2_DBCHG_MASK, },
203 { .reg_offset = 2, .mask = MAX14577_INT3_EOC_MASK, },
204 { .reg_offset = 2, .mask = MAX14577_INT3_CGMBC_MASK, },
205 { .reg_offset = 2, .mask = MAX14577_INT3_OVP_MASK, },
220 { .reg_offset = 0, .mask = MAX14577_INT1_ADC_MASK, },
223 { .reg_offset = 0, .mask = MAX77836_INT1_ADC1K_MASK, },
228 { .reg_offset = 1, .mask = MAX14577_INT2_DBCHG_MASK, },
230 { .reg_offset = 1, .mask = MAX77836_INT2_VIDRM_MASK, },
232 { .reg_offset = 2, .mask = MAX14577_INT3_EOC_MASK, },
[all …]
H A Drk8xx-core.c258 .reg_offset = 0,
262 .reg_offset = 0,
266 .reg_offset = 0,
270 .reg_offset = 0,
274 .reg_offset = 0,
278 .reg_offset = 0,
282 .reg_offset = 0,
286 .reg_offset = 0,
315 .reg_offset = 0,
319 .reg_offset = 0,
[all …]
H A Dwm8998-tables.c88 .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
91 .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1
94 .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1
100 .reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1
103 .reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1
112 .reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1
115 .reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1
128 .reg_offset = 3, .mask = ARIZONA_AIF3_ERR_EINT1
131 .reg_offset = 3, .mask = ARIZONA_AIF2_ERR_EINT1
134 .reg_offset = 3, .mask = ARIZONA_AIF1_ERR_EINT1
[all …]
H A Dwm5102-tables.c133 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1
136 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1
146 .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
149 .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1
152 .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1
173 .reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1
176 .reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1
189 .reg_offset = 3, .mask = ARIZONA_AIF3_ERR_EINT1
192 .reg_offset = 3, .mask = ARIZONA_AIF2_ERR_EINT1
195 .reg_offset = 3, .mask = ARIZONA_AIF1_ERR_EINT1
[all …]
H A Dwm8997-tables.c72 .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
75 .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1
78 .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1
87 .reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1
90 .reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1
93 .reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1
96 .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1
103 .reg_offset = 3, .mask = ARIZONA_AIF2_ERR_EINT1
106 .reg_offset = 3, .mask = ARIZONA_AIF1_ERR_EINT1
109 .reg_offset = 3, .mask = ARIZONA_CTRLIF_ERR_EINT1
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Darct_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in arct_reg_base_init()
35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in arct_reg_base_init()
36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in arct_reg_base_init()
38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i])); in arct_reg_base_init()
39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in arct_reg_base_init()
40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in arct_reg_base_init()
41 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in arct_reg_base_init()
42 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in arct_reg_base_init()
53 adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); in arct_reg_base_init()
54 adev->reg_offset[UMC_HWIP][i] = (uint32_t *)(&(UMC_BASE.instance[i])); in arct_reg_base_init()
[all …]
H A Daldebaran_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in aldebaran_reg_base_init()
35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in aldebaran_reg_base_init()
36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in aldebaran_reg_base_init()
37 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in aldebaran_reg_base_init()
38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in aldebaran_reg_base_init()
39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in aldebaran_reg_base_init()
40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in aldebaran_reg_base_init()
41 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in aldebaran_reg_base_init()
49 adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); in aldebaran_reg_base_init()
50 adev->reg_offset[UMC_HWIP][i] = (uint32_t *)(&(UMC_BASE.instance[i])); in aldebaran_reg_base_init()
[all …]
H A Ddimgrey_cavefish_reg_init.c35 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
36 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
40 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
41 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
42 adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN0_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
43 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
44 adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
46 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
47 adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
48 adev->reg_offset[SDMA2_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
[all …]
H A Dvega10_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega10_reg_base_init()
35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in vega10_reg_base_init()
39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega10_reg_base_init()
40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega10_reg_base_init()
41 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in vega10_reg_base_init()
42 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); in vega10_reg_base_init()
43 adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i])); in vega10_reg_base_init()
44 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in vega10_reg_base_init()
45 adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCE_BASE.instance[i])); in vega10_reg_base_init()
50 adev->reg_offset[PWR_HWIP][i] = (uint32_t *)(&(PWR_BASE.instance[i])); in vega10_reg_base_init()
[all …]
H A Dvega20_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega20_reg_base_init()
35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in vega20_reg_base_init()
39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega20_reg_base_init()
40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega20_reg_base_init()
41 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in vega20_reg_base_init()
42 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); in vega20_reg_base_init()
43 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in vega20_reg_base_init()
44 adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCE_BASE.instance[i])); in vega20_reg_base_init()
50 adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); in vega20_reg_base_init()
51 adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); in vega20_reg_base_init()
[all …]
H A Djpeg_v1_0.c42 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || in jpeg_v1_0_decode_ring_patch_wreg()
43 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { in jpeg_v1_0_decode_ring_patch_wreg()
61 reg_offset = (reg << 2); in jpeg_v1_0_decode_ring_set_patch_ring()
67 reg_offset = (reg << 2); in jpeg_v1_0_decode_ring_set_patch_ring()
79 reg_offset = (reg << 2); in jpeg_v1_0_decode_ring_set_patch_ring()
100 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || in jpeg_v1_0_decode_ring_set_patch_ring()
101 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { in jpeg_v1_0_decode_ring_set_patch_ring()
363 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || in jpeg_v1_0_decode_ring_emit_reg_wait()
364 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { in jpeg_v1_0_decode_ring_emit_reg_wait()
399 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || in jpeg_v1_0_decode_ring_emit_wreg()
[all …]
H A Dsoc15_common.h38 (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)+(offset))
53 adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
61 adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, \
67 __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
75 __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
93 __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
102 (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)), \
107 (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg) + (offset)), \
180 uint32_t target_reg = adev->reg_offset[GC_HWIP][inst][reg##_BASE_IDX] + reg;\
199 RREG32_PCIE_EXT((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) * 4 \
[all …]
H A Dmmsch_v1_0.h61 uint32_t reg_offset : 28; member
66 uint32_t reg_offset : 20; member
99 uint32_t reg_offset, in mmsch_v1_0_insert_direct_wt() argument
102 direct_wt->cmd_header.reg_offset = reg_offset; in mmsch_v1_0_insert_direct_wt()
109 uint32_t reg_offset, in mmsch_v1_0_insert_direct_rd_mod_wt() argument
112 direct_rd_mod_wt->cmd_header.reg_offset = reg_offset; in mmsch_v1_0_insert_direct_rd_mod_wt()
121 uint32_t reg_offset, in mmsch_v1_0_insert_direct_poll() argument
124 direct_poll->cmd_header.reg_offset = reg_offset; in mmsch_v1_0_insert_direct_poll()
H A Dsdma_v4_4.c40 uint32_t sdma_base = adev->reg_offset[SDMA0_HWIP][0][0]; in sdma_v4_4_get_reg_offset()
167 uint32_t reg_offset, in sdma_v4_4_get_ras_error_count() argument
177 if (sdma_v4_4_ras_fields[i].reg_offset != reg_offset) in sdma_v4_4_get_ras_error_count()
202 uint32_t reg_offset = 0; in sdma_v4_4_query_ras_error_count_by_instance() local
205 reg_value = RREG32(reg_offset); in sdma_v4_4_query_ras_error_count_by_instance()
212 reg_value = RREG32(reg_offset); in sdma_v4_4_query_ras_error_count_by_instance()
239 uint32_t reg_offset; in sdma_v4_4_reset_ras_error_count() local
244 reg_offset = sdma_v4_4_get_reg_offset(adev, i, regSDMA0_EDC_COUNTER); in sdma_v4_4_reset_ras_error_count()
245 WREG32(reg_offset, 0); in sdma_v4_4_reset_ras_error_count()
246 reg_offset = sdma_v4_4_get_reg_offset(adev, i, regSDMA0_EDC_COUNTER2); in sdma_v4_4_reset_ras_error_count()
[all …]
/openbmc/linux/drivers/soc/qcom/
H A Dspm.c45 .reg_offset = spm_reg_offset_v4_1,
51 .reg_offset = spm_reg_offset_v4_1,
57 .reg_offset = spm_reg_offset_v4_1,
63 .reg_offset = spm_reg_offset_v4_1,
77 .reg_offset = spm_reg_offset_v3_0,
89 .reg_offset = spm_reg_offset_v3_0,
100 .reg_offset = spm_reg_offset_v3_0,
120 .reg_offset = spm_reg_offset_v2_3,
130 .reg_offset = spm_reg_offset_v2_3,
148 .reg_offset = spm_reg_offset_v2_1,
[all …]
/openbmc/linux/drivers/input/misc/
H A Diqs7222.c797 int reg_offset; member
811 .reg_offset = 0,
819 .reg_offset = 0,
827 .reg_offset = 1,
835 .reg_offset = 1,
842 .reg_offset = 1,
849 .reg_offset = 1,
856 .reg_offset = 1,
865 .reg_offset = 2,
872 .reg_offset = 2,
[all …]

12345678910>>...16