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Searched refs:reg_offset (Results 1 – 25 of 34) sorted by relevance

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/openbmc/u-boot/drivers/power/pmic/
H A Dpmic_tps65910.c82 unsigned int reg_offset; in tps65910_voltage_update() local
86 reg_offset = TPS65910_VDD1_OP_REG; in tps65910_voltage_update()
88 reg_offset = TPS65910_VDD2_OP_REG; in tps65910_voltage_update()
91 ret = tps65910_read_reg(reg_offset, &buf); in tps65910_voltage_update()
97 ret = tps65910_write_reg(reg_offset, &buf); in tps65910_voltage_update()
102 ret = tps65910_read_reg(reg_offset, &buf); in tps65910_voltage_update()
109 ret = tps65910_write_reg(reg_offset, &buf); in tps65910_voltage_update()
113 ret = tps65910_read_reg(reg_offset, &buf); in tps65910_voltage_update()
/openbmc/qemu/tests/qtest/
H A Driscv-iommu-test.c18 static uint32_t riscv_iommu_read_reg32(QRISCVIOMMU *r_iommu, int reg_offset) in riscv_iommu_read_reg32() argument
20 return qpci_io_readl(&r_iommu->dev, r_iommu->reg_bar, reg_offset); in riscv_iommu_read_reg32()
23 static uint64_t riscv_iommu_read_reg64(QRISCVIOMMU *r_iommu, int reg_offset) in riscv_iommu_read_reg64() argument
25 return qpci_io_readq(&r_iommu->dev, r_iommu->reg_bar, reg_offset); in riscv_iommu_read_reg64()
28 static void riscv_iommu_write_reg32(QRISCVIOMMU *r_iommu, int reg_offset, in riscv_iommu_write_reg32() argument
31 qpci_io_writel(&r_iommu->dev, r_iommu->reg_bar, reg_offset, val); in riscv_iommu_write_reg32()
34 static void riscv_iommu_write_reg64(QRISCVIOMMU *r_iommu, int reg_offset, in riscv_iommu_write_reg64() argument
37 qpci_io_writeq(&r_iommu->dev, r_iommu->reg_bar, reg_offset, val); in riscv_iommu_write_reg64()
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dfsl_liodn.h14 unsigned long reg_offset[2]; member
20 .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
26 .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
28 .reg_offset[1] = offsetof(ccsr_gur_t, rio##port##maintliodnr) \
34 .reg_offset[0] = offsetof(struct ccsr_rio, liodn) \
44 unsigned long reg_offset; member
56 unsigned long reg_offset; member
73 .reg_offset = off + CONFIG_SYS_CCSRBAR, \
80 .reg_offset = off + CONFIG_SYS_CCSRBAR, \
87 .reg_offset = off + CONFIG_SYS_CCSRBAR, \
/openbmc/u-boot/drivers/pinctrl/mvebu/
H A Dpinctrl-mvebu.c98 int reg_offset; in mvebu_pinctrl_set_state() local
109 reg_offset = priv->reg_direction * 4 * in mvebu_pinctrl_set_state()
113 clrsetbits_le32(priv->base_reg + reg_offset, in mvebu_pinctrl_set_state()
155 int reg_offset; in mvebu_pinctrl_set_state_all() local
170 reg_offset = priv->reg_direction * 4 * in mvebu_pinctrl_set_state_all()
174 clrsetbits_le32(priv->base_reg + reg_offset, in mvebu_pinctrl_set_state_all()
/openbmc/openbmc/meta-facebook/meta-bletchley/recipes-bletchley/plat-tools/files/
H A Dbletchley-net-util69 for reg_offset in {0..31}
71 …printf "[%02X]: %04X\n" "$reg_offset" "$(mdio "$SWITCH_MDIO_BUS" phy "${PORT_NUM_MAP[port_phy]}" "…
/openbmc/u-boot/board/siemens/pxm2/
H A Dboard.c94 unsigned int reg_offset; in voltage_update() local
97 reg_offset = PMIC_VDD1_OP_REG; in voltage_update()
99 reg_offset = PMIC_VDD2_OP_REG; in voltage_update()
102 if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) in voltage_update()
107 if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) in voltage_update()
111 if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) in voltage_update()
117 if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) in voltage_update()
120 if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) in voltage_update()
/openbmc/u-boot/drivers/reset/
H A Dreset-meson.c40 uint reg_offset = LEVEL_OFFSET + (bank << 2); in meson_reset_level() local
43 regmap_read(priv->regmap, reg_offset, &val); in meson_reset_level()
48 regmap_write(priv->regmap, reg_offset, val); in meson_reset_level()
H A Dreset-rockchip.c106 int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number) in rockchip_reset_bind() argument
119 priv->reset_reg_offset = reg_offset; in rockchip_reset_bind()
/openbmc/u-boot/arch/arm/mach-omap2/am33xx/
H A Dmux.c31 for (i = 0; mod_pin_mux[i].reg_offset != -1; i++) in configure_module_pin_mux()
32 MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset); in configure_module_pin_mux()
/openbmc/u-boot/arch/arm/include/asm/arch-ls102xa/
H A Dls102xa_stream_id.h14 .reg_offset = off + CONFIG_SYS_IMMR, \
21 .reg_offset = off + CONFIG_SYS_IMMR, \
62 unsigned long reg_offset; member
/openbmc/u-boot/drivers/pinctrl/broadcom/
H A Dpinctrl-bcm283x.c35 int reg_offset; in bcm2835_gpio_set_func_id() local
38 reg_offset = BCM2835_GPIO_FSEL_BANK(gpio); in bcm2835_gpio_set_func_id()
41 clrsetbits_le32(&priv->base_reg[reg_offset], in bcm2835_gpio_set_func_id()
/openbmc/u-boot/drivers/gpio/
H A Dgpio-uniphier.c86 unsigned int bank, reg_offset; in uniphier_gpio_offset_read() local
90 reg_offset = uniphier_gpio_bank_to_reg(bank) + reg; in uniphier_gpio_offset_read()
92 return !!(readl(priv->regs + reg_offset) & mask); in uniphier_gpio_offset_read()
H A Dzynq_gpio.c220 unsigned int reg_offset, bank_num, bank_pin_num; in zynq_gpio_set_value() local
231 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num); in zynq_gpio_set_value()
233 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num); in zynq_gpio_set_value()
244 writel(value, platdata->base + reg_offset); in zynq_gpio_set_value()
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dliodn.c32 unsigned long reg_off = tbl[i].reg_offset[0]; in set_srio_liodn()
36 reg_off = tbl[i].reg_offset[1]; in set_srio_liodn()
55 out_be32((volatile u32 *)(tbl[i].reg_offset), liodn); in set_liodn()
71 out_be32((volatile u32 *)(tbl[i].reg_offset), liodn); in set_fman_liodn()
163 out_be32((u32 *)(tbl[i].reg_offset), tbl[i].id[0]); in set_rman_liodn()
/openbmc/u-boot/arch/arm/include/asm/arch-am33xx/
H A Dmux.h33 short reg_offset; member
/openbmc/u-boot/drivers/serial/
H A Dns16550.c107 serial_out_shift(addr + plat->reg_offset, plat->reg_shift, value); in ns16550_writeb()
118 return serial_in_shift(addr + plat->reg_offset, plat->reg_shift); in ns16550_readb()
406 info->reg_offset = plat->reg_offset; in ns16550_serial_getinfo()
482 plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0); in ns16550_serial_ofdata_to_platdata()
H A Dserial_intel_mid.c31 writel(value, addr + plat->reg_offset); in mid_writel()
/openbmc/u-boot/board/freescale/common/
H A Dls102xa_stream_id.c33 out_le32((u32 *)(tbl[i].reg_offset), liodn); in ls1021x_config_caam_stream_id()
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dclock.h101 int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
/openbmc/qemu/include/hw/intc/
H A Daspeed_intc.h61 uint64_t reg_offset; member
/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_ip_engine.c703 u32 reg_offset, pup_cnt, start_pup, end_pup, start_reg, end_reg; in ddr3_tip_read_training_result() local
789 for (reg_offset = start_reg; reg_offset <= end_reg; in ddr3_tip_read_training_result()
790 reg_offset++) { in ddr3_tip_read_training_result()
797 reg_addr[reg_offset], in ddr3_tip_read_training_result()
804 [reg_offset] = in ddr3_tip_read_training_result()
809 [reg_offset] = in ddr3_tip_read_training_result()
815 interface_train_res[reg_offset] in ddr3_tip_read_training_result()
822 reg_offset, in ddr3_tip_read_training_result()
824 [reg_offset], in ddr3_tip_read_training_result()
826 [reg_offset])); in ddr3_tip_read_training_result()
/openbmc/u-boot/drivers/net/
H A Dsh_eth.h606 const u16 *reg_offset = sh_eth_offset_gigabit; in sh_eth_reg_addr() local
608 const u16 *reg_offset = sh_eth_offset_fast_sh4; in sh_eth_reg_addr()
612 return (unsigned long)port->iobase + reg_offset[enum_index]; in sh_eth_reg_addr()
H A Dmvgbe.c348 u32 reg_offset; in port_uc_addr() local
355 reg_offset = uc_nibble % 4; in port_uc_addr()
364 unicast_reg &= (0xFF << (8 * reg_offset)); in port_uc_addr()
370 unicast_reg &= (0xFF << (8 * reg_offset)); in port_uc_addr()
371 unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset)); in port_uc_addr()
/openbmc/qemu/hw/intc/
H A Daspeed_intc.c844 memory_region_add_subregion(&s->iomem_container, aic->reg_offset, in aspeed_intc_realize()
916 aic->reg_offset = 0x1000; in aspeed_2700_intc_class_init()
947 aic->reg_offset = 0x100; in aspeed_2700_intcio_class_init()
983 aic->reg_offset = 0x0; in aspeed_2700ssp_intc_class_init()
1016 aic->reg_offset = 0; in aspeed_2700ssp_intcio_class_init()
1052 aic->reg_offset = 0; in aspeed_2700tsp_intc_class_init()
1085 aic->reg_offset = 0x0; in aspeed_2700tsp_intcio_class_init()
/openbmc/u-boot/include/
H A Dns16550.h60 int reg_offset; member

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