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Searched refs:regGCVM_L2_PROTECTION_FAULT_CNTL (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v3_0_3.c414 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v3_0_3_set_fault_enable_default()
444 WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp); in gfxhub_v3_0_3_set_fault_enable_default()
473 SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v3_0_3_init()
H A Dgfxhub_v3_0.c426 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v3_0_set_fault_enable_default()
456 WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp); in gfxhub_v3_0_set_fault_enable_default()
485 SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v3_0_init()
H A Dimu_v11_0.c217 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, 0x00001ffc, 0xe0000000),
299 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, 0x00001ffc, 0xe0000000),
H A Dimu_v11_0_3.c81 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, 0x00001ffc, 0xe0000000),
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_3_offset.h2888 #define regGCVM_L2_PROTECTION_FAULT_CNTL … macro
H A Dgc_11_0_0_offset.h2746 #define regGCVM_L2_PROTECTION_FAULT_CNTL … macro