1f33ac92fSHawking Zhang /* 2f33ac92fSHawking Zhang * Copyright 2021 Advanced Micro Devices, Inc. 3f33ac92fSHawking Zhang * 4f33ac92fSHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5f33ac92fSHawking Zhang * copy of this software and associated documentation files (the "Software"), 6f33ac92fSHawking Zhang * to deal in the Software without restriction, including without limitation 7f33ac92fSHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8f33ac92fSHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9f33ac92fSHawking Zhang * Software is furnished to do so, subject to the following conditions: 10f33ac92fSHawking Zhang * 11f33ac92fSHawking Zhang * The above copyright notice and this permission notice shall be included in 12f33ac92fSHawking Zhang * all copies or substantial portions of the Software. 13f33ac92fSHawking Zhang * 14f33ac92fSHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15f33ac92fSHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16f33ac92fSHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17f33ac92fSHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18f33ac92fSHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19f33ac92fSHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20f33ac92fSHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21f33ac92fSHawking Zhang * 22f33ac92fSHawking Zhang */ 23f33ac92fSHawking Zhang #ifndef _gc_11_0_0_OFFSET_HEADER 24f33ac92fSHawking Zhang #define _gc_11_0_0_OFFSET_HEADER 25f33ac92fSHawking Zhang 26f33ac92fSHawking Zhang 27f33ac92fSHawking Zhang 28f33ac92fSHawking Zhang // addressBlock: gc_sdma0_sdma0dec 29f33ac92fSHawking Zhang // base address: 0x4980 30f33ac92fSHawking Zhang #define regSDMA0_DEC_START 0x0000 31f33ac92fSHawking Zhang #define regSDMA0_DEC_START_BASE_IDX 0 32f33ac92fSHawking Zhang #define regSDMA0_F32_MISC_CNTL 0x000b 33f33ac92fSHawking Zhang #define regSDMA0_F32_MISC_CNTL_BASE_IDX 0 34f33ac92fSHawking Zhang #define regSDMA0_GLOBAL_TIMESTAMP_LO 0x000f 35f33ac92fSHawking Zhang #define regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0 36f33ac92fSHawking Zhang #define regSDMA0_GLOBAL_TIMESTAMP_HI 0x0010 37f33ac92fSHawking Zhang #define regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0 38f33ac92fSHawking Zhang #define regSDMA0_POWER_CNTL 0x001a 39f33ac92fSHawking Zhang #define regSDMA0_POWER_CNTL_BASE_IDX 0 40f33ac92fSHawking Zhang #define regSDMA0_CNTL 0x001c 41f33ac92fSHawking Zhang #define regSDMA0_CNTL_BASE_IDX 0 42f33ac92fSHawking Zhang #define regSDMA0_CHICKEN_BITS 0x001d 43f33ac92fSHawking Zhang #define regSDMA0_CHICKEN_BITS_BASE_IDX 0 44f33ac92fSHawking Zhang #define regSDMA0_GB_ADDR_CONFIG 0x001e 45f33ac92fSHawking Zhang #define regSDMA0_GB_ADDR_CONFIG_BASE_IDX 0 46f33ac92fSHawking Zhang #define regSDMA0_GB_ADDR_CONFIG_READ 0x001f 47f33ac92fSHawking Zhang #define regSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX 0 48f33ac92fSHawking Zhang #define regSDMA0_RB_RPTR_FETCH 0x0020 49f33ac92fSHawking Zhang #define regSDMA0_RB_RPTR_FETCH_BASE_IDX 0 50f33ac92fSHawking Zhang #define regSDMA0_RB_RPTR_FETCH_HI 0x0021 51f33ac92fSHawking Zhang #define regSDMA0_RB_RPTR_FETCH_HI_BASE_IDX 0 52f33ac92fSHawking Zhang #define regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0022 53f33ac92fSHawking Zhang #define regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 54f33ac92fSHawking Zhang #define regSDMA0_IB_OFFSET_FETCH 0x0023 55f33ac92fSHawking Zhang #define regSDMA0_IB_OFFSET_FETCH_BASE_IDX 0 56f33ac92fSHawking Zhang #define regSDMA0_PROGRAM 0x0024 57f33ac92fSHawking Zhang #define regSDMA0_PROGRAM_BASE_IDX 0 58f33ac92fSHawking Zhang #define regSDMA0_STATUS_REG 0x0025 59f33ac92fSHawking Zhang #define regSDMA0_STATUS_REG_BASE_IDX 0 60f33ac92fSHawking Zhang #define regSDMA0_STATUS1_REG 0x0026 61f33ac92fSHawking Zhang #define regSDMA0_STATUS1_REG_BASE_IDX 0 62f33ac92fSHawking Zhang #define regSDMA0_CNTL1 0x0027 63f33ac92fSHawking Zhang #define regSDMA0_CNTL1_BASE_IDX 0 64f33ac92fSHawking Zhang #define regSDMA0_HBM_PAGE_CONFIG 0x0028 65f33ac92fSHawking Zhang #define regSDMA0_HBM_PAGE_CONFIG_BASE_IDX 0 66f33ac92fSHawking Zhang #define regSDMA0_UCODE_CHECKSUM 0x0029 67f33ac92fSHawking Zhang #define regSDMA0_UCODE_CHECKSUM_BASE_IDX 0 68f33ac92fSHawking Zhang #define regSDMA0_FREEZE 0x002b 69f33ac92fSHawking Zhang #define regSDMA0_FREEZE_BASE_IDX 0 70f33ac92fSHawking Zhang #define regSDMA0_PROCESS_QUANTUM0 0x002c 71f33ac92fSHawking Zhang #define regSDMA0_PROCESS_QUANTUM0_BASE_IDX 0 72f33ac92fSHawking Zhang #define regSDMA0_PROCESS_QUANTUM1 0x002d 73f33ac92fSHawking Zhang #define regSDMA0_PROCESS_QUANTUM1_BASE_IDX 0 74f33ac92fSHawking Zhang #define regSDMA0_WATCHDOG_CNTL 0x002e 75f33ac92fSHawking Zhang #define regSDMA0_WATCHDOG_CNTL_BASE_IDX 0 76f33ac92fSHawking Zhang #define regSDMA0_QUEUE_STATUS0 0x002f 77f33ac92fSHawking Zhang #define regSDMA0_QUEUE_STATUS0_BASE_IDX 0 78f33ac92fSHawking Zhang #define regSDMA0_EDC_CONFIG 0x0032 79f33ac92fSHawking Zhang #define regSDMA0_EDC_CONFIG_BASE_IDX 0 80f33ac92fSHawking Zhang #define regSDMA0_BA_THRESHOLD 0x0033 81f33ac92fSHawking Zhang #define regSDMA0_BA_THRESHOLD_BASE_IDX 0 82f33ac92fSHawking Zhang #define regSDMA0_ID 0x0034 83f33ac92fSHawking Zhang #define regSDMA0_ID_BASE_IDX 0 84f33ac92fSHawking Zhang #define regSDMA0_VERSION 0x0035 85f33ac92fSHawking Zhang #define regSDMA0_VERSION_BASE_IDX 0 86f33ac92fSHawking Zhang #define regSDMA0_EDC_COUNTER 0x0036 87f33ac92fSHawking Zhang #define regSDMA0_EDC_COUNTER_BASE_IDX 0 88f33ac92fSHawking Zhang #define regSDMA0_EDC_COUNTER_CLEAR 0x0037 89f33ac92fSHawking Zhang #define regSDMA0_EDC_COUNTER_CLEAR_BASE_IDX 0 90f33ac92fSHawking Zhang #define regSDMA0_STATUS2_REG 0x0038 91f33ac92fSHawking Zhang #define regSDMA0_STATUS2_REG_BASE_IDX 0 92f33ac92fSHawking Zhang #define regSDMA0_ATOMIC_CNTL 0x0039 93f33ac92fSHawking Zhang #define regSDMA0_ATOMIC_CNTL_BASE_IDX 0 94f33ac92fSHawking Zhang #define regSDMA0_ATOMIC_PREOP_LO 0x003a 95f33ac92fSHawking Zhang #define regSDMA0_ATOMIC_PREOP_LO_BASE_IDX 0 96f33ac92fSHawking Zhang #define regSDMA0_ATOMIC_PREOP_HI 0x003b 97f33ac92fSHawking Zhang #define regSDMA0_ATOMIC_PREOP_HI_BASE_IDX 0 98f33ac92fSHawking Zhang #define regSDMA0_UTCL1_CNTL 0x003c 99f33ac92fSHawking Zhang #define regSDMA0_UTCL1_CNTL_BASE_IDX 0 100f33ac92fSHawking Zhang #define regSDMA0_UTCL1_WATERMK 0x003d 101f33ac92fSHawking Zhang #define regSDMA0_UTCL1_WATERMK_BASE_IDX 0 102f33ac92fSHawking Zhang #define regSDMA0_UTCL1_TIMEOUT 0x003e 103f33ac92fSHawking Zhang #define regSDMA0_UTCL1_TIMEOUT_BASE_IDX 0 104f33ac92fSHawking Zhang #define regSDMA0_UTCL1_PAGE 0x003f 105f33ac92fSHawking Zhang #define regSDMA0_UTCL1_PAGE_BASE_IDX 0 106f33ac92fSHawking Zhang #define regSDMA0_UTCL1_RD_STATUS 0x0040 107f33ac92fSHawking Zhang #define regSDMA0_UTCL1_RD_STATUS_BASE_IDX 0 108f33ac92fSHawking Zhang #define regSDMA0_UTCL1_WR_STATUS 0x0041 109f33ac92fSHawking Zhang #define regSDMA0_UTCL1_WR_STATUS_BASE_IDX 0 110f33ac92fSHawking Zhang #define regSDMA0_UTCL1_INV0 0x0042 111f33ac92fSHawking Zhang #define regSDMA0_UTCL1_INV0_BASE_IDX 0 112f33ac92fSHawking Zhang #define regSDMA0_UTCL1_INV1 0x0043 113f33ac92fSHawking Zhang #define regSDMA0_UTCL1_INV1_BASE_IDX 0 114f33ac92fSHawking Zhang #define regSDMA0_UTCL1_INV2 0x0044 115f33ac92fSHawking Zhang #define regSDMA0_UTCL1_INV2_BASE_IDX 0 116f33ac92fSHawking Zhang #define regSDMA0_UTCL1_RD_XNACK0 0x0045 117f33ac92fSHawking Zhang #define regSDMA0_UTCL1_RD_XNACK0_BASE_IDX 0 118f33ac92fSHawking Zhang #define regSDMA0_UTCL1_RD_XNACK1 0x0046 119f33ac92fSHawking Zhang #define regSDMA0_UTCL1_RD_XNACK1_BASE_IDX 0 120f33ac92fSHawking Zhang #define regSDMA0_UTCL1_WR_XNACK0 0x0047 121f33ac92fSHawking Zhang #define regSDMA0_UTCL1_WR_XNACK0_BASE_IDX 0 122f33ac92fSHawking Zhang #define regSDMA0_UTCL1_WR_XNACK1 0x0048 123f33ac92fSHawking Zhang #define regSDMA0_UTCL1_WR_XNACK1_BASE_IDX 0 124f33ac92fSHawking Zhang #define regSDMA0_RELAX_ORDERING_LUT 0x004a 125f33ac92fSHawking Zhang #define regSDMA0_RELAX_ORDERING_LUT_BASE_IDX 0 126f33ac92fSHawking Zhang #define regSDMA0_CHICKEN_BITS_2 0x004b 127f33ac92fSHawking Zhang #define regSDMA0_CHICKEN_BITS_2_BASE_IDX 0 128f33ac92fSHawking Zhang #define regSDMA0_STATUS3_REG 0x004c 129f33ac92fSHawking Zhang #define regSDMA0_STATUS3_REG_BASE_IDX 0 130f33ac92fSHawking Zhang #define regSDMA0_PHYSICAL_ADDR_LO 0x004d 131f33ac92fSHawking Zhang #define regSDMA0_PHYSICAL_ADDR_LO_BASE_IDX 0 132f33ac92fSHawking Zhang #define regSDMA0_PHYSICAL_ADDR_HI 0x004e 133f33ac92fSHawking Zhang #define regSDMA0_PHYSICAL_ADDR_HI_BASE_IDX 0 134f33ac92fSHawking Zhang #define regSDMA0_GLOBAL_QUANTUM 0x004f 135f33ac92fSHawking Zhang #define regSDMA0_GLOBAL_QUANTUM_BASE_IDX 0 136f33ac92fSHawking Zhang #define regSDMA0_ERROR_LOG 0x0050 137f33ac92fSHawking Zhang #define regSDMA0_ERROR_LOG_BASE_IDX 0 138f33ac92fSHawking Zhang #define regSDMA0_PUB_DUMMY_REG0 0x0051 139f33ac92fSHawking Zhang #define regSDMA0_PUB_DUMMY_REG0_BASE_IDX 0 140f33ac92fSHawking Zhang #define regSDMA0_PUB_DUMMY_REG1 0x0052 141f33ac92fSHawking Zhang #define regSDMA0_PUB_DUMMY_REG1_BASE_IDX 0 142f33ac92fSHawking Zhang #define regSDMA0_PUB_DUMMY_REG2 0x0053 143f33ac92fSHawking Zhang #define regSDMA0_PUB_DUMMY_REG2_BASE_IDX 0 144f33ac92fSHawking Zhang #define regSDMA0_PUB_DUMMY_REG3 0x0054 145f33ac92fSHawking Zhang #define regSDMA0_PUB_DUMMY_REG3_BASE_IDX 0 146f33ac92fSHawking Zhang #define regSDMA0_F32_COUNTER 0x0055 147f33ac92fSHawking Zhang #define regSDMA0_F32_COUNTER_BASE_IDX 0 148f33ac92fSHawking Zhang #define regSDMA0_CRD_CNTL 0x005b 149f33ac92fSHawking Zhang #define regSDMA0_CRD_CNTL_BASE_IDX 0 150f33ac92fSHawking Zhang #define regSDMA0_RLC_CGCG_CTRL 0x005c 151f33ac92fSHawking Zhang #define regSDMA0_RLC_CGCG_CTRL_BASE_IDX 0 152f33ac92fSHawking Zhang #define regSDMA0_AQL_STATUS 0x005f 153f33ac92fSHawking Zhang #define regSDMA0_AQL_STATUS_BASE_IDX 0 154f33ac92fSHawking Zhang #define regSDMA0_EA_DBIT_ADDR_DATA 0x0060 155f33ac92fSHawking Zhang #define regSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX 0 156f33ac92fSHawking Zhang #define regSDMA0_EA_DBIT_ADDR_INDEX 0x0061 157f33ac92fSHawking Zhang #define regSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX 0 158f33ac92fSHawking Zhang #define regSDMA0_TLBI_GCR_CNTL 0x0062 159f33ac92fSHawking Zhang #define regSDMA0_TLBI_GCR_CNTL_BASE_IDX 0 160f33ac92fSHawking Zhang #define regSDMA0_TILING_CONFIG 0x0063 161f33ac92fSHawking Zhang #define regSDMA0_TILING_CONFIG_BASE_IDX 0 162f33ac92fSHawking Zhang #define regSDMA0_INT_STATUS 0x0070 163f33ac92fSHawking Zhang #define regSDMA0_INT_STATUS_BASE_IDX 0 164f33ac92fSHawking Zhang #define regSDMA0_HOLE_ADDR_LO 0x0072 165f33ac92fSHawking Zhang #define regSDMA0_HOLE_ADDR_LO_BASE_IDX 0 166f33ac92fSHawking Zhang #define regSDMA0_HOLE_ADDR_HI 0x0073 167f33ac92fSHawking Zhang #define regSDMA0_HOLE_ADDR_HI_BASE_IDX 0 168f33ac92fSHawking Zhang #define regSDMA0_CLOCK_GATING_STATUS 0x0075 169f33ac92fSHawking Zhang #define regSDMA0_CLOCK_GATING_STATUS_BASE_IDX 0 170f33ac92fSHawking Zhang #define regSDMA0_STATUS4_REG 0x0076 171f33ac92fSHawking Zhang #define regSDMA0_STATUS4_REG_BASE_IDX 0 172f33ac92fSHawking Zhang #define regSDMA0_SCRATCH_RAM_DATA 0x0077 173f33ac92fSHawking Zhang #define regSDMA0_SCRATCH_RAM_DATA_BASE_IDX 0 174f33ac92fSHawking Zhang #define regSDMA0_SCRATCH_RAM_ADDR 0x0078 175f33ac92fSHawking Zhang #define regSDMA0_SCRATCH_RAM_ADDR_BASE_IDX 0 176f33ac92fSHawking Zhang #define regSDMA0_TIMESTAMP_CNTL 0x0079 177f33ac92fSHawking Zhang #define regSDMA0_TIMESTAMP_CNTL_BASE_IDX 0 178f33ac92fSHawking Zhang #define regSDMA0_STATUS5_REG 0x007a 179f33ac92fSHawking Zhang #define regSDMA0_STATUS5_REG_BASE_IDX 0 180f33ac92fSHawking Zhang #define regSDMA0_QUEUE_RESET_REQ 0x007b 181f33ac92fSHawking Zhang #define regSDMA0_QUEUE_RESET_REQ_BASE_IDX 0 182f33ac92fSHawking Zhang #define regSDMA0_STATUS6_REG 0x007c 183f33ac92fSHawking Zhang #define regSDMA0_STATUS6_REG_BASE_IDX 0 184f33ac92fSHawking Zhang #define regSDMA0_UCODE1_CHECKSUM 0x007d 185f33ac92fSHawking Zhang #define regSDMA0_UCODE1_CHECKSUM_BASE_IDX 0 186f33ac92fSHawking Zhang #define regSDMA0_CE_CTRL 0x007e 187f33ac92fSHawking Zhang #define regSDMA0_CE_CTRL_BASE_IDX 0 188f33ac92fSHawking Zhang #define regSDMA0_FED_STATUS 0x007f 189f33ac92fSHawking Zhang #define regSDMA0_FED_STATUS_BASE_IDX 0 190f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_RB_CNTL 0x0080 191f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_RB_CNTL_BASE_IDX 0 192f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_RB_BASE 0x0081 193f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_RB_BASE_BASE_IDX 0 194f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_RB_BASE_HI 0x0082 195f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_RB_BASE_HI_BASE_IDX 0 196f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_RB_RPTR 0x0083 197f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_RB_RPTR_BASE_IDX 0 198f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_RB_RPTR_HI 0x0084 199f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_RB_RPTR_HI_BASE_IDX 0 200f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_RB_WPTR 0x0085 201f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_RB_WPTR_BASE_IDX 0 202f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_RB_WPTR_HI 0x0086 203f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_RB_WPTR_HI_BASE_IDX 0 204f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_RB_RPTR_ADDR_HI 0x0088 205f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX 0 206f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_RB_RPTR_ADDR_LO 0x0089 207f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX 0 208f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_IB_CNTL 0x008a 209f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_IB_CNTL_BASE_IDX 0 210f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_IB_RPTR 0x008b 211f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_IB_RPTR_BASE_IDX 0 212f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_IB_OFFSET 0x008c 213f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_IB_OFFSET_BASE_IDX 0 214f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_IB_BASE_LO 0x008d 215f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_IB_BASE_LO_BASE_IDX 0 216f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_IB_BASE_HI 0x008e 217f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_IB_BASE_HI_BASE_IDX 0 218f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_IB_SIZE 0x008f 219f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_IB_SIZE_BASE_IDX 0 220f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_SKIP_CNTL 0x0090 221f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_SKIP_CNTL_BASE_IDX 0 222f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_CONTEXT_STATUS 0x0091 223f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_CONTEXT_STATUS_BASE_IDX 0 224f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_DOORBELL 0x0092 225f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_DOORBELL_BASE_IDX 0 226f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_DOORBELL_LOG 0x00a9 227f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_DOORBELL_LOG_BASE_IDX 0 228f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_DOORBELL_OFFSET 0x00ab 229f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_DOORBELL_OFFSET_BASE_IDX 0 230f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_CSA_ADDR_LO 0x00ac 231f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_CSA_ADDR_LO_BASE_IDX 0 232f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_CSA_ADDR_HI 0x00ad 233f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_CSA_ADDR_HI_BASE_IDX 0 234f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_SCHEDULE_CNTL 0x00ae 235f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_SCHEDULE_CNTL_BASE_IDX 0 236f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_IB_SUB_REMAIN 0x00af 237f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_IB_SUB_REMAIN_BASE_IDX 0 238f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_PREEMPT 0x00b0 239f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_PREEMPT_BASE_IDX 0 240f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_DUMMY_REG 0x00b1 241f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_DUMMY_REG_BASE_IDX 0 242f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI 0x00b2 243f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 244f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO 0x00b3 245f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 246f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_RB_AQL_CNTL 0x00b4 247f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_RB_AQL_CNTL_BASE_IDX 0 248f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_MINOR_PTR_UPDATE 0x00b5 249f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX 0 250f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_RB_PREEMPT 0x00b6 251f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_RB_PREEMPT_BASE_IDX 0 252f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_MIDCMD_DATA0 0x00c0 253f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_MIDCMD_DATA0_BASE_IDX 0 254f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_MIDCMD_DATA1 0x00c1 255f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_MIDCMD_DATA1_BASE_IDX 0 256f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_MIDCMD_DATA2 0x00c2 257f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_MIDCMD_DATA2_BASE_IDX 0 258f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_MIDCMD_DATA3 0x00c3 259f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_MIDCMD_DATA3_BASE_IDX 0 260f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_MIDCMD_DATA4 0x00c4 261f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_MIDCMD_DATA4_BASE_IDX 0 262f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_MIDCMD_DATA5 0x00c5 263f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_MIDCMD_DATA5_BASE_IDX 0 264f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_MIDCMD_DATA6 0x00c6 265f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_MIDCMD_DATA6_BASE_IDX 0 266f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_MIDCMD_DATA7 0x00c7 267f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_MIDCMD_DATA7_BASE_IDX 0 268f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_MIDCMD_DATA8 0x00c8 269f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_MIDCMD_DATA8_BASE_IDX 0 270f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_MIDCMD_DATA9 0x00c9 271f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_MIDCMD_DATA9_BASE_IDX 0 272f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_MIDCMD_DATA10 0x00ca 273f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_MIDCMD_DATA10_BASE_IDX 0 274f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_MIDCMD_CNTL 0x00cb 275f33ac92fSHawking Zhang #define regSDMA0_QUEUE0_MIDCMD_CNTL_BASE_IDX 0 276f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_RB_CNTL 0x00d8 277f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_RB_CNTL_BASE_IDX 0 278f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_RB_BASE 0x00d9 279f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_RB_BASE_BASE_IDX 0 280f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_RB_BASE_HI 0x00da 281f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_RB_BASE_HI_BASE_IDX 0 282f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_RB_RPTR 0x00db 283f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_RB_RPTR_BASE_IDX 0 284f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_RB_RPTR_HI 0x00dc 285f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_RB_RPTR_HI_BASE_IDX 0 286f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_RB_WPTR 0x00dd 287f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_RB_WPTR_BASE_IDX 0 288f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_RB_WPTR_HI 0x00de 289f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_RB_WPTR_HI_BASE_IDX 0 290f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_RB_RPTR_ADDR_HI 0x00e0 291f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX 0 292f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_RB_RPTR_ADDR_LO 0x00e1 293f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX 0 294f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_IB_CNTL 0x00e2 295f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_IB_CNTL_BASE_IDX 0 296f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_IB_RPTR 0x00e3 297f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_IB_RPTR_BASE_IDX 0 298f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_IB_OFFSET 0x00e4 299f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_IB_OFFSET_BASE_IDX 0 300f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_IB_BASE_LO 0x00e5 301f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_IB_BASE_LO_BASE_IDX 0 302f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_IB_BASE_HI 0x00e6 303f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_IB_BASE_HI_BASE_IDX 0 304f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_IB_SIZE 0x00e7 305f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_IB_SIZE_BASE_IDX 0 306f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_SKIP_CNTL 0x00e8 307f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_SKIP_CNTL_BASE_IDX 0 308f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_CONTEXT_STATUS 0x00e9 309f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_CONTEXT_STATUS_BASE_IDX 0 310f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_DOORBELL 0x00ea 311f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_DOORBELL_BASE_IDX 0 312f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_DOORBELL_LOG 0x0101 313f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_DOORBELL_LOG_BASE_IDX 0 314f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_DOORBELL_OFFSET 0x0103 315f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_DOORBELL_OFFSET_BASE_IDX 0 316f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_CSA_ADDR_LO 0x0104 317f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_CSA_ADDR_LO_BASE_IDX 0 318f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_CSA_ADDR_HI 0x0105 319f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_CSA_ADDR_HI_BASE_IDX 0 320f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_SCHEDULE_CNTL 0x0106 321f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_SCHEDULE_CNTL_BASE_IDX 0 322f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_IB_SUB_REMAIN 0x0107 323f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_IB_SUB_REMAIN_BASE_IDX 0 324f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_PREEMPT 0x0108 325f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_PREEMPT_BASE_IDX 0 326f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_DUMMY_REG 0x0109 327f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_DUMMY_REG_BASE_IDX 0 328f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI 0x010a 329f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 330f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO 0x010b 331f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 332f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_RB_AQL_CNTL 0x010c 333f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_RB_AQL_CNTL_BASE_IDX 0 334f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_MINOR_PTR_UPDATE 0x010d 335f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX 0 336f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_RB_PREEMPT 0x010e 337f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_RB_PREEMPT_BASE_IDX 0 338f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_MIDCMD_DATA0 0x0118 339f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_MIDCMD_DATA0_BASE_IDX 0 340f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_MIDCMD_DATA1 0x0119 341f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_MIDCMD_DATA1_BASE_IDX 0 342f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_MIDCMD_DATA2 0x011a 343f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_MIDCMD_DATA2_BASE_IDX 0 344f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_MIDCMD_DATA3 0x011b 345f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_MIDCMD_DATA3_BASE_IDX 0 346f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_MIDCMD_DATA4 0x011c 347f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_MIDCMD_DATA4_BASE_IDX 0 348f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_MIDCMD_DATA5 0x011d 349f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_MIDCMD_DATA5_BASE_IDX 0 350f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_MIDCMD_DATA6 0x011e 351f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_MIDCMD_DATA6_BASE_IDX 0 352f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_MIDCMD_DATA7 0x011f 353f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_MIDCMD_DATA7_BASE_IDX 0 354f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_MIDCMD_DATA8 0x0120 355f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_MIDCMD_DATA8_BASE_IDX 0 356f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_MIDCMD_DATA9 0x0121 357f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_MIDCMD_DATA9_BASE_IDX 0 358f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_MIDCMD_DATA10 0x0122 359f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_MIDCMD_DATA10_BASE_IDX 0 360f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_MIDCMD_CNTL 0x0123 361f33ac92fSHawking Zhang #define regSDMA0_QUEUE1_MIDCMD_CNTL_BASE_IDX 0 362f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_RB_CNTL 0x0130 363f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_RB_CNTL_BASE_IDX 0 364f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_RB_BASE 0x0131 365f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_RB_BASE_BASE_IDX 0 366f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_RB_BASE_HI 0x0132 367f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_RB_BASE_HI_BASE_IDX 0 368f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_RB_RPTR 0x0133 369f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_RB_RPTR_BASE_IDX 0 370f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_RB_RPTR_HI 0x0134 371f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_RB_RPTR_HI_BASE_IDX 0 372f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_RB_WPTR 0x0135 373f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_RB_WPTR_BASE_IDX 0 374f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_RB_WPTR_HI 0x0136 375f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_RB_WPTR_HI_BASE_IDX 0 376f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_RB_RPTR_ADDR_HI 0x0138 377f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX 0 378f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_RB_RPTR_ADDR_LO 0x0139 379f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX 0 380f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_IB_CNTL 0x013a 381f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_IB_CNTL_BASE_IDX 0 382f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_IB_RPTR 0x013b 383f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_IB_RPTR_BASE_IDX 0 384f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_IB_OFFSET 0x013c 385f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_IB_OFFSET_BASE_IDX 0 386f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_IB_BASE_LO 0x013d 387f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_IB_BASE_LO_BASE_IDX 0 388f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_IB_BASE_HI 0x013e 389f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_IB_BASE_HI_BASE_IDX 0 390f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_IB_SIZE 0x013f 391f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_IB_SIZE_BASE_IDX 0 392f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_SKIP_CNTL 0x0140 393f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_SKIP_CNTL_BASE_IDX 0 394f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_CONTEXT_STATUS 0x0141 395f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_CONTEXT_STATUS_BASE_IDX 0 396f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_DOORBELL 0x0142 397f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_DOORBELL_BASE_IDX 0 398f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_DOORBELL_LOG 0x0159 399f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_DOORBELL_LOG_BASE_IDX 0 400f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_DOORBELL_OFFSET 0x015b 401f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_DOORBELL_OFFSET_BASE_IDX 0 402f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_CSA_ADDR_LO 0x015c 403f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_CSA_ADDR_LO_BASE_IDX 0 404f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_CSA_ADDR_HI 0x015d 405f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_CSA_ADDR_HI_BASE_IDX 0 406f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_SCHEDULE_CNTL 0x015e 407f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_SCHEDULE_CNTL_BASE_IDX 0 408f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_IB_SUB_REMAIN 0x015f 409f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_IB_SUB_REMAIN_BASE_IDX 0 410f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_PREEMPT 0x0160 411f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_PREEMPT_BASE_IDX 0 412f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_DUMMY_REG 0x0161 413f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_DUMMY_REG_BASE_IDX 0 414f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI 0x0162 415f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 416f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO 0x0163 417f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 418f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_RB_AQL_CNTL 0x0164 419f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_RB_AQL_CNTL_BASE_IDX 0 420f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_MINOR_PTR_UPDATE 0x0165 421f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX 0 422f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_RB_PREEMPT 0x0166 423f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_RB_PREEMPT_BASE_IDX 0 424f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_MIDCMD_DATA0 0x0170 425f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_MIDCMD_DATA0_BASE_IDX 0 426f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_MIDCMD_DATA1 0x0171 427f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_MIDCMD_DATA1_BASE_IDX 0 428f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_MIDCMD_DATA2 0x0172 429f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_MIDCMD_DATA2_BASE_IDX 0 430f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_MIDCMD_DATA3 0x0173 431f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_MIDCMD_DATA3_BASE_IDX 0 432f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_MIDCMD_DATA4 0x0174 433f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_MIDCMD_DATA4_BASE_IDX 0 434f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_MIDCMD_DATA5 0x0175 435f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_MIDCMD_DATA5_BASE_IDX 0 436f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_MIDCMD_DATA6 0x0176 437f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_MIDCMD_DATA6_BASE_IDX 0 438f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_MIDCMD_DATA7 0x0177 439f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_MIDCMD_DATA7_BASE_IDX 0 440f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_MIDCMD_DATA8 0x0178 441f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_MIDCMD_DATA8_BASE_IDX 0 442f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_MIDCMD_DATA9 0x0179 443f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_MIDCMD_DATA9_BASE_IDX 0 444f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_MIDCMD_DATA10 0x017a 445f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_MIDCMD_DATA10_BASE_IDX 0 446f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_MIDCMD_CNTL 0x017b 447f33ac92fSHawking Zhang #define regSDMA0_QUEUE2_MIDCMD_CNTL_BASE_IDX 0 448f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_RB_CNTL 0x0188 449f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_RB_CNTL_BASE_IDX 0 450f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_RB_BASE 0x0189 451f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_RB_BASE_BASE_IDX 0 452f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_RB_BASE_HI 0x018a 453f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_RB_BASE_HI_BASE_IDX 0 454f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_RB_RPTR 0x018b 455f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_RB_RPTR_BASE_IDX 0 456f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_RB_RPTR_HI 0x018c 457f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_RB_RPTR_HI_BASE_IDX 0 458f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_RB_WPTR 0x018d 459f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_RB_WPTR_BASE_IDX 0 460f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_RB_WPTR_HI 0x018e 461f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_RB_WPTR_HI_BASE_IDX 0 462f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_RB_RPTR_ADDR_HI 0x0190 463f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX 0 464f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_RB_RPTR_ADDR_LO 0x0191 465f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX 0 466f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_IB_CNTL 0x0192 467f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_IB_CNTL_BASE_IDX 0 468f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_IB_RPTR 0x0193 469f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_IB_RPTR_BASE_IDX 0 470f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_IB_OFFSET 0x0194 471f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_IB_OFFSET_BASE_IDX 0 472f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_IB_BASE_LO 0x0195 473f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_IB_BASE_LO_BASE_IDX 0 474f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_IB_BASE_HI 0x0196 475f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_IB_BASE_HI_BASE_IDX 0 476f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_IB_SIZE 0x0197 477f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_IB_SIZE_BASE_IDX 0 478f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_SKIP_CNTL 0x0198 479f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_SKIP_CNTL_BASE_IDX 0 480f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_CONTEXT_STATUS 0x0199 481f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_CONTEXT_STATUS_BASE_IDX 0 482f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_DOORBELL 0x019a 483f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_DOORBELL_BASE_IDX 0 484f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_DOORBELL_LOG 0x01b1 485f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_DOORBELL_LOG_BASE_IDX 0 486f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_DOORBELL_OFFSET 0x01b3 487f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_DOORBELL_OFFSET_BASE_IDX 0 488f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_CSA_ADDR_LO 0x01b4 489f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_CSA_ADDR_LO_BASE_IDX 0 490f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_CSA_ADDR_HI 0x01b5 491f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_CSA_ADDR_HI_BASE_IDX 0 492f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_SCHEDULE_CNTL 0x01b6 493f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_SCHEDULE_CNTL_BASE_IDX 0 494f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_IB_SUB_REMAIN 0x01b7 495f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_IB_SUB_REMAIN_BASE_IDX 0 496f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_PREEMPT 0x01b8 497f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_PREEMPT_BASE_IDX 0 498f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_DUMMY_REG 0x01b9 499f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_DUMMY_REG_BASE_IDX 0 500f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI 0x01ba 501f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 502f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO 0x01bb 503f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 504f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_RB_AQL_CNTL 0x01bc 505f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_RB_AQL_CNTL_BASE_IDX 0 506f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_MINOR_PTR_UPDATE 0x01bd 507f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX 0 508f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_RB_PREEMPT 0x01be 509f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_RB_PREEMPT_BASE_IDX 0 510f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_MIDCMD_DATA0 0x01c8 511f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_MIDCMD_DATA0_BASE_IDX 0 512f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_MIDCMD_DATA1 0x01c9 513f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_MIDCMD_DATA1_BASE_IDX 0 514f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_MIDCMD_DATA2 0x01ca 515f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_MIDCMD_DATA2_BASE_IDX 0 516f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_MIDCMD_DATA3 0x01cb 517f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_MIDCMD_DATA3_BASE_IDX 0 518f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_MIDCMD_DATA4 0x01cc 519f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_MIDCMD_DATA4_BASE_IDX 0 520f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_MIDCMD_DATA5 0x01cd 521f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_MIDCMD_DATA5_BASE_IDX 0 522f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_MIDCMD_DATA6 0x01ce 523f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_MIDCMD_DATA6_BASE_IDX 0 524f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_MIDCMD_DATA7 0x01cf 525f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_MIDCMD_DATA7_BASE_IDX 0 526f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_MIDCMD_DATA8 0x01d0 527f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_MIDCMD_DATA8_BASE_IDX 0 528f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_MIDCMD_DATA9 0x01d1 529f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_MIDCMD_DATA9_BASE_IDX 0 530f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_MIDCMD_DATA10 0x01d2 531f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_MIDCMD_DATA10_BASE_IDX 0 532f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_MIDCMD_CNTL 0x01d3 533f33ac92fSHawking Zhang #define regSDMA0_QUEUE3_MIDCMD_CNTL_BASE_IDX 0 534f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_RB_CNTL 0x01e0 535f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_RB_CNTL_BASE_IDX 0 536f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_RB_BASE 0x01e1 537f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_RB_BASE_BASE_IDX 0 538f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_RB_BASE_HI 0x01e2 539f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_RB_BASE_HI_BASE_IDX 0 540f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_RB_RPTR 0x01e3 541f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_RB_RPTR_BASE_IDX 0 542f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_RB_RPTR_HI 0x01e4 543f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_RB_RPTR_HI_BASE_IDX 0 544f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_RB_WPTR 0x01e5 545f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_RB_WPTR_BASE_IDX 0 546f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_RB_WPTR_HI 0x01e6 547f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_RB_WPTR_HI_BASE_IDX 0 548f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_RB_RPTR_ADDR_HI 0x01e8 549f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX 0 550f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_RB_RPTR_ADDR_LO 0x01e9 551f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX 0 552f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_IB_CNTL 0x01ea 553f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_IB_CNTL_BASE_IDX 0 554f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_IB_RPTR 0x01eb 555f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_IB_RPTR_BASE_IDX 0 556f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_IB_OFFSET 0x01ec 557f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_IB_OFFSET_BASE_IDX 0 558f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_IB_BASE_LO 0x01ed 559f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_IB_BASE_LO_BASE_IDX 0 560f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_IB_BASE_HI 0x01ee 561f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_IB_BASE_HI_BASE_IDX 0 562f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_IB_SIZE 0x01ef 563f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_IB_SIZE_BASE_IDX 0 564f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_SKIP_CNTL 0x01f0 565f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_SKIP_CNTL_BASE_IDX 0 566f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_CONTEXT_STATUS 0x01f1 567f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_CONTEXT_STATUS_BASE_IDX 0 568f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_DOORBELL 0x01f2 569f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_DOORBELL_BASE_IDX 0 570f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_DOORBELL_LOG 0x0209 571f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_DOORBELL_LOG_BASE_IDX 0 572f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_DOORBELL_OFFSET 0x020b 573f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_DOORBELL_OFFSET_BASE_IDX 0 574f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_CSA_ADDR_LO 0x020c 575f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_CSA_ADDR_LO_BASE_IDX 0 576f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_CSA_ADDR_HI 0x020d 577f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_CSA_ADDR_HI_BASE_IDX 0 578f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_SCHEDULE_CNTL 0x020e 579f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_SCHEDULE_CNTL_BASE_IDX 0 580f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_IB_SUB_REMAIN 0x020f 581f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_IB_SUB_REMAIN_BASE_IDX 0 582f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_PREEMPT 0x0210 583f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_PREEMPT_BASE_IDX 0 584f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_DUMMY_REG 0x0211 585f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_DUMMY_REG_BASE_IDX 0 586f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI 0x0212 587f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 588f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO 0x0213 589f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 590f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_RB_AQL_CNTL 0x0214 591f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_RB_AQL_CNTL_BASE_IDX 0 592f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_MINOR_PTR_UPDATE 0x0215 593f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX 0 594f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_RB_PREEMPT 0x0216 595f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_RB_PREEMPT_BASE_IDX 0 596f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_MIDCMD_DATA0 0x0220 597f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_MIDCMD_DATA0_BASE_IDX 0 598f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_MIDCMD_DATA1 0x0221 599f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_MIDCMD_DATA1_BASE_IDX 0 600f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_MIDCMD_DATA2 0x0222 601f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_MIDCMD_DATA2_BASE_IDX 0 602f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_MIDCMD_DATA3 0x0223 603f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_MIDCMD_DATA3_BASE_IDX 0 604f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_MIDCMD_DATA4 0x0224 605f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_MIDCMD_DATA4_BASE_IDX 0 606f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_MIDCMD_DATA5 0x0225 607f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_MIDCMD_DATA5_BASE_IDX 0 608f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_MIDCMD_DATA6 0x0226 609f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_MIDCMD_DATA6_BASE_IDX 0 610f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_MIDCMD_DATA7 0x0227 611f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_MIDCMD_DATA7_BASE_IDX 0 612f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_MIDCMD_DATA8 0x0228 613f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_MIDCMD_DATA8_BASE_IDX 0 614f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_MIDCMD_DATA9 0x0229 615f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_MIDCMD_DATA9_BASE_IDX 0 616f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_MIDCMD_DATA10 0x022a 617f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_MIDCMD_DATA10_BASE_IDX 0 618f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_MIDCMD_CNTL 0x022b 619f33ac92fSHawking Zhang #define regSDMA0_QUEUE4_MIDCMD_CNTL_BASE_IDX 0 620f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_RB_CNTL 0x0238 621f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_RB_CNTL_BASE_IDX 0 622f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_RB_BASE 0x0239 623f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_RB_BASE_BASE_IDX 0 624f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_RB_BASE_HI 0x023a 625f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_RB_BASE_HI_BASE_IDX 0 626f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_RB_RPTR 0x023b 627f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_RB_RPTR_BASE_IDX 0 628f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_RB_RPTR_HI 0x023c 629f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_RB_RPTR_HI_BASE_IDX 0 630f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_RB_WPTR 0x023d 631f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_RB_WPTR_BASE_IDX 0 632f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_RB_WPTR_HI 0x023e 633f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_RB_WPTR_HI_BASE_IDX 0 634f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_RB_RPTR_ADDR_HI 0x0240 635f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX 0 636f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_RB_RPTR_ADDR_LO 0x0241 637f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX 0 638f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_IB_CNTL 0x0242 639f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_IB_CNTL_BASE_IDX 0 640f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_IB_RPTR 0x0243 641f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_IB_RPTR_BASE_IDX 0 642f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_IB_OFFSET 0x0244 643f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_IB_OFFSET_BASE_IDX 0 644f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_IB_BASE_LO 0x0245 645f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_IB_BASE_LO_BASE_IDX 0 646f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_IB_BASE_HI 0x0246 647f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_IB_BASE_HI_BASE_IDX 0 648f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_IB_SIZE 0x0247 649f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_IB_SIZE_BASE_IDX 0 650f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_SKIP_CNTL 0x0248 651f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_SKIP_CNTL_BASE_IDX 0 652f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_CONTEXT_STATUS 0x0249 653f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_CONTEXT_STATUS_BASE_IDX 0 654f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_DOORBELL 0x024a 655f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_DOORBELL_BASE_IDX 0 656f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_DOORBELL_LOG 0x0261 657f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_DOORBELL_LOG_BASE_IDX 0 658f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_DOORBELL_OFFSET 0x0263 659f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_DOORBELL_OFFSET_BASE_IDX 0 660f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_CSA_ADDR_LO 0x0264 661f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_CSA_ADDR_LO_BASE_IDX 0 662f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_CSA_ADDR_HI 0x0265 663f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_CSA_ADDR_HI_BASE_IDX 0 664f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_SCHEDULE_CNTL 0x0266 665f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_SCHEDULE_CNTL_BASE_IDX 0 666f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_IB_SUB_REMAIN 0x0267 667f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_IB_SUB_REMAIN_BASE_IDX 0 668f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_PREEMPT 0x0268 669f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_PREEMPT_BASE_IDX 0 670f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_DUMMY_REG 0x0269 671f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_DUMMY_REG_BASE_IDX 0 672f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI 0x026a 673f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 674f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO 0x026b 675f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 676f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_RB_AQL_CNTL 0x026c 677f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_RB_AQL_CNTL_BASE_IDX 0 678f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_MINOR_PTR_UPDATE 0x026d 679f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX 0 680f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_RB_PREEMPT 0x026e 681f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_RB_PREEMPT_BASE_IDX 0 682f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_MIDCMD_DATA0 0x0278 683f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_MIDCMD_DATA0_BASE_IDX 0 684f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_MIDCMD_DATA1 0x0279 685f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_MIDCMD_DATA1_BASE_IDX 0 686f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_MIDCMD_DATA2 0x027a 687f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_MIDCMD_DATA2_BASE_IDX 0 688f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_MIDCMD_DATA3 0x027b 689f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_MIDCMD_DATA3_BASE_IDX 0 690f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_MIDCMD_DATA4 0x027c 691f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_MIDCMD_DATA4_BASE_IDX 0 692f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_MIDCMD_DATA5 0x027d 693f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_MIDCMD_DATA5_BASE_IDX 0 694f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_MIDCMD_DATA6 0x027e 695f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_MIDCMD_DATA6_BASE_IDX 0 696f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_MIDCMD_DATA7 0x027f 697f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_MIDCMD_DATA7_BASE_IDX 0 698f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_MIDCMD_DATA8 0x0280 699f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_MIDCMD_DATA8_BASE_IDX 0 700f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_MIDCMD_DATA9 0x0281 701f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_MIDCMD_DATA9_BASE_IDX 0 702f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_MIDCMD_DATA10 0x0282 703f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_MIDCMD_DATA10_BASE_IDX 0 704f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_MIDCMD_CNTL 0x0283 705f33ac92fSHawking Zhang #define regSDMA0_QUEUE5_MIDCMD_CNTL_BASE_IDX 0 706f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_RB_CNTL 0x0290 707f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_RB_CNTL_BASE_IDX 0 708f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_RB_BASE 0x0291 709f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_RB_BASE_BASE_IDX 0 710f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_RB_BASE_HI 0x0292 711f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_RB_BASE_HI_BASE_IDX 0 712f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_RB_RPTR 0x0293 713f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_RB_RPTR_BASE_IDX 0 714f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_RB_RPTR_HI 0x0294 715f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_RB_RPTR_HI_BASE_IDX 0 716f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_RB_WPTR 0x0295 717f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_RB_WPTR_BASE_IDX 0 718f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_RB_WPTR_HI 0x0296 719f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_RB_WPTR_HI_BASE_IDX 0 720f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_RB_RPTR_ADDR_HI 0x0298 721f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX 0 722f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_RB_RPTR_ADDR_LO 0x0299 723f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX 0 724f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_IB_CNTL 0x029a 725f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_IB_CNTL_BASE_IDX 0 726f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_IB_RPTR 0x029b 727f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_IB_RPTR_BASE_IDX 0 728f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_IB_OFFSET 0x029c 729f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_IB_OFFSET_BASE_IDX 0 730f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_IB_BASE_LO 0x029d 731f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_IB_BASE_LO_BASE_IDX 0 732f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_IB_BASE_HI 0x029e 733f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_IB_BASE_HI_BASE_IDX 0 734f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_IB_SIZE 0x029f 735f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_IB_SIZE_BASE_IDX 0 736f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_SKIP_CNTL 0x02a0 737f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_SKIP_CNTL_BASE_IDX 0 738f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_CONTEXT_STATUS 0x02a1 739f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_CONTEXT_STATUS_BASE_IDX 0 740f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_DOORBELL 0x02a2 741f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_DOORBELL_BASE_IDX 0 742f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_DOORBELL_LOG 0x02b9 743f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_DOORBELL_LOG_BASE_IDX 0 744f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_DOORBELL_OFFSET 0x02bb 745f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_DOORBELL_OFFSET_BASE_IDX 0 746f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_CSA_ADDR_LO 0x02bc 747f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_CSA_ADDR_LO_BASE_IDX 0 748f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_CSA_ADDR_HI 0x02bd 749f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_CSA_ADDR_HI_BASE_IDX 0 750f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_SCHEDULE_CNTL 0x02be 751f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_SCHEDULE_CNTL_BASE_IDX 0 752f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_IB_SUB_REMAIN 0x02bf 753f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_IB_SUB_REMAIN_BASE_IDX 0 754f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_PREEMPT 0x02c0 755f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_PREEMPT_BASE_IDX 0 756f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_DUMMY_REG 0x02c1 757f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_DUMMY_REG_BASE_IDX 0 758f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI 0x02c2 759f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 760f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO 0x02c3 761f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 762f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_RB_AQL_CNTL 0x02c4 763f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_RB_AQL_CNTL_BASE_IDX 0 764f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_MINOR_PTR_UPDATE 0x02c5 765f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX 0 766f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_RB_PREEMPT 0x02c6 767f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_RB_PREEMPT_BASE_IDX 0 768f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_MIDCMD_DATA0 0x02d0 769f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_MIDCMD_DATA0_BASE_IDX 0 770f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_MIDCMD_DATA1 0x02d1 771f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_MIDCMD_DATA1_BASE_IDX 0 772f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_MIDCMD_DATA2 0x02d2 773f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_MIDCMD_DATA2_BASE_IDX 0 774f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_MIDCMD_DATA3 0x02d3 775f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_MIDCMD_DATA3_BASE_IDX 0 776f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_MIDCMD_DATA4 0x02d4 777f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_MIDCMD_DATA4_BASE_IDX 0 778f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_MIDCMD_DATA5 0x02d5 779f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_MIDCMD_DATA5_BASE_IDX 0 780f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_MIDCMD_DATA6 0x02d6 781f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_MIDCMD_DATA6_BASE_IDX 0 782f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_MIDCMD_DATA7 0x02d7 783f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_MIDCMD_DATA7_BASE_IDX 0 784f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_MIDCMD_DATA8 0x02d8 785f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_MIDCMD_DATA8_BASE_IDX 0 786f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_MIDCMD_DATA9 0x02d9 787f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_MIDCMD_DATA9_BASE_IDX 0 788f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_MIDCMD_DATA10 0x02da 789f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_MIDCMD_DATA10_BASE_IDX 0 790f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_MIDCMD_CNTL 0x02db 791f33ac92fSHawking Zhang #define regSDMA0_QUEUE6_MIDCMD_CNTL_BASE_IDX 0 792f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_RB_CNTL 0x02e8 793f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_RB_CNTL_BASE_IDX 0 794f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_RB_BASE 0x02e9 795f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_RB_BASE_BASE_IDX 0 796f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_RB_BASE_HI 0x02ea 797f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_RB_BASE_HI_BASE_IDX 0 798f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_RB_RPTR 0x02eb 799f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_RB_RPTR_BASE_IDX 0 800f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_RB_RPTR_HI 0x02ec 801f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_RB_RPTR_HI_BASE_IDX 0 802f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_RB_WPTR 0x02ed 803f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_RB_WPTR_BASE_IDX 0 804f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_RB_WPTR_HI 0x02ee 805f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_RB_WPTR_HI_BASE_IDX 0 806f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_RB_RPTR_ADDR_HI 0x02f0 807f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX 0 808f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_RB_RPTR_ADDR_LO 0x02f1 809f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX 0 810f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_IB_CNTL 0x02f2 811f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_IB_CNTL_BASE_IDX 0 812f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_IB_RPTR 0x02f3 813f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_IB_RPTR_BASE_IDX 0 814f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_IB_OFFSET 0x02f4 815f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_IB_OFFSET_BASE_IDX 0 816f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_IB_BASE_LO 0x02f5 817f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_IB_BASE_LO_BASE_IDX 0 818f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_IB_BASE_HI 0x02f6 819f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_IB_BASE_HI_BASE_IDX 0 820f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_IB_SIZE 0x02f7 821f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_IB_SIZE_BASE_IDX 0 822f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_SKIP_CNTL 0x02f8 823f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_SKIP_CNTL_BASE_IDX 0 824f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_CONTEXT_STATUS 0x02f9 825f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_CONTEXT_STATUS_BASE_IDX 0 826f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_DOORBELL 0x02fa 827f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_DOORBELL_BASE_IDX 0 828f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_DOORBELL_LOG 0x0311 829f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_DOORBELL_LOG_BASE_IDX 0 830f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_DOORBELL_OFFSET 0x0313 831f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_DOORBELL_OFFSET_BASE_IDX 0 832f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_CSA_ADDR_LO 0x0314 833f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_CSA_ADDR_LO_BASE_IDX 0 834f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_CSA_ADDR_HI 0x0315 835f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_CSA_ADDR_HI_BASE_IDX 0 836f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_SCHEDULE_CNTL 0x0316 837f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_SCHEDULE_CNTL_BASE_IDX 0 838f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_IB_SUB_REMAIN 0x0317 839f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_IB_SUB_REMAIN_BASE_IDX 0 840f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_PREEMPT 0x0318 841f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_PREEMPT_BASE_IDX 0 842f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_DUMMY_REG 0x0319 843f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_DUMMY_REG_BASE_IDX 0 844f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI 0x031a 845f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 846f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO 0x031b 847f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 848f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_RB_AQL_CNTL 0x031c 849f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_RB_AQL_CNTL_BASE_IDX 0 850f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_MINOR_PTR_UPDATE 0x031d 851f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX 0 852f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_RB_PREEMPT 0x031e 853f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_RB_PREEMPT_BASE_IDX 0 854f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_MIDCMD_DATA0 0x0328 855f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_MIDCMD_DATA0_BASE_IDX 0 856f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_MIDCMD_DATA1 0x0329 857f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_MIDCMD_DATA1_BASE_IDX 0 858f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_MIDCMD_DATA2 0x032a 859f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_MIDCMD_DATA2_BASE_IDX 0 860f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_MIDCMD_DATA3 0x032b 861f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_MIDCMD_DATA3_BASE_IDX 0 862f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_MIDCMD_DATA4 0x032c 863f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_MIDCMD_DATA4_BASE_IDX 0 864f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_MIDCMD_DATA5 0x032d 865f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_MIDCMD_DATA5_BASE_IDX 0 866f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_MIDCMD_DATA6 0x032e 867f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_MIDCMD_DATA6_BASE_IDX 0 868f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_MIDCMD_DATA7 0x032f 869f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_MIDCMD_DATA7_BASE_IDX 0 870f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_MIDCMD_DATA8 0x0330 871f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_MIDCMD_DATA8_BASE_IDX 0 872f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_MIDCMD_DATA9 0x0331 873f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_MIDCMD_DATA9_BASE_IDX 0 874f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_MIDCMD_DATA10 0x0332 875f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_MIDCMD_DATA10_BASE_IDX 0 876f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_MIDCMD_CNTL 0x0333 877f33ac92fSHawking Zhang #define regSDMA0_QUEUE7_MIDCMD_CNTL_BASE_IDX 0 878f33ac92fSHawking Zhang 879f33ac92fSHawking Zhang 880f33ac92fSHawking Zhang // addressBlock: gc_sdma0_sdma1dec 881f33ac92fSHawking Zhang // base address: 0x6180 882f33ac92fSHawking Zhang #define regSDMA1_DEC_START 0x0600 883f33ac92fSHawking Zhang #define regSDMA1_DEC_START_BASE_IDX 0 884f33ac92fSHawking Zhang #define regSDMA1_F32_MISC_CNTL 0x060b 885f33ac92fSHawking Zhang #define regSDMA1_F32_MISC_CNTL_BASE_IDX 0 886f33ac92fSHawking Zhang #define regSDMA1_GLOBAL_TIMESTAMP_LO 0x060f 887f33ac92fSHawking Zhang #define regSDMA1_GLOBAL_TIMESTAMP_LO_BASE_IDX 0 888f33ac92fSHawking Zhang #define regSDMA1_GLOBAL_TIMESTAMP_HI 0x0610 889f33ac92fSHawking Zhang #define regSDMA1_GLOBAL_TIMESTAMP_HI_BASE_IDX 0 890f33ac92fSHawking Zhang #define regSDMA1_POWER_CNTL 0x061a 891f33ac92fSHawking Zhang #define regSDMA1_POWER_CNTL_BASE_IDX 0 892f33ac92fSHawking Zhang #define regSDMA1_CNTL 0x061c 893f33ac92fSHawking Zhang #define regSDMA1_CNTL_BASE_IDX 0 894f33ac92fSHawking Zhang #define regSDMA1_CHICKEN_BITS 0x061d 895f33ac92fSHawking Zhang #define regSDMA1_CHICKEN_BITS_BASE_IDX 0 896f33ac92fSHawking Zhang #define regSDMA1_GB_ADDR_CONFIG 0x061e 897f33ac92fSHawking Zhang #define regSDMA1_GB_ADDR_CONFIG_BASE_IDX 0 898f33ac92fSHawking Zhang #define regSDMA1_GB_ADDR_CONFIG_READ 0x061f 899f33ac92fSHawking Zhang #define regSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX 0 900f33ac92fSHawking Zhang #define regSDMA1_RB_RPTR_FETCH 0x0620 901f33ac92fSHawking Zhang #define regSDMA1_RB_RPTR_FETCH_BASE_IDX 0 902f33ac92fSHawking Zhang #define regSDMA1_RB_RPTR_FETCH_HI 0x0621 903f33ac92fSHawking Zhang #define regSDMA1_RB_RPTR_FETCH_HI_BASE_IDX 0 904f33ac92fSHawking Zhang #define regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x0622 905f33ac92fSHawking Zhang #define regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 906f33ac92fSHawking Zhang #define regSDMA1_IB_OFFSET_FETCH 0x0623 907f33ac92fSHawking Zhang #define regSDMA1_IB_OFFSET_FETCH_BASE_IDX 0 908f33ac92fSHawking Zhang #define regSDMA1_PROGRAM 0x0624 909f33ac92fSHawking Zhang #define regSDMA1_PROGRAM_BASE_IDX 0 910f33ac92fSHawking Zhang #define regSDMA1_STATUS_REG 0x0625 911f33ac92fSHawking Zhang #define regSDMA1_STATUS_REG_BASE_IDX 0 912f33ac92fSHawking Zhang #define regSDMA1_STATUS1_REG 0x0626 913f33ac92fSHawking Zhang #define regSDMA1_STATUS1_REG_BASE_IDX 0 914f33ac92fSHawking Zhang #define regSDMA1_CNTL1 0x0627 915f33ac92fSHawking Zhang #define regSDMA1_CNTL1_BASE_IDX 0 916f33ac92fSHawking Zhang #define regSDMA1_HBM_PAGE_CONFIG 0x0628 917f33ac92fSHawking Zhang #define regSDMA1_HBM_PAGE_CONFIG_BASE_IDX 0 918f33ac92fSHawking Zhang #define regSDMA1_UCODE_CHECKSUM 0x0629 919f33ac92fSHawking Zhang #define regSDMA1_UCODE_CHECKSUM_BASE_IDX 0 920f33ac92fSHawking Zhang #define regSDMA1_FREEZE 0x062b 921f33ac92fSHawking Zhang #define regSDMA1_FREEZE_BASE_IDX 0 922f33ac92fSHawking Zhang #define regSDMA1_PROCESS_QUANTUM0 0x062c 923f33ac92fSHawking Zhang #define regSDMA1_PROCESS_QUANTUM0_BASE_IDX 0 924f33ac92fSHawking Zhang #define regSDMA1_PROCESS_QUANTUM1 0x062d 925f33ac92fSHawking Zhang #define regSDMA1_PROCESS_QUANTUM1_BASE_IDX 0 926f33ac92fSHawking Zhang #define regSDMA1_WATCHDOG_CNTL 0x062e 927f33ac92fSHawking Zhang #define regSDMA1_WATCHDOG_CNTL_BASE_IDX 0 928f33ac92fSHawking Zhang #define regSDMA1_QUEUE_STATUS0 0x062f 929f33ac92fSHawking Zhang #define regSDMA1_QUEUE_STATUS0_BASE_IDX 0 930f33ac92fSHawking Zhang #define regSDMA1_EDC_CONFIG 0x0632 931f33ac92fSHawking Zhang #define regSDMA1_EDC_CONFIG_BASE_IDX 0 932f33ac92fSHawking Zhang #define regSDMA1_BA_THRESHOLD 0x0633 933f33ac92fSHawking Zhang #define regSDMA1_BA_THRESHOLD_BASE_IDX 0 934f33ac92fSHawking Zhang #define regSDMA1_ID 0x0634 935f33ac92fSHawking Zhang #define regSDMA1_ID_BASE_IDX 0 936f33ac92fSHawking Zhang #define regSDMA1_VERSION 0x0635 937f33ac92fSHawking Zhang #define regSDMA1_VERSION_BASE_IDX 0 938f33ac92fSHawking Zhang #define regSDMA1_EDC_COUNTER 0x0636 939f33ac92fSHawking Zhang #define regSDMA1_EDC_COUNTER_BASE_IDX 0 940f33ac92fSHawking Zhang #define regSDMA1_EDC_COUNTER_CLEAR 0x0637 941f33ac92fSHawking Zhang #define regSDMA1_EDC_COUNTER_CLEAR_BASE_IDX 0 942f33ac92fSHawking Zhang #define regSDMA1_STATUS2_REG 0x0638 943f33ac92fSHawking Zhang #define regSDMA1_STATUS2_REG_BASE_IDX 0 944f33ac92fSHawking Zhang #define regSDMA1_ATOMIC_CNTL 0x0639 945f33ac92fSHawking Zhang #define regSDMA1_ATOMIC_CNTL_BASE_IDX 0 946f33ac92fSHawking Zhang #define regSDMA1_ATOMIC_PREOP_LO 0x063a 947f33ac92fSHawking Zhang #define regSDMA1_ATOMIC_PREOP_LO_BASE_IDX 0 948f33ac92fSHawking Zhang #define regSDMA1_ATOMIC_PREOP_HI 0x063b 949f33ac92fSHawking Zhang #define regSDMA1_ATOMIC_PREOP_HI_BASE_IDX 0 950f33ac92fSHawking Zhang #define regSDMA1_UTCL1_CNTL 0x063c 951f33ac92fSHawking Zhang #define regSDMA1_UTCL1_CNTL_BASE_IDX 0 952f33ac92fSHawking Zhang #define regSDMA1_UTCL1_WATERMK 0x063d 953f33ac92fSHawking Zhang #define regSDMA1_UTCL1_WATERMK_BASE_IDX 0 954f33ac92fSHawking Zhang #define regSDMA1_UTCL1_TIMEOUT 0x063e 955f33ac92fSHawking Zhang #define regSDMA1_UTCL1_TIMEOUT_BASE_IDX 0 956f33ac92fSHawking Zhang #define regSDMA1_UTCL1_PAGE 0x063f 957f33ac92fSHawking Zhang #define regSDMA1_UTCL1_PAGE_BASE_IDX 0 958f33ac92fSHawking Zhang #define regSDMA1_UTCL1_RD_STATUS 0x0640 959f33ac92fSHawking Zhang #define regSDMA1_UTCL1_RD_STATUS_BASE_IDX 0 960f33ac92fSHawking Zhang #define regSDMA1_UTCL1_WR_STATUS 0x0641 961f33ac92fSHawking Zhang #define regSDMA1_UTCL1_WR_STATUS_BASE_IDX 0 962f33ac92fSHawking Zhang #define regSDMA1_UTCL1_INV0 0x0642 963f33ac92fSHawking Zhang #define regSDMA1_UTCL1_INV0_BASE_IDX 0 964f33ac92fSHawking Zhang #define regSDMA1_UTCL1_INV1 0x0643 965f33ac92fSHawking Zhang #define regSDMA1_UTCL1_INV1_BASE_IDX 0 966f33ac92fSHawking Zhang #define regSDMA1_UTCL1_INV2 0x0644 967f33ac92fSHawking Zhang #define regSDMA1_UTCL1_INV2_BASE_IDX 0 968f33ac92fSHawking Zhang #define regSDMA1_UTCL1_RD_XNACK0 0x0645 969f33ac92fSHawking Zhang #define regSDMA1_UTCL1_RD_XNACK0_BASE_IDX 0 970f33ac92fSHawking Zhang #define regSDMA1_UTCL1_RD_XNACK1 0x0646 971f33ac92fSHawking Zhang #define regSDMA1_UTCL1_RD_XNACK1_BASE_IDX 0 972f33ac92fSHawking Zhang #define regSDMA1_UTCL1_WR_XNACK0 0x0647 973f33ac92fSHawking Zhang #define regSDMA1_UTCL1_WR_XNACK0_BASE_IDX 0 974f33ac92fSHawking Zhang #define regSDMA1_UTCL1_WR_XNACK1 0x0648 975f33ac92fSHawking Zhang #define regSDMA1_UTCL1_WR_XNACK1_BASE_IDX 0 976f33ac92fSHawking Zhang #define regSDMA1_RELAX_ORDERING_LUT 0x064a 977f33ac92fSHawking Zhang #define regSDMA1_RELAX_ORDERING_LUT_BASE_IDX 0 978f33ac92fSHawking Zhang #define regSDMA1_CHICKEN_BITS_2 0x064b 979f33ac92fSHawking Zhang #define regSDMA1_CHICKEN_BITS_2_BASE_IDX 0 980f33ac92fSHawking Zhang #define regSDMA1_STATUS3_REG 0x064c 981f33ac92fSHawking Zhang #define regSDMA1_STATUS3_REG_BASE_IDX 0 982f33ac92fSHawking Zhang #define regSDMA1_PHYSICAL_ADDR_LO 0x064d 983f33ac92fSHawking Zhang #define regSDMA1_PHYSICAL_ADDR_LO_BASE_IDX 0 984f33ac92fSHawking Zhang #define regSDMA1_PHYSICAL_ADDR_HI 0x064e 985f33ac92fSHawking Zhang #define regSDMA1_PHYSICAL_ADDR_HI_BASE_IDX 0 986f33ac92fSHawking Zhang #define regSDMA1_GLOBAL_QUANTUM 0x064f 987f33ac92fSHawking Zhang #define regSDMA1_GLOBAL_QUANTUM_BASE_IDX 0 988f33ac92fSHawking Zhang #define regSDMA1_ERROR_LOG 0x0650 989f33ac92fSHawking Zhang #define regSDMA1_ERROR_LOG_BASE_IDX 0 990f33ac92fSHawking Zhang #define regSDMA1_PUB_DUMMY_REG0 0x0651 991f33ac92fSHawking Zhang #define regSDMA1_PUB_DUMMY_REG0_BASE_IDX 0 992f33ac92fSHawking Zhang #define regSDMA1_PUB_DUMMY_REG1 0x0652 993f33ac92fSHawking Zhang #define regSDMA1_PUB_DUMMY_REG1_BASE_IDX 0 994f33ac92fSHawking Zhang #define regSDMA1_PUB_DUMMY_REG2 0x0653 995f33ac92fSHawking Zhang #define regSDMA1_PUB_DUMMY_REG2_BASE_IDX 0 996f33ac92fSHawking Zhang #define regSDMA1_PUB_DUMMY_REG3 0x0654 997f33ac92fSHawking Zhang #define regSDMA1_PUB_DUMMY_REG3_BASE_IDX 0 998f33ac92fSHawking Zhang #define regSDMA1_F32_COUNTER 0x0655 999f33ac92fSHawking Zhang #define regSDMA1_F32_COUNTER_BASE_IDX 0 1000f33ac92fSHawking Zhang #define regSDMA1_CRD_CNTL 0x065b 1001f33ac92fSHawking Zhang #define regSDMA1_CRD_CNTL_BASE_IDX 0 1002f33ac92fSHawking Zhang #define regSDMA1_RLC_CGCG_CTRL 0x065c 1003f33ac92fSHawking Zhang #define regSDMA1_RLC_CGCG_CTRL_BASE_IDX 0 1004f33ac92fSHawking Zhang #define regSDMA1_AQL_STATUS 0x065f 1005f33ac92fSHawking Zhang #define regSDMA1_AQL_STATUS_BASE_IDX 0 1006f33ac92fSHawking Zhang #define regSDMA1_EA_DBIT_ADDR_DATA 0x0660 1007f33ac92fSHawking Zhang #define regSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX 0 1008f33ac92fSHawking Zhang #define regSDMA1_EA_DBIT_ADDR_INDEX 0x0661 1009f33ac92fSHawking Zhang #define regSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX 0 1010f33ac92fSHawking Zhang #define regSDMA1_TLBI_GCR_CNTL 0x0662 1011f33ac92fSHawking Zhang #define regSDMA1_TLBI_GCR_CNTL_BASE_IDX 0 1012f33ac92fSHawking Zhang #define regSDMA1_TILING_CONFIG 0x0663 1013f33ac92fSHawking Zhang #define regSDMA1_TILING_CONFIG_BASE_IDX 0 1014f33ac92fSHawking Zhang #define regSDMA1_INT_STATUS 0x0670 1015f33ac92fSHawking Zhang #define regSDMA1_INT_STATUS_BASE_IDX 0 1016f33ac92fSHawking Zhang #define regSDMA1_HOLE_ADDR_LO 0x0672 1017f33ac92fSHawking Zhang #define regSDMA1_HOLE_ADDR_LO_BASE_IDX 0 1018f33ac92fSHawking Zhang #define regSDMA1_HOLE_ADDR_HI 0x0673 1019f33ac92fSHawking Zhang #define regSDMA1_HOLE_ADDR_HI_BASE_IDX 0 1020f33ac92fSHawking Zhang #define regSDMA1_CLOCK_GATING_STATUS 0x0675 1021f33ac92fSHawking Zhang #define regSDMA1_CLOCK_GATING_STATUS_BASE_IDX 0 1022f33ac92fSHawking Zhang #define regSDMA1_STATUS4_REG 0x0676 1023f33ac92fSHawking Zhang #define regSDMA1_STATUS4_REG_BASE_IDX 0 1024f33ac92fSHawking Zhang #define regSDMA1_SCRATCH_RAM_DATA 0x0677 1025f33ac92fSHawking Zhang #define regSDMA1_SCRATCH_RAM_DATA_BASE_IDX 0 1026f33ac92fSHawking Zhang #define regSDMA1_SCRATCH_RAM_ADDR 0x0678 1027f33ac92fSHawking Zhang #define regSDMA1_SCRATCH_RAM_ADDR_BASE_IDX 0 1028f33ac92fSHawking Zhang #define regSDMA1_TIMESTAMP_CNTL 0x0679 1029f33ac92fSHawking Zhang #define regSDMA1_TIMESTAMP_CNTL_BASE_IDX 0 1030f33ac92fSHawking Zhang #define regSDMA1_STATUS5_REG 0x067a 1031f33ac92fSHawking Zhang #define regSDMA1_STATUS5_REG_BASE_IDX 0 1032f33ac92fSHawking Zhang #define regSDMA1_QUEUE_RESET_REQ 0x067b 1033f33ac92fSHawking Zhang #define regSDMA1_QUEUE_RESET_REQ_BASE_IDX 0 1034f33ac92fSHawking Zhang #define regSDMA1_STATUS6_REG 0x067c 1035f33ac92fSHawking Zhang #define regSDMA1_STATUS6_REG_BASE_IDX 0 1036f33ac92fSHawking Zhang #define regSDMA1_UCODE1_CHECKSUM 0x067d 1037f33ac92fSHawking Zhang #define regSDMA1_UCODE1_CHECKSUM_BASE_IDX 0 1038f33ac92fSHawking Zhang #define regSDMA1_CE_CTRL 0x067e 1039f33ac92fSHawking Zhang #define regSDMA1_CE_CTRL_BASE_IDX 0 1040f33ac92fSHawking Zhang #define regSDMA1_FED_STATUS 0x067f 1041f33ac92fSHawking Zhang #define regSDMA1_FED_STATUS_BASE_IDX 0 1042f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_RB_CNTL 0x0680 1043f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_RB_CNTL_BASE_IDX 0 1044f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_RB_BASE 0x0681 1045f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_RB_BASE_BASE_IDX 0 1046f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_RB_BASE_HI 0x0682 1047f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_RB_BASE_HI_BASE_IDX 0 1048f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_RB_RPTR 0x0683 1049f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_RB_RPTR_BASE_IDX 0 1050f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_RB_RPTR_HI 0x0684 1051f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_RB_RPTR_HI_BASE_IDX 0 1052f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_RB_WPTR 0x0685 1053f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_RB_WPTR_BASE_IDX 0 1054f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_RB_WPTR_HI 0x0686 1055f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_RB_WPTR_HI_BASE_IDX 0 1056f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_RB_RPTR_ADDR_HI 0x0688 1057f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX 0 1058f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_RB_RPTR_ADDR_LO 0x0689 1059f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX 0 1060f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_IB_CNTL 0x068a 1061f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_IB_CNTL_BASE_IDX 0 1062f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_IB_RPTR 0x068b 1063f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_IB_RPTR_BASE_IDX 0 1064f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_IB_OFFSET 0x068c 1065f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_IB_OFFSET_BASE_IDX 0 1066f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_IB_BASE_LO 0x068d 1067f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_IB_BASE_LO_BASE_IDX 0 1068f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_IB_BASE_HI 0x068e 1069f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_IB_BASE_HI_BASE_IDX 0 1070f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_IB_SIZE 0x068f 1071f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_IB_SIZE_BASE_IDX 0 1072f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_SKIP_CNTL 0x0690 1073f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_SKIP_CNTL_BASE_IDX 0 1074f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_CONTEXT_STATUS 0x0691 1075f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_CONTEXT_STATUS_BASE_IDX 0 1076f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_DOORBELL 0x0692 1077f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_DOORBELL_BASE_IDX 0 1078f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_DOORBELL_LOG 0x06a9 1079f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_DOORBELL_LOG_BASE_IDX 0 1080f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_DOORBELL_OFFSET 0x06ab 1081f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_DOORBELL_OFFSET_BASE_IDX 0 1082f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_CSA_ADDR_LO 0x06ac 1083f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_CSA_ADDR_LO_BASE_IDX 0 1084f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_CSA_ADDR_HI 0x06ad 1085f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_CSA_ADDR_HI_BASE_IDX 0 1086f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_SCHEDULE_CNTL 0x06ae 1087f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_SCHEDULE_CNTL_BASE_IDX 0 1088f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_IB_SUB_REMAIN 0x06af 1089f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_IB_SUB_REMAIN_BASE_IDX 0 1090f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_PREEMPT 0x06b0 1091f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_PREEMPT_BASE_IDX 0 1092f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_DUMMY_REG 0x06b1 1093f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_DUMMY_REG_BASE_IDX 0 1094f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI 0x06b2 1095f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 1096f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO 0x06b3 1097f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 1098f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_RB_AQL_CNTL 0x06b4 1099f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_RB_AQL_CNTL_BASE_IDX 0 1100f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_MINOR_PTR_UPDATE 0x06b5 1101f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX 0 1102f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_RB_PREEMPT 0x06b6 1103f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_RB_PREEMPT_BASE_IDX 0 1104f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_MIDCMD_DATA0 0x06c0 1105f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_MIDCMD_DATA0_BASE_IDX 0 1106f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_MIDCMD_DATA1 0x06c1 1107f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_MIDCMD_DATA1_BASE_IDX 0 1108f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_MIDCMD_DATA2 0x06c2 1109f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_MIDCMD_DATA2_BASE_IDX 0 1110f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_MIDCMD_DATA3 0x06c3 1111f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_MIDCMD_DATA3_BASE_IDX 0 1112f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_MIDCMD_DATA4 0x06c4 1113f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_MIDCMD_DATA4_BASE_IDX 0 1114f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_MIDCMD_DATA5 0x06c5 1115f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_MIDCMD_DATA5_BASE_IDX 0 1116f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_MIDCMD_DATA6 0x06c6 1117f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_MIDCMD_DATA6_BASE_IDX 0 1118f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_MIDCMD_DATA7 0x06c7 1119f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_MIDCMD_DATA7_BASE_IDX 0 1120f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_MIDCMD_DATA8 0x06c8 1121f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_MIDCMD_DATA8_BASE_IDX 0 1122f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_MIDCMD_DATA9 0x06c9 1123f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_MIDCMD_DATA9_BASE_IDX 0 1124f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_MIDCMD_DATA10 0x06ca 1125f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_MIDCMD_DATA10_BASE_IDX 0 1126f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_MIDCMD_CNTL 0x06cb 1127f33ac92fSHawking Zhang #define regSDMA1_QUEUE0_MIDCMD_CNTL_BASE_IDX 0 1128f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_RB_CNTL 0x06d8 1129f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_RB_CNTL_BASE_IDX 0 1130f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_RB_BASE 0x06d9 1131f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_RB_BASE_BASE_IDX 0 1132f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_RB_BASE_HI 0x06da 1133f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_RB_BASE_HI_BASE_IDX 0 1134f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_RB_RPTR 0x06db 1135f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_RB_RPTR_BASE_IDX 0 1136f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_RB_RPTR_HI 0x06dc 1137f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_RB_RPTR_HI_BASE_IDX 0 1138f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_RB_WPTR 0x06dd 1139f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_RB_WPTR_BASE_IDX 0 1140f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_RB_WPTR_HI 0x06de 1141f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_RB_WPTR_HI_BASE_IDX 0 1142f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_RB_RPTR_ADDR_HI 0x06e0 1143f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX 0 1144f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_RB_RPTR_ADDR_LO 0x06e1 1145f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX 0 1146f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_IB_CNTL 0x06e2 1147f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_IB_CNTL_BASE_IDX 0 1148f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_IB_RPTR 0x06e3 1149f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_IB_RPTR_BASE_IDX 0 1150f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_IB_OFFSET 0x06e4 1151f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_IB_OFFSET_BASE_IDX 0 1152f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_IB_BASE_LO 0x06e5 1153f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_IB_BASE_LO_BASE_IDX 0 1154f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_IB_BASE_HI 0x06e6 1155f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_IB_BASE_HI_BASE_IDX 0 1156f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_IB_SIZE 0x06e7 1157f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_IB_SIZE_BASE_IDX 0 1158f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_SKIP_CNTL 0x06e8 1159f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_SKIP_CNTL_BASE_IDX 0 1160f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_CONTEXT_STATUS 0x06e9 1161f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_CONTEXT_STATUS_BASE_IDX 0 1162f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_DOORBELL 0x06ea 1163f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_DOORBELL_BASE_IDX 0 1164f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_DOORBELL_LOG 0x0701 1165f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_DOORBELL_LOG_BASE_IDX 0 1166f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_DOORBELL_OFFSET 0x0703 1167f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_DOORBELL_OFFSET_BASE_IDX 0 1168f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_CSA_ADDR_LO 0x0704 1169f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_CSA_ADDR_LO_BASE_IDX 0 1170f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_CSA_ADDR_HI 0x0705 1171f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_CSA_ADDR_HI_BASE_IDX 0 1172f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_SCHEDULE_CNTL 0x0706 1173f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_SCHEDULE_CNTL_BASE_IDX 0 1174f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_IB_SUB_REMAIN 0x0707 1175f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_IB_SUB_REMAIN_BASE_IDX 0 1176f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_PREEMPT 0x0708 1177f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_PREEMPT_BASE_IDX 0 1178f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_DUMMY_REG 0x0709 1179f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_DUMMY_REG_BASE_IDX 0 1180f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI 0x070a 1181f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 1182f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO 0x070b 1183f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 1184f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_RB_AQL_CNTL 0x070c 1185f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_RB_AQL_CNTL_BASE_IDX 0 1186f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_MINOR_PTR_UPDATE 0x070d 1187f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX 0 1188f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_RB_PREEMPT 0x070e 1189f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_RB_PREEMPT_BASE_IDX 0 1190f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_MIDCMD_DATA0 0x0718 1191f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_MIDCMD_DATA0_BASE_IDX 0 1192f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_MIDCMD_DATA1 0x0719 1193f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_MIDCMD_DATA1_BASE_IDX 0 1194f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_MIDCMD_DATA2 0x071a 1195f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_MIDCMD_DATA2_BASE_IDX 0 1196f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_MIDCMD_DATA3 0x071b 1197f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_MIDCMD_DATA3_BASE_IDX 0 1198f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_MIDCMD_DATA4 0x071c 1199f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_MIDCMD_DATA4_BASE_IDX 0 1200f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_MIDCMD_DATA5 0x071d 1201f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_MIDCMD_DATA5_BASE_IDX 0 1202f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_MIDCMD_DATA6 0x071e 1203f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_MIDCMD_DATA6_BASE_IDX 0 1204f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_MIDCMD_DATA7 0x071f 1205f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_MIDCMD_DATA7_BASE_IDX 0 1206f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_MIDCMD_DATA8 0x0720 1207f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_MIDCMD_DATA8_BASE_IDX 0 1208f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_MIDCMD_DATA9 0x0721 1209f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_MIDCMD_DATA9_BASE_IDX 0 1210f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_MIDCMD_DATA10 0x0722 1211f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_MIDCMD_DATA10_BASE_IDX 0 1212f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_MIDCMD_CNTL 0x0723 1213f33ac92fSHawking Zhang #define regSDMA1_QUEUE1_MIDCMD_CNTL_BASE_IDX 0 1214f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_RB_CNTL 0x0730 1215f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_RB_CNTL_BASE_IDX 0 1216f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_RB_BASE 0x0731 1217f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_RB_BASE_BASE_IDX 0 1218f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_RB_BASE_HI 0x0732 1219f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_RB_BASE_HI_BASE_IDX 0 1220f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_RB_RPTR 0x0733 1221f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_RB_RPTR_BASE_IDX 0 1222f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_RB_RPTR_HI 0x0734 1223f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_RB_RPTR_HI_BASE_IDX 0 1224f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_RB_WPTR 0x0735 1225f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_RB_WPTR_BASE_IDX 0 1226f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_RB_WPTR_HI 0x0736 1227f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_RB_WPTR_HI_BASE_IDX 0 1228f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_RB_RPTR_ADDR_HI 0x0738 1229f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX 0 1230f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_RB_RPTR_ADDR_LO 0x0739 1231f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX 0 1232f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_IB_CNTL 0x073a 1233f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_IB_CNTL_BASE_IDX 0 1234f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_IB_RPTR 0x073b 1235f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_IB_RPTR_BASE_IDX 0 1236f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_IB_OFFSET 0x073c 1237f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_IB_OFFSET_BASE_IDX 0 1238f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_IB_BASE_LO 0x073d 1239f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_IB_BASE_LO_BASE_IDX 0 1240f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_IB_BASE_HI 0x073e 1241f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_IB_BASE_HI_BASE_IDX 0 1242f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_IB_SIZE 0x073f 1243f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_IB_SIZE_BASE_IDX 0 1244f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_SKIP_CNTL 0x0740 1245f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_SKIP_CNTL_BASE_IDX 0 1246f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_CONTEXT_STATUS 0x0741 1247f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_CONTEXT_STATUS_BASE_IDX 0 1248f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_DOORBELL 0x0742 1249f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_DOORBELL_BASE_IDX 0 1250f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_DOORBELL_LOG 0x0759 1251f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_DOORBELL_LOG_BASE_IDX 0 1252f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_DOORBELL_OFFSET 0x075b 1253f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_DOORBELL_OFFSET_BASE_IDX 0 1254f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_CSA_ADDR_LO 0x075c 1255f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_CSA_ADDR_LO_BASE_IDX 0 1256f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_CSA_ADDR_HI 0x075d 1257f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_CSA_ADDR_HI_BASE_IDX 0 1258f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_SCHEDULE_CNTL 0x075e 1259f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_SCHEDULE_CNTL_BASE_IDX 0 1260f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_IB_SUB_REMAIN 0x075f 1261f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_IB_SUB_REMAIN_BASE_IDX 0 1262f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_PREEMPT 0x0760 1263f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_PREEMPT_BASE_IDX 0 1264f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_DUMMY_REG 0x0761 1265f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_DUMMY_REG_BASE_IDX 0 1266f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI 0x0762 1267f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 1268f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO 0x0763 1269f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 1270f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_RB_AQL_CNTL 0x0764 1271f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_RB_AQL_CNTL_BASE_IDX 0 1272f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_MINOR_PTR_UPDATE 0x0765 1273f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX 0 1274f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_RB_PREEMPT 0x0766 1275f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_RB_PREEMPT_BASE_IDX 0 1276f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_MIDCMD_DATA0 0x0770 1277f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_MIDCMD_DATA0_BASE_IDX 0 1278f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_MIDCMD_DATA1 0x0771 1279f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_MIDCMD_DATA1_BASE_IDX 0 1280f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_MIDCMD_DATA2 0x0772 1281f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_MIDCMD_DATA2_BASE_IDX 0 1282f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_MIDCMD_DATA3 0x0773 1283f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_MIDCMD_DATA3_BASE_IDX 0 1284f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_MIDCMD_DATA4 0x0774 1285f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_MIDCMD_DATA4_BASE_IDX 0 1286f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_MIDCMD_DATA5 0x0775 1287f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_MIDCMD_DATA5_BASE_IDX 0 1288f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_MIDCMD_DATA6 0x0776 1289f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_MIDCMD_DATA6_BASE_IDX 0 1290f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_MIDCMD_DATA7 0x0777 1291f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_MIDCMD_DATA7_BASE_IDX 0 1292f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_MIDCMD_DATA8 0x0778 1293f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_MIDCMD_DATA8_BASE_IDX 0 1294f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_MIDCMD_DATA9 0x0779 1295f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_MIDCMD_DATA9_BASE_IDX 0 1296f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_MIDCMD_DATA10 0x077a 1297f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_MIDCMD_DATA10_BASE_IDX 0 1298f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_MIDCMD_CNTL 0x077b 1299f33ac92fSHawking Zhang #define regSDMA1_QUEUE2_MIDCMD_CNTL_BASE_IDX 0 1300f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_RB_CNTL 0x0788 1301f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_RB_CNTL_BASE_IDX 0 1302f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_RB_BASE 0x0789 1303f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_RB_BASE_BASE_IDX 0 1304f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_RB_BASE_HI 0x078a 1305f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_RB_BASE_HI_BASE_IDX 0 1306f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_RB_RPTR 0x078b 1307f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_RB_RPTR_BASE_IDX 0 1308f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_RB_RPTR_HI 0x078c 1309f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_RB_RPTR_HI_BASE_IDX 0 1310f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_RB_WPTR 0x078d 1311f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_RB_WPTR_BASE_IDX 0 1312f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_RB_WPTR_HI 0x078e 1313f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_RB_WPTR_HI_BASE_IDX 0 1314f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_RB_RPTR_ADDR_HI 0x0790 1315f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX 0 1316f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_RB_RPTR_ADDR_LO 0x0791 1317f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX 0 1318f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_IB_CNTL 0x0792 1319f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_IB_CNTL_BASE_IDX 0 1320f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_IB_RPTR 0x0793 1321f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_IB_RPTR_BASE_IDX 0 1322f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_IB_OFFSET 0x0794 1323f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_IB_OFFSET_BASE_IDX 0 1324f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_IB_BASE_LO 0x0795 1325f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_IB_BASE_LO_BASE_IDX 0 1326f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_IB_BASE_HI 0x0796 1327f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_IB_BASE_HI_BASE_IDX 0 1328f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_IB_SIZE 0x0797 1329f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_IB_SIZE_BASE_IDX 0 1330f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_SKIP_CNTL 0x0798 1331f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_SKIP_CNTL_BASE_IDX 0 1332f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_CONTEXT_STATUS 0x0799 1333f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_CONTEXT_STATUS_BASE_IDX 0 1334f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_DOORBELL 0x079a 1335f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_DOORBELL_BASE_IDX 0 1336f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_DOORBELL_LOG 0x07b1 1337f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_DOORBELL_LOG_BASE_IDX 0 1338f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_DOORBELL_OFFSET 0x07b3 1339f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_DOORBELL_OFFSET_BASE_IDX 0 1340f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_CSA_ADDR_LO 0x07b4 1341f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_CSA_ADDR_LO_BASE_IDX 0 1342f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_CSA_ADDR_HI 0x07b5 1343f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_CSA_ADDR_HI_BASE_IDX 0 1344f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_SCHEDULE_CNTL 0x07b6 1345f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_SCHEDULE_CNTL_BASE_IDX 0 1346f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_IB_SUB_REMAIN 0x07b7 1347f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_IB_SUB_REMAIN_BASE_IDX 0 1348f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_PREEMPT 0x07b8 1349f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_PREEMPT_BASE_IDX 0 1350f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_DUMMY_REG 0x07b9 1351f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_DUMMY_REG_BASE_IDX 0 1352f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI 0x07ba 1353f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 1354f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO 0x07bb 1355f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 1356f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_RB_AQL_CNTL 0x07bc 1357f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_RB_AQL_CNTL_BASE_IDX 0 1358f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_MINOR_PTR_UPDATE 0x07bd 1359f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX 0 1360f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_RB_PREEMPT 0x07be 1361f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_RB_PREEMPT_BASE_IDX 0 1362f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_MIDCMD_DATA0 0x07c8 1363f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_MIDCMD_DATA0_BASE_IDX 0 1364f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_MIDCMD_DATA1 0x07c9 1365f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_MIDCMD_DATA1_BASE_IDX 0 1366f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_MIDCMD_DATA2 0x07ca 1367f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_MIDCMD_DATA2_BASE_IDX 0 1368f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_MIDCMD_DATA3 0x07cb 1369f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_MIDCMD_DATA3_BASE_IDX 0 1370f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_MIDCMD_DATA4 0x07cc 1371f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_MIDCMD_DATA4_BASE_IDX 0 1372f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_MIDCMD_DATA5 0x07cd 1373f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_MIDCMD_DATA5_BASE_IDX 0 1374f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_MIDCMD_DATA6 0x07ce 1375f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_MIDCMD_DATA6_BASE_IDX 0 1376f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_MIDCMD_DATA7 0x07cf 1377f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_MIDCMD_DATA7_BASE_IDX 0 1378f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_MIDCMD_DATA8 0x07d0 1379f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_MIDCMD_DATA8_BASE_IDX 0 1380f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_MIDCMD_DATA9 0x07d1 1381f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_MIDCMD_DATA9_BASE_IDX 0 1382f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_MIDCMD_DATA10 0x07d2 1383f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_MIDCMD_DATA10_BASE_IDX 0 1384f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_MIDCMD_CNTL 0x07d3 1385f33ac92fSHawking Zhang #define regSDMA1_QUEUE3_MIDCMD_CNTL_BASE_IDX 0 1386f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_RB_CNTL 0x07e0 1387f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_RB_CNTL_BASE_IDX 0 1388f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_RB_BASE 0x07e1 1389f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_RB_BASE_BASE_IDX 0 1390f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_RB_BASE_HI 0x07e2 1391f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_RB_BASE_HI_BASE_IDX 0 1392f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_RB_RPTR 0x07e3 1393f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_RB_RPTR_BASE_IDX 0 1394f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_RB_RPTR_HI 0x07e4 1395f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_RB_RPTR_HI_BASE_IDX 0 1396f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_RB_WPTR 0x07e5 1397f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_RB_WPTR_BASE_IDX 0 1398f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_RB_WPTR_HI 0x07e6 1399f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_RB_WPTR_HI_BASE_IDX 0 1400f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_RB_RPTR_ADDR_HI 0x07e8 1401f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX 0 1402f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_RB_RPTR_ADDR_LO 0x07e9 1403f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX 0 1404f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_IB_CNTL 0x07ea 1405f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_IB_CNTL_BASE_IDX 0 1406f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_IB_RPTR 0x07eb 1407f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_IB_RPTR_BASE_IDX 0 1408f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_IB_OFFSET 0x07ec 1409f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_IB_OFFSET_BASE_IDX 0 1410f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_IB_BASE_LO 0x07ed 1411f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_IB_BASE_LO_BASE_IDX 0 1412f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_IB_BASE_HI 0x07ee 1413f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_IB_BASE_HI_BASE_IDX 0 1414f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_IB_SIZE 0x07ef 1415f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_IB_SIZE_BASE_IDX 0 1416f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_SKIP_CNTL 0x07f0 1417f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_SKIP_CNTL_BASE_IDX 0 1418f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_CONTEXT_STATUS 0x07f1 1419f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_CONTEXT_STATUS_BASE_IDX 0 1420f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_DOORBELL 0x07f2 1421f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_DOORBELL_BASE_IDX 0 1422f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_DOORBELL_LOG 0x0809 1423f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_DOORBELL_LOG_BASE_IDX 0 1424f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_DOORBELL_OFFSET 0x080b 1425f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_DOORBELL_OFFSET_BASE_IDX 0 1426f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_CSA_ADDR_LO 0x080c 1427f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_CSA_ADDR_LO_BASE_IDX 0 1428f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_CSA_ADDR_HI 0x080d 1429f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_CSA_ADDR_HI_BASE_IDX 0 1430f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_SCHEDULE_CNTL 0x080e 1431f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_SCHEDULE_CNTL_BASE_IDX 0 1432f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_IB_SUB_REMAIN 0x080f 1433f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_IB_SUB_REMAIN_BASE_IDX 0 1434f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_PREEMPT 0x0810 1435f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_PREEMPT_BASE_IDX 0 1436f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_DUMMY_REG 0x0811 1437f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_DUMMY_REG_BASE_IDX 0 1438f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI 0x0812 1439f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 1440f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO 0x0813 1441f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 1442f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_RB_AQL_CNTL 0x0814 1443f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_RB_AQL_CNTL_BASE_IDX 0 1444f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_MINOR_PTR_UPDATE 0x0815 1445f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX 0 1446f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_RB_PREEMPT 0x0816 1447f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_RB_PREEMPT_BASE_IDX 0 1448f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_MIDCMD_DATA0 0x0820 1449f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_MIDCMD_DATA0_BASE_IDX 0 1450f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_MIDCMD_DATA1 0x0821 1451f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_MIDCMD_DATA1_BASE_IDX 0 1452f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_MIDCMD_DATA2 0x0822 1453f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_MIDCMD_DATA2_BASE_IDX 0 1454f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_MIDCMD_DATA3 0x0823 1455f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_MIDCMD_DATA3_BASE_IDX 0 1456f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_MIDCMD_DATA4 0x0824 1457f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_MIDCMD_DATA4_BASE_IDX 0 1458f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_MIDCMD_DATA5 0x0825 1459f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_MIDCMD_DATA5_BASE_IDX 0 1460f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_MIDCMD_DATA6 0x0826 1461f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_MIDCMD_DATA6_BASE_IDX 0 1462f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_MIDCMD_DATA7 0x0827 1463f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_MIDCMD_DATA7_BASE_IDX 0 1464f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_MIDCMD_DATA8 0x0828 1465f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_MIDCMD_DATA8_BASE_IDX 0 1466f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_MIDCMD_DATA9 0x0829 1467f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_MIDCMD_DATA9_BASE_IDX 0 1468f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_MIDCMD_DATA10 0x082a 1469f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_MIDCMD_DATA10_BASE_IDX 0 1470f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_MIDCMD_CNTL 0x082b 1471f33ac92fSHawking Zhang #define regSDMA1_QUEUE4_MIDCMD_CNTL_BASE_IDX 0 1472f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_RB_CNTL 0x0838 1473f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_RB_CNTL_BASE_IDX 0 1474f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_RB_BASE 0x0839 1475f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_RB_BASE_BASE_IDX 0 1476f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_RB_BASE_HI 0x083a 1477f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_RB_BASE_HI_BASE_IDX 0 1478f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_RB_RPTR 0x083b 1479f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_RB_RPTR_BASE_IDX 0 1480f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_RB_RPTR_HI 0x083c 1481f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_RB_RPTR_HI_BASE_IDX 0 1482f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_RB_WPTR 0x083d 1483f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_RB_WPTR_BASE_IDX 0 1484f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_RB_WPTR_HI 0x083e 1485f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_RB_WPTR_HI_BASE_IDX 0 1486f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_RB_RPTR_ADDR_HI 0x0840 1487f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX 0 1488f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_RB_RPTR_ADDR_LO 0x0841 1489f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX 0 1490f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_IB_CNTL 0x0842 1491f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_IB_CNTL_BASE_IDX 0 1492f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_IB_RPTR 0x0843 1493f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_IB_RPTR_BASE_IDX 0 1494f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_IB_OFFSET 0x0844 1495f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_IB_OFFSET_BASE_IDX 0 1496f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_IB_BASE_LO 0x0845 1497f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_IB_BASE_LO_BASE_IDX 0 1498f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_IB_BASE_HI 0x0846 1499f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_IB_BASE_HI_BASE_IDX 0 1500f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_IB_SIZE 0x0847 1501f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_IB_SIZE_BASE_IDX 0 1502f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_SKIP_CNTL 0x0848 1503f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_SKIP_CNTL_BASE_IDX 0 1504f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_CONTEXT_STATUS 0x0849 1505f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_CONTEXT_STATUS_BASE_IDX 0 1506f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_DOORBELL 0x084a 1507f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_DOORBELL_BASE_IDX 0 1508f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_DOORBELL_LOG 0x0861 1509f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_DOORBELL_LOG_BASE_IDX 0 1510f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_DOORBELL_OFFSET 0x0863 1511f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_DOORBELL_OFFSET_BASE_IDX 0 1512f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_CSA_ADDR_LO 0x0864 1513f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_CSA_ADDR_LO_BASE_IDX 0 1514f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_CSA_ADDR_HI 0x0865 1515f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_CSA_ADDR_HI_BASE_IDX 0 1516f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_SCHEDULE_CNTL 0x0866 1517f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_SCHEDULE_CNTL_BASE_IDX 0 1518f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_IB_SUB_REMAIN 0x0867 1519f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_IB_SUB_REMAIN_BASE_IDX 0 1520f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_PREEMPT 0x0868 1521f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_PREEMPT_BASE_IDX 0 1522f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_DUMMY_REG 0x0869 1523f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_DUMMY_REG_BASE_IDX 0 1524f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI 0x086a 1525f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 1526f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO 0x086b 1527f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 1528f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_RB_AQL_CNTL 0x086c 1529f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_RB_AQL_CNTL_BASE_IDX 0 1530f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_MINOR_PTR_UPDATE 0x086d 1531f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX 0 1532f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_RB_PREEMPT 0x086e 1533f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_RB_PREEMPT_BASE_IDX 0 1534f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_MIDCMD_DATA0 0x0878 1535f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_MIDCMD_DATA0_BASE_IDX 0 1536f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_MIDCMD_DATA1 0x0879 1537f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_MIDCMD_DATA1_BASE_IDX 0 1538f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_MIDCMD_DATA2 0x087a 1539f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_MIDCMD_DATA2_BASE_IDX 0 1540f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_MIDCMD_DATA3 0x087b 1541f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_MIDCMD_DATA3_BASE_IDX 0 1542f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_MIDCMD_DATA4 0x087c 1543f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_MIDCMD_DATA4_BASE_IDX 0 1544f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_MIDCMD_DATA5 0x087d 1545f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_MIDCMD_DATA5_BASE_IDX 0 1546f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_MIDCMD_DATA6 0x087e 1547f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_MIDCMD_DATA6_BASE_IDX 0 1548f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_MIDCMD_DATA7 0x087f 1549f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_MIDCMD_DATA7_BASE_IDX 0 1550f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_MIDCMD_DATA8 0x0880 1551f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_MIDCMD_DATA8_BASE_IDX 0 1552f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_MIDCMD_DATA9 0x0881 1553f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_MIDCMD_DATA9_BASE_IDX 0 1554f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_MIDCMD_DATA10 0x0882 1555f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_MIDCMD_DATA10_BASE_IDX 0 1556f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_MIDCMD_CNTL 0x0883 1557f33ac92fSHawking Zhang #define regSDMA1_QUEUE5_MIDCMD_CNTL_BASE_IDX 0 1558f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_RB_CNTL 0x0890 1559f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_RB_CNTL_BASE_IDX 0 1560f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_RB_BASE 0x0891 1561f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_RB_BASE_BASE_IDX 0 1562f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_RB_BASE_HI 0x0892 1563f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_RB_BASE_HI_BASE_IDX 0 1564f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_RB_RPTR 0x0893 1565f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_RB_RPTR_BASE_IDX 0 1566f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_RB_RPTR_HI 0x0894 1567f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_RB_RPTR_HI_BASE_IDX 0 1568f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_RB_WPTR 0x0895 1569f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_RB_WPTR_BASE_IDX 0 1570f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_RB_WPTR_HI 0x0896 1571f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_RB_WPTR_HI_BASE_IDX 0 1572f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_RB_RPTR_ADDR_HI 0x0898 1573f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX 0 1574f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_RB_RPTR_ADDR_LO 0x0899 1575f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX 0 1576f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_IB_CNTL 0x089a 1577f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_IB_CNTL_BASE_IDX 0 1578f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_IB_RPTR 0x089b 1579f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_IB_RPTR_BASE_IDX 0 1580f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_IB_OFFSET 0x089c 1581f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_IB_OFFSET_BASE_IDX 0 1582f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_IB_BASE_LO 0x089d 1583f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_IB_BASE_LO_BASE_IDX 0 1584f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_IB_BASE_HI 0x089e 1585f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_IB_BASE_HI_BASE_IDX 0 1586f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_IB_SIZE 0x089f 1587f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_IB_SIZE_BASE_IDX 0 1588f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_SKIP_CNTL 0x08a0 1589f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_SKIP_CNTL_BASE_IDX 0 1590f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_CONTEXT_STATUS 0x08a1 1591f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_CONTEXT_STATUS_BASE_IDX 0 1592f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_DOORBELL 0x08a2 1593f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_DOORBELL_BASE_IDX 0 1594f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_DOORBELL_LOG 0x08b9 1595f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_DOORBELL_LOG_BASE_IDX 0 1596f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_DOORBELL_OFFSET 0x08bb 1597f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_DOORBELL_OFFSET_BASE_IDX 0 1598f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_CSA_ADDR_LO 0x08bc 1599f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_CSA_ADDR_LO_BASE_IDX 0 1600f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_CSA_ADDR_HI 0x08bd 1601f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_CSA_ADDR_HI_BASE_IDX 0 1602f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_SCHEDULE_CNTL 0x08be 1603f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_SCHEDULE_CNTL_BASE_IDX 0 1604f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_IB_SUB_REMAIN 0x08bf 1605f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_IB_SUB_REMAIN_BASE_IDX 0 1606f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_PREEMPT 0x08c0 1607f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_PREEMPT_BASE_IDX 0 1608f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_DUMMY_REG 0x08c1 1609f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_DUMMY_REG_BASE_IDX 0 1610f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI 0x08c2 1611f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 1612f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO 0x08c3 1613f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 1614f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_RB_AQL_CNTL 0x08c4 1615f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_RB_AQL_CNTL_BASE_IDX 0 1616f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_MINOR_PTR_UPDATE 0x08c5 1617f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX 0 1618f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_RB_PREEMPT 0x08c6 1619f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_RB_PREEMPT_BASE_IDX 0 1620f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_MIDCMD_DATA0 0x08d0 1621f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_MIDCMD_DATA0_BASE_IDX 0 1622f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_MIDCMD_DATA1 0x08d1 1623f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_MIDCMD_DATA1_BASE_IDX 0 1624f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_MIDCMD_DATA2 0x08d2 1625f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_MIDCMD_DATA2_BASE_IDX 0 1626f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_MIDCMD_DATA3 0x08d3 1627f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_MIDCMD_DATA3_BASE_IDX 0 1628f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_MIDCMD_DATA4 0x08d4 1629f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_MIDCMD_DATA4_BASE_IDX 0 1630f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_MIDCMD_DATA5 0x08d5 1631f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_MIDCMD_DATA5_BASE_IDX 0 1632f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_MIDCMD_DATA6 0x08d6 1633f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_MIDCMD_DATA6_BASE_IDX 0 1634f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_MIDCMD_DATA7 0x08d7 1635f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_MIDCMD_DATA7_BASE_IDX 0 1636f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_MIDCMD_DATA8 0x08d8 1637f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_MIDCMD_DATA8_BASE_IDX 0 1638f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_MIDCMD_DATA9 0x08d9 1639f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_MIDCMD_DATA9_BASE_IDX 0 1640f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_MIDCMD_DATA10 0x08da 1641f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_MIDCMD_DATA10_BASE_IDX 0 1642f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_MIDCMD_CNTL 0x08db 1643f33ac92fSHawking Zhang #define regSDMA1_QUEUE6_MIDCMD_CNTL_BASE_IDX 0 1644f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_RB_CNTL 0x08e8 1645f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_RB_CNTL_BASE_IDX 0 1646f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_RB_BASE 0x08e9 1647f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_RB_BASE_BASE_IDX 0 1648f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_RB_BASE_HI 0x08ea 1649f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_RB_BASE_HI_BASE_IDX 0 1650f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_RB_RPTR 0x08eb 1651f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_RB_RPTR_BASE_IDX 0 1652f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_RB_RPTR_HI 0x08ec 1653f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_RB_RPTR_HI_BASE_IDX 0 1654f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_RB_WPTR 0x08ed 1655f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_RB_WPTR_BASE_IDX 0 1656f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_RB_WPTR_HI 0x08ee 1657f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_RB_WPTR_HI_BASE_IDX 0 1658f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_RB_RPTR_ADDR_HI 0x08f0 1659f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX 0 1660f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_RB_RPTR_ADDR_LO 0x08f1 1661f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX 0 1662f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_IB_CNTL 0x08f2 1663f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_IB_CNTL_BASE_IDX 0 1664f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_IB_RPTR 0x08f3 1665f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_IB_RPTR_BASE_IDX 0 1666f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_IB_OFFSET 0x08f4 1667f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_IB_OFFSET_BASE_IDX 0 1668f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_IB_BASE_LO 0x08f5 1669f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_IB_BASE_LO_BASE_IDX 0 1670f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_IB_BASE_HI 0x08f6 1671f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_IB_BASE_HI_BASE_IDX 0 1672f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_IB_SIZE 0x08f7 1673f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_IB_SIZE_BASE_IDX 0 1674f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_SKIP_CNTL 0x08f8 1675f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_SKIP_CNTL_BASE_IDX 0 1676f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_CONTEXT_STATUS 0x08f9 1677f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_CONTEXT_STATUS_BASE_IDX 0 1678f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_DOORBELL 0x08fa 1679f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_DOORBELL_BASE_IDX 0 1680f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_DOORBELL_LOG 0x0911 1681f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_DOORBELL_LOG_BASE_IDX 0 1682f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_DOORBELL_OFFSET 0x0913 1683f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_DOORBELL_OFFSET_BASE_IDX 0 1684f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_CSA_ADDR_LO 0x0914 1685f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_CSA_ADDR_LO_BASE_IDX 0 1686f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_CSA_ADDR_HI 0x0915 1687f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_CSA_ADDR_HI_BASE_IDX 0 1688f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_SCHEDULE_CNTL 0x0916 1689f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_SCHEDULE_CNTL_BASE_IDX 0 1690f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_IB_SUB_REMAIN 0x0917 1691f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_IB_SUB_REMAIN_BASE_IDX 0 1692f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_PREEMPT 0x0918 1693f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_PREEMPT_BASE_IDX 0 1694f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_DUMMY_REG 0x0919 1695f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_DUMMY_REG_BASE_IDX 0 1696f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI 0x091a 1697f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 1698f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO 0x091b 1699f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 1700f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_RB_AQL_CNTL 0x091c 1701f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_RB_AQL_CNTL_BASE_IDX 0 1702f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_MINOR_PTR_UPDATE 0x091d 1703f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX 0 1704f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_RB_PREEMPT 0x091e 1705f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_RB_PREEMPT_BASE_IDX 0 1706f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_MIDCMD_DATA0 0x0928 1707f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_MIDCMD_DATA0_BASE_IDX 0 1708f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_MIDCMD_DATA1 0x0929 1709f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_MIDCMD_DATA1_BASE_IDX 0 1710f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_MIDCMD_DATA2 0x092a 1711f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_MIDCMD_DATA2_BASE_IDX 0 1712f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_MIDCMD_DATA3 0x092b 1713f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_MIDCMD_DATA3_BASE_IDX 0 1714f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_MIDCMD_DATA4 0x092c 1715f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_MIDCMD_DATA4_BASE_IDX 0 1716f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_MIDCMD_DATA5 0x092d 1717f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_MIDCMD_DATA5_BASE_IDX 0 1718f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_MIDCMD_DATA6 0x092e 1719f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_MIDCMD_DATA6_BASE_IDX 0 1720f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_MIDCMD_DATA7 0x092f 1721f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_MIDCMD_DATA7_BASE_IDX 0 1722f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_MIDCMD_DATA8 0x0930 1723f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_MIDCMD_DATA8_BASE_IDX 0 1724f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_MIDCMD_DATA9 0x0931 1725f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_MIDCMD_DATA9_BASE_IDX 0 1726f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_MIDCMD_DATA10 0x0932 1727f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_MIDCMD_DATA10_BASE_IDX 0 1728f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_MIDCMD_CNTL 0x0933 1729f33ac92fSHawking Zhang #define regSDMA1_QUEUE7_MIDCMD_CNTL_BASE_IDX 0 1730f33ac92fSHawking Zhang 1731f33ac92fSHawking Zhang 1732f33ac92fSHawking Zhang // addressBlock: gc_sdma0_sdma0hypdec 1733f33ac92fSHawking Zhang // base address: 0x3e200 1734f33ac92fSHawking Zhang #define regSDMA0_UCODE_ADDR 0x5880 1735f33ac92fSHawking Zhang #define regSDMA0_UCODE_ADDR_BASE_IDX 1 1736f33ac92fSHawking Zhang #define regSDMA0_UCODE_DATA 0x5881 1737f33ac92fSHawking Zhang #define regSDMA0_UCODE_DATA_BASE_IDX 1 1738f33ac92fSHawking Zhang #define regSDMA0_UCODE_SELFLOAD_CONTROL 0x5882 1739f33ac92fSHawking Zhang #define regSDMA0_UCODE_SELFLOAD_CONTROL_BASE_IDX 1 1740f33ac92fSHawking Zhang #define regSDMA0_BROADCAST_UCODE_ADDR 0x5886 1741f33ac92fSHawking Zhang #define regSDMA0_BROADCAST_UCODE_ADDR_BASE_IDX 1 1742f33ac92fSHawking Zhang #define regSDMA0_BROADCAST_UCODE_DATA 0x5887 1743f33ac92fSHawking Zhang #define regSDMA0_BROADCAST_UCODE_DATA_BASE_IDX 1 1744f33ac92fSHawking Zhang #define regSDMA0_F32_CNTL 0x589a 1745f33ac92fSHawking Zhang #define regSDMA0_F32_CNTL_BASE_IDX 1 1746f33ac92fSHawking Zhang 1747f33ac92fSHawking Zhang 1748f33ac92fSHawking Zhang // addressBlock: gc_sdma0_sdma1hypdec 1749f33ac92fSHawking Zhang // base address: 0x3e280 1750f33ac92fSHawking Zhang #define regSDMA1_UCODE_ADDR 0x58a0 1751f33ac92fSHawking Zhang #define regSDMA1_UCODE_ADDR_BASE_IDX 1 1752f33ac92fSHawking Zhang #define regSDMA1_UCODE_DATA 0x58a1 1753f33ac92fSHawking Zhang #define regSDMA1_UCODE_DATA_BASE_IDX 1 1754f33ac92fSHawking Zhang #define regSDMA1_UCODE_SELFLOAD_CONTROL 0x58a2 1755f33ac92fSHawking Zhang #define regSDMA1_UCODE_SELFLOAD_CONTROL_BASE_IDX 1 1756f33ac92fSHawking Zhang #define regSDMA1_BROADCAST_UCODE_ADDR 0x58a6 1757f33ac92fSHawking Zhang #define regSDMA1_BROADCAST_UCODE_ADDR_BASE_IDX 1 1758f33ac92fSHawking Zhang #define regSDMA1_BROADCAST_UCODE_DATA 0x58a7 1759f33ac92fSHawking Zhang #define regSDMA1_BROADCAST_UCODE_DATA_BASE_IDX 1 1760f33ac92fSHawking Zhang #define regSDMA1_F32_CNTL 0x58ba 1761f33ac92fSHawking Zhang #define regSDMA1_F32_CNTL_BASE_IDX 1 1762f33ac92fSHawking Zhang 1763f33ac92fSHawking Zhang 1764f33ac92fSHawking Zhang // addressBlock: gc_sdma0_sdma0perfsdec 1765f33ac92fSHawking Zhang // base address: 0x37880 1766f33ac92fSHawking Zhang #define regSDMA0_PERFCNT_PERFCOUNTER0_CFG 0x3e20 1767f33ac92fSHawking Zhang #define regSDMA0_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 1 1768f33ac92fSHawking Zhang #define regSDMA0_PERFCNT_PERFCOUNTER1_CFG 0x3e21 1769f33ac92fSHawking Zhang #define regSDMA0_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 1 1770f33ac92fSHawking Zhang #define regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x3e22 1771f33ac92fSHawking Zhang #define regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 1772f33ac92fSHawking Zhang #define regSDMA0_PERFCNT_MISC_CNTL 0x3e23 1773f33ac92fSHawking Zhang #define regSDMA0_PERFCNT_MISC_CNTL_BASE_IDX 1 1774f33ac92fSHawking Zhang #define regSDMA0_PERFCOUNTER0_SELECT 0x3e24 1775f33ac92fSHawking Zhang #define regSDMA0_PERFCOUNTER0_SELECT_BASE_IDX 1 1776f33ac92fSHawking Zhang #define regSDMA0_PERFCOUNTER0_SELECT1 0x3e25 1777f33ac92fSHawking Zhang #define regSDMA0_PERFCOUNTER0_SELECT1_BASE_IDX 1 1778f33ac92fSHawking Zhang #define regSDMA0_PERFCOUNTER1_SELECT 0x3e26 1779f33ac92fSHawking Zhang #define regSDMA0_PERFCOUNTER1_SELECT_BASE_IDX 1 1780f33ac92fSHawking Zhang #define regSDMA0_PERFCOUNTER1_SELECT1 0x3e27 1781f33ac92fSHawking Zhang #define regSDMA0_PERFCOUNTER1_SELECT1_BASE_IDX 1 1782f33ac92fSHawking Zhang 1783f33ac92fSHawking Zhang 1784f33ac92fSHawking Zhang // addressBlock: gc_sdma0_sdma1perfsdec 1785f33ac92fSHawking Zhang // base address: 0x378b0 1786f33ac92fSHawking Zhang #define regSDMA1_PERFCNT_PERFCOUNTER0_CFG 0x3e2c 1787f33ac92fSHawking Zhang #define regSDMA1_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 1 1788f33ac92fSHawking Zhang #define regSDMA1_PERFCNT_PERFCOUNTER1_CFG 0x3e2d 1789f33ac92fSHawking Zhang #define regSDMA1_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 1 1790f33ac92fSHawking Zhang #define regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x3e2e 1791f33ac92fSHawking Zhang #define regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 1792f33ac92fSHawking Zhang #define regSDMA1_PERFCNT_MISC_CNTL 0x3e2f 1793f33ac92fSHawking Zhang #define regSDMA1_PERFCNT_MISC_CNTL_BASE_IDX 1 1794f33ac92fSHawking Zhang #define regSDMA1_PERFCOUNTER0_SELECT 0x3e30 1795f33ac92fSHawking Zhang #define regSDMA1_PERFCOUNTER0_SELECT_BASE_IDX 1 1796f33ac92fSHawking Zhang #define regSDMA1_PERFCOUNTER0_SELECT1 0x3e31 1797f33ac92fSHawking Zhang #define regSDMA1_PERFCOUNTER0_SELECT1_BASE_IDX 1 1798f33ac92fSHawking Zhang #define regSDMA1_PERFCOUNTER1_SELECT 0x3e32 1799f33ac92fSHawking Zhang #define regSDMA1_PERFCOUNTER1_SELECT_BASE_IDX 1 1800f33ac92fSHawking Zhang #define regSDMA1_PERFCOUNTER1_SELECT1 0x3e33 1801f33ac92fSHawking Zhang #define regSDMA1_PERFCOUNTER1_SELECT1_BASE_IDX 1 1802f33ac92fSHawking Zhang 1803f33ac92fSHawking Zhang 1804f33ac92fSHawking Zhang // addressBlock: gc_sdma0_sdma0perfddec 1805f33ac92fSHawking Zhang // base address: 0x35980 1806f33ac92fSHawking Zhang #define regSDMA0_PERFCNT_PERFCOUNTER_LO 0x3660 1807f33ac92fSHawking Zhang #define regSDMA0_PERFCNT_PERFCOUNTER_LO_BASE_IDX 1 1808f33ac92fSHawking Zhang #define regSDMA0_PERFCNT_PERFCOUNTER_HI 0x3661 1809f33ac92fSHawking Zhang #define regSDMA0_PERFCNT_PERFCOUNTER_HI_BASE_IDX 1 1810f33ac92fSHawking Zhang #define regSDMA0_PERFCOUNTER0_LO 0x3662 1811f33ac92fSHawking Zhang #define regSDMA0_PERFCOUNTER0_LO_BASE_IDX 1 1812f33ac92fSHawking Zhang #define regSDMA0_PERFCOUNTER0_HI 0x3663 1813f33ac92fSHawking Zhang #define regSDMA0_PERFCOUNTER0_HI_BASE_IDX 1 1814f33ac92fSHawking Zhang #define regSDMA0_PERFCOUNTER1_LO 0x3664 1815f33ac92fSHawking Zhang #define regSDMA0_PERFCOUNTER1_LO_BASE_IDX 1 1816f33ac92fSHawking Zhang #define regSDMA0_PERFCOUNTER1_HI 0x3665 1817f33ac92fSHawking Zhang #define regSDMA0_PERFCOUNTER1_HI_BASE_IDX 1 1818f33ac92fSHawking Zhang 1819f33ac92fSHawking Zhang 1820f33ac92fSHawking Zhang // addressBlock: gc_sdma0_sdma1perfddec 1821f33ac92fSHawking Zhang // base address: 0x359b0 1822f33ac92fSHawking Zhang #define regSDMA1_PERFCNT_PERFCOUNTER_LO 0x366c 1823f33ac92fSHawking Zhang #define regSDMA1_PERFCNT_PERFCOUNTER_LO_BASE_IDX 1 1824f33ac92fSHawking Zhang #define regSDMA1_PERFCNT_PERFCOUNTER_HI 0x366d 1825f33ac92fSHawking Zhang #define regSDMA1_PERFCNT_PERFCOUNTER_HI_BASE_IDX 1 1826f33ac92fSHawking Zhang #define regSDMA1_PERFCOUNTER0_LO 0x366e 1827f33ac92fSHawking Zhang #define regSDMA1_PERFCOUNTER0_LO_BASE_IDX 1 1828f33ac92fSHawking Zhang #define regSDMA1_PERFCOUNTER0_HI 0x366f 1829f33ac92fSHawking Zhang #define regSDMA1_PERFCOUNTER0_HI_BASE_IDX 1 1830f33ac92fSHawking Zhang #define regSDMA1_PERFCOUNTER1_LO 0x3670 1831f33ac92fSHawking Zhang #define regSDMA1_PERFCOUNTER1_LO_BASE_IDX 1 1832f33ac92fSHawking Zhang #define regSDMA1_PERFCOUNTER1_HI 0x3671 1833f33ac92fSHawking Zhang #define regSDMA1_PERFCOUNTER1_HI_BASE_IDX 1 1834f33ac92fSHawking Zhang 1835f33ac92fSHawking Zhang 1836f33ac92fSHawking Zhang // addressBlock: gc_grbmdec 1837f33ac92fSHawking Zhang // base address: 0x8000 1838f33ac92fSHawking Zhang #define regGRBM_CNTL 0x0da0 1839f33ac92fSHawking Zhang #define regGRBM_CNTL_BASE_IDX 0 1840f33ac92fSHawking Zhang #define regGRBM_SKEW_CNTL 0x0da1 1841f33ac92fSHawking Zhang #define regGRBM_SKEW_CNTL_BASE_IDX 0 1842f33ac92fSHawking Zhang #define regGRBM_STATUS2 0x0da2 1843f33ac92fSHawking Zhang #define regGRBM_STATUS2_BASE_IDX 0 1844f33ac92fSHawking Zhang #define regGRBM_PWR_CNTL 0x0da3 1845f33ac92fSHawking Zhang #define regGRBM_PWR_CNTL_BASE_IDX 0 1846f33ac92fSHawking Zhang #define regGRBM_STATUS 0x0da4 1847f33ac92fSHawking Zhang #define regGRBM_STATUS_BASE_IDX 0 1848f33ac92fSHawking Zhang #define regGRBM_STATUS_SE0 0x0da5 1849f33ac92fSHawking Zhang #define regGRBM_STATUS_SE0_BASE_IDX 0 1850f33ac92fSHawking Zhang #define regGRBM_STATUS_SE1 0x0da6 1851f33ac92fSHawking Zhang #define regGRBM_STATUS_SE1_BASE_IDX 0 1852f33ac92fSHawking Zhang #define regGRBM_STATUS3 0x0da7 1853f33ac92fSHawking Zhang #define regGRBM_STATUS3_BASE_IDX 0 1854f33ac92fSHawking Zhang #define regGRBM_SOFT_RESET 0x0da8 1855f33ac92fSHawking Zhang #define regGRBM_SOFT_RESET_BASE_IDX 0 1856f33ac92fSHawking Zhang #define regGRBM_GFX_CLKEN_CNTL 0x0dac 1857f33ac92fSHawking Zhang #define regGRBM_GFX_CLKEN_CNTL_BASE_IDX 0 1858f33ac92fSHawking Zhang #define regGRBM_WAIT_IDLE_CLOCKS 0x0dad 1859f33ac92fSHawking Zhang #define regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX 0 1860f33ac92fSHawking Zhang #define regGRBM_STATUS_SE2 0x0dae 1861f33ac92fSHawking Zhang #define regGRBM_STATUS_SE2_BASE_IDX 0 1862f33ac92fSHawking Zhang #define regGRBM_STATUS_SE3 0x0daf 1863f33ac92fSHawking Zhang #define regGRBM_STATUS_SE3_BASE_IDX 0 1864f33ac92fSHawking Zhang #define regGRBM_STATUS_SE4 0x0db0 1865f33ac92fSHawking Zhang #define regGRBM_STATUS_SE4_BASE_IDX 0 1866f33ac92fSHawking Zhang #define regGRBM_STATUS_SE5 0x0db1 1867f33ac92fSHawking Zhang #define regGRBM_STATUS_SE5_BASE_IDX 0 1868f33ac92fSHawking Zhang #define regGRBM_READ_ERROR 0x0db6 1869f33ac92fSHawking Zhang #define regGRBM_READ_ERROR_BASE_IDX 0 1870f33ac92fSHawking Zhang #define regGRBM_READ_ERROR2 0x0db7 1871f33ac92fSHawking Zhang #define regGRBM_READ_ERROR2_BASE_IDX 0 1872f33ac92fSHawking Zhang #define regGRBM_INT_CNTL 0x0db8 1873f33ac92fSHawking Zhang #define regGRBM_INT_CNTL_BASE_IDX 0 1874f33ac92fSHawking Zhang #define regGRBM_TRAP_OP 0x0db9 1875f33ac92fSHawking Zhang #define regGRBM_TRAP_OP_BASE_IDX 0 1876f33ac92fSHawking Zhang #define regGRBM_TRAP_ADDR 0x0dba 1877f33ac92fSHawking Zhang #define regGRBM_TRAP_ADDR_BASE_IDX 0 1878f33ac92fSHawking Zhang #define regGRBM_TRAP_ADDR_MSK 0x0dbb 1879f33ac92fSHawking Zhang #define regGRBM_TRAP_ADDR_MSK_BASE_IDX 0 1880f33ac92fSHawking Zhang #define regGRBM_TRAP_WD 0x0dbc 1881f33ac92fSHawking Zhang #define regGRBM_TRAP_WD_BASE_IDX 0 1882f33ac92fSHawking Zhang #define regGRBM_TRAP_WD_MSK 0x0dbd 1883f33ac92fSHawking Zhang #define regGRBM_TRAP_WD_MSK_BASE_IDX 0 1884f33ac92fSHawking Zhang #define regGRBM_DSM_BYPASS 0x0dbe 1885f33ac92fSHawking Zhang #define regGRBM_DSM_BYPASS_BASE_IDX 0 1886f33ac92fSHawking Zhang #define regGRBM_WRITE_ERROR 0x0dbf 1887f33ac92fSHawking Zhang #define regGRBM_WRITE_ERROR_BASE_IDX 0 1888f33ac92fSHawking Zhang #define regGRBM_CHIP_REVISION 0x0dc1 1889f33ac92fSHawking Zhang #define regGRBM_CHIP_REVISION_BASE_IDX 0 1890f33ac92fSHawking Zhang #define regGRBM_IH_CREDIT 0x0dc4 1891f33ac92fSHawking Zhang #define regGRBM_IH_CREDIT_BASE_IDX 0 1892f33ac92fSHawking Zhang #define regGRBM_PWR_CNTL2 0x0dc5 1893f33ac92fSHawking Zhang #define regGRBM_PWR_CNTL2_BASE_IDX 0 1894f33ac92fSHawking Zhang #define regGRBM_UTCL2_INVAL_RANGE_START 0x0dc6 1895f33ac92fSHawking Zhang #define regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX 0 1896f33ac92fSHawking Zhang #define regGRBM_UTCL2_INVAL_RANGE_END 0x0dc7 1897f33ac92fSHawking Zhang #define regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX 0 1898f33ac92fSHawking Zhang #define regGRBM_INVALID_PIPE 0x0dc9 1899f33ac92fSHawking Zhang #define regGRBM_INVALID_PIPE_BASE_IDX 0 1900f33ac92fSHawking Zhang #define regGRBM_FENCE_RANGE0 0x0dca 1901f33ac92fSHawking Zhang #define regGRBM_FENCE_RANGE0_BASE_IDX 0 1902f33ac92fSHawking Zhang #define regGRBM_FENCE_RANGE1 0x0dcb 1903f33ac92fSHawking Zhang #define regGRBM_FENCE_RANGE1_BASE_IDX 0 1904f33ac92fSHawking Zhang #define regGRBM_SCRATCH_REG0 0x0de0 1905f33ac92fSHawking Zhang #define regGRBM_SCRATCH_REG0_BASE_IDX 0 1906f33ac92fSHawking Zhang #define regGRBM_SCRATCH_REG1 0x0de1 1907f33ac92fSHawking Zhang #define regGRBM_SCRATCH_REG1_BASE_IDX 0 1908f33ac92fSHawking Zhang #define regGRBM_SCRATCH_REG2 0x0de2 1909f33ac92fSHawking Zhang #define regGRBM_SCRATCH_REG2_BASE_IDX 0 1910f33ac92fSHawking Zhang #define regGRBM_SCRATCH_REG3 0x0de3 1911f33ac92fSHawking Zhang #define regGRBM_SCRATCH_REG3_BASE_IDX 0 1912f33ac92fSHawking Zhang #define regGRBM_SCRATCH_REG4 0x0de4 1913f33ac92fSHawking Zhang #define regGRBM_SCRATCH_REG4_BASE_IDX 0 1914f33ac92fSHawking Zhang #define regGRBM_SCRATCH_REG5 0x0de5 1915f33ac92fSHawking Zhang #define regGRBM_SCRATCH_REG5_BASE_IDX 0 1916f33ac92fSHawking Zhang #define regGRBM_SCRATCH_REG6 0x0de6 1917f33ac92fSHawking Zhang #define regGRBM_SCRATCH_REG6_BASE_IDX 0 1918f33ac92fSHawking Zhang #define regGRBM_SCRATCH_REG7 0x0de7 1919f33ac92fSHawking Zhang #define regGRBM_SCRATCH_REG7_BASE_IDX 0 1920f33ac92fSHawking Zhang #define regVIOLATION_DATA_ASYNC_VF_PROG 0x0df1 1921f33ac92fSHawking Zhang #define regVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX 0 1922f33ac92fSHawking Zhang 1923f33ac92fSHawking Zhang 1924f33ac92fSHawking Zhang // addressBlock: gc_cpdec 1925f33ac92fSHawking Zhang // base address: 0x8200 1926f33ac92fSHawking Zhang #define regCP_CPC_DEBUG_CNTL 0x0e20 1927f33ac92fSHawking Zhang #define regCP_CPC_DEBUG_CNTL_BASE_IDX 0 1928f33ac92fSHawking Zhang #define regCP_CPC_DEBUG_DATA 0x0e21 1929f33ac92fSHawking Zhang #define regCP_CPC_DEBUG_DATA_BASE_IDX 0 1930f33ac92fSHawking Zhang #define regCP_CPC_STATUS 0x0e24 1931f33ac92fSHawking Zhang #define regCP_CPC_STATUS_BASE_IDX 0 1932f33ac92fSHawking Zhang #define regCP_CPC_BUSY_STAT 0x0e25 1933f33ac92fSHawking Zhang #define regCP_CPC_BUSY_STAT_BASE_IDX 0 1934f33ac92fSHawking Zhang #define regCP_CPC_STALLED_STAT1 0x0e26 1935f33ac92fSHawking Zhang #define regCP_CPC_STALLED_STAT1_BASE_IDX 0 1936f33ac92fSHawking Zhang #define regCP_CPF_STATUS 0x0e27 1937f33ac92fSHawking Zhang #define regCP_CPF_STATUS_BASE_IDX 0 1938f33ac92fSHawking Zhang #define regCP_CPF_BUSY_STAT 0x0e28 1939f33ac92fSHawking Zhang #define regCP_CPF_BUSY_STAT_BASE_IDX 0 1940f33ac92fSHawking Zhang #define regCP_CPF_STALLED_STAT1 0x0e29 1941f33ac92fSHawking Zhang #define regCP_CPF_STALLED_STAT1_BASE_IDX 0 1942f33ac92fSHawking Zhang #define regCP_CPC_BUSY_STAT2 0x0e2a 1943f33ac92fSHawking Zhang #define regCP_CPC_BUSY_STAT2_BASE_IDX 0 1944f33ac92fSHawking Zhang #define regCP_CPC_GRBM_FREE_COUNT 0x0e2b 1945f33ac92fSHawking Zhang #define regCP_CPC_GRBM_FREE_COUNT_BASE_IDX 0 1946f33ac92fSHawking Zhang #define regCP_CPC_PRIV_VIOLATION_ADDR 0x0e2c 1947f33ac92fSHawking Zhang #define regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX 0 1948f33ac92fSHawking Zhang #define regCP_MEC_ME1_HEADER_DUMP 0x0e2e 1949f33ac92fSHawking Zhang #define regCP_MEC_ME1_HEADER_DUMP_BASE_IDX 0 1950f33ac92fSHawking Zhang #define regCP_MEC_ME2_HEADER_DUMP 0x0e2f 1951f33ac92fSHawking Zhang #define regCP_MEC_ME2_HEADER_DUMP_BASE_IDX 0 1952f33ac92fSHawking Zhang #define regCP_CPC_SCRATCH_INDEX 0x0e30 1953f33ac92fSHawking Zhang #define regCP_CPC_SCRATCH_INDEX_BASE_IDX 0 1954f33ac92fSHawking Zhang #define regCP_CPC_SCRATCH_DATA 0x0e31 1955f33ac92fSHawking Zhang #define regCP_CPC_SCRATCH_DATA_BASE_IDX 0 1956f33ac92fSHawking Zhang #define regCP_CPF_GRBM_FREE_COUNT 0x0e32 1957f33ac92fSHawking Zhang #define regCP_CPF_GRBM_FREE_COUNT_BASE_IDX 0 1958f33ac92fSHawking Zhang #define regCP_CPF_BUSY_STAT2 0x0e33 1959f33ac92fSHawking Zhang #define regCP_CPF_BUSY_STAT2_BASE_IDX 0 1960f33ac92fSHawking Zhang #define regCP_CPC_HALT_HYST_COUNT 0x0e47 1961f33ac92fSHawking Zhang #define regCP_CPC_HALT_HYST_COUNT_BASE_IDX 0 1962f33ac92fSHawking Zhang #define regCP_STALLED_STAT3 0x0f3c 1963f33ac92fSHawking Zhang #define regCP_STALLED_STAT3_BASE_IDX 0 1964f33ac92fSHawking Zhang #define regCP_STALLED_STAT1 0x0f3d 1965f33ac92fSHawking Zhang #define regCP_STALLED_STAT1_BASE_IDX 0 1966f33ac92fSHawking Zhang #define regCP_STALLED_STAT2 0x0f3e 1967f33ac92fSHawking Zhang #define regCP_STALLED_STAT2_BASE_IDX 0 1968f33ac92fSHawking Zhang #define regCP_BUSY_STAT 0x0f3f 1969f33ac92fSHawking Zhang #define regCP_BUSY_STAT_BASE_IDX 0 1970f33ac92fSHawking Zhang #define regCP_STAT 0x0f40 1971f33ac92fSHawking Zhang #define regCP_STAT_BASE_IDX 0 1972f33ac92fSHawking Zhang #define regCP_ME_HEADER_DUMP 0x0f41 1973f33ac92fSHawking Zhang #define regCP_ME_HEADER_DUMP_BASE_IDX 0 1974f33ac92fSHawking Zhang #define regCP_PFP_HEADER_DUMP 0x0f42 1975f33ac92fSHawking Zhang #define regCP_PFP_HEADER_DUMP_BASE_IDX 0 1976f33ac92fSHawking Zhang #define regCP_GRBM_FREE_COUNT 0x0f43 1977f33ac92fSHawking Zhang #define regCP_GRBM_FREE_COUNT_BASE_IDX 0 1978f33ac92fSHawking Zhang #define regCP_PFP_INSTR_PNTR 0x0f45 1979f33ac92fSHawking Zhang #define regCP_PFP_INSTR_PNTR_BASE_IDX 0 1980f33ac92fSHawking Zhang #define regCP_ME_INSTR_PNTR 0x0f46 1981f33ac92fSHawking Zhang #define regCP_ME_INSTR_PNTR_BASE_IDX 0 1982f33ac92fSHawking Zhang #define regCP_MEC1_INSTR_PNTR 0x0f48 1983f33ac92fSHawking Zhang #define regCP_MEC1_INSTR_PNTR_BASE_IDX 0 1984f33ac92fSHawking Zhang #define regCP_MEC2_INSTR_PNTR 0x0f49 1985f33ac92fSHawking Zhang #define regCP_MEC2_INSTR_PNTR_BASE_IDX 0 1986f33ac92fSHawking Zhang #define regCP_CSF_STAT 0x0f54 1987f33ac92fSHawking Zhang #define regCP_CSF_STAT_BASE_IDX 0 1988f33ac92fSHawking Zhang #define regCP_CNTX_STAT 0x0f58 1989f33ac92fSHawking Zhang #define regCP_CNTX_STAT_BASE_IDX 0 1990f33ac92fSHawking Zhang #define regCP_ME_PREEMPTION 0x0f59 1991f33ac92fSHawking Zhang #define regCP_ME_PREEMPTION_BASE_IDX 0 1992f33ac92fSHawking Zhang #define regCP_RB1_RPTR 0x0f5f 1993f33ac92fSHawking Zhang #define regCP_RB1_RPTR_BASE_IDX 0 1994f33ac92fSHawking Zhang #define regCP_RB0_RPTR 0x0f60 1995f33ac92fSHawking Zhang #define regCP_RB0_RPTR_BASE_IDX 0 1996f33ac92fSHawking Zhang #define regCP_RB_RPTR 0x0f60 1997f33ac92fSHawking Zhang #define regCP_RB_RPTR_BASE_IDX 0 1998f33ac92fSHawking Zhang #define regCP_RB_WPTR_DELAY 0x0f61 1999f33ac92fSHawking Zhang #define regCP_RB_WPTR_DELAY_BASE_IDX 0 2000f33ac92fSHawking Zhang #define regCP_RB_WPTR_POLL_CNTL 0x0f62 2001f33ac92fSHawking Zhang #define regCP_RB_WPTR_POLL_CNTL_BASE_IDX 0 2002f33ac92fSHawking Zhang #define regCP_ROQ1_THRESHOLDS 0x0f75 2003f33ac92fSHawking Zhang #define regCP_ROQ1_THRESHOLDS_BASE_IDX 0 2004f33ac92fSHawking Zhang #define regCP_ROQ2_THRESHOLDS 0x0f76 2005f33ac92fSHawking Zhang #define regCP_ROQ2_THRESHOLDS_BASE_IDX 0 2006f33ac92fSHawking Zhang #define regCP_STQ_THRESHOLDS 0x0f77 2007f33ac92fSHawking Zhang #define regCP_STQ_THRESHOLDS_BASE_IDX 0 2008f33ac92fSHawking Zhang #define regCP_MEQ_THRESHOLDS 0x0f79 2009f33ac92fSHawking Zhang #define regCP_MEQ_THRESHOLDS_BASE_IDX 0 2010f33ac92fSHawking Zhang #define regCP_ROQ_AVAIL 0x0f7a 2011f33ac92fSHawking Zhang #define regCP_ROQ_AVAIL_BASE_IDX 0 2012f33ac92fSHawking Zhang #define regCP_STQ_AVAIL 0x0f7b 2013f33ac92fSHawking Zhang #define regCP_STQ_AVAIL_BASE_IDX 0 2014f33ac92fSHawking Zhang #define regCP_ROQ2_AVAIL 0x0f7c 2015f33ac92fSHawking Zhang #define regCP_ROQ2_AVAIL_BASE_IDX 0 2016f33ac92fSHawking Zhang #define regCP_MEQ_AVAIL 0x0f7d 2017f33ac92fSHawking Zhang #define regCP_MEQ_AVAIL_BASE_IDX 0 2018f33ac92fSHawking Zhang #define regCP_CMD_INDEX 0x0f7e 2019f33ac92fSHawking Zhang #define regCP_CMD_INDEX_BASE_IDX 0 2020f33ac92fSHawking Zhang #define regCP_CMD_DATA 0x0f7f 2021f33ac92fSHawking Zhang #define regCP_CMD_DATA_BASE_IDX 0 2022f33ac92fSHawking Zhang #define regCP_ROQ_RB_STAT 0x0f80 2023f33ac92fSHawking Zhang #define regCP_ROQ_RB_STAT_BASE_IDX 0 2024f33ac92fSHawking Zhang #define regCP_ROQ_IB1_STAT 0x0f81 2025f33ac92fSHawking Zhang #define regCP_ROQ_IB1_STAT_BASE_IDX 0 2026f33ac92fSHawking Zhang #define regCP_ROQ_IB2_STAT 0x0f82 2027f33ac92fSHawking Zhang #define regCP_ROQ_IB2_STAT_BASE_IDX 0 2028f33ac92fSHawking Zhang #define regCP_STQ_STAT 0x0f83 2029f33ac92fSHawking Zhang #define regCP_STQ_STAT_BASE_IDX 0 2030f33ac92fSHawking Zhang #define regCP_STQ_WR_STAT 0x0f84 2031f33ac92fSHawking Zhang #define regCP_STQ_WR_STAT_BASE_IDX 0 2032f33ac92fSHawking Zhang #define regCP_MEQ_STAT 0x0f85 2033f33ac92fSHawking Zhang #define regCP_MEQ_STAT_BASE_IDX 0 2034f33ac92fSHawking Zhang #define regCP_ROQ3_THRESHOLDS 0x0f8c 2035f33ac92fSHawking Zhang #define regCP_ROQ3_THRESHOLDS_BASE_IDX 0 2036f33ac92fSHawking Zhang #define regCP_ROQ_DB_STAT 0x0f8d 2037f33ac92fSHawking Zhang #define regCP_ROQ_DB_STAT_BASE_IDX 0 2038f33ac92fSHawking Zhang #define regCP_DEBUG_CNTL 0x0f98 2039f33ac92fSHawking Zhang #define regCP_DEBUG_CNTL_BASE_IDX 0 2040f33ac92fSHawking Zhang #define regCP_DEBUG_DATA 0x0f99 2041f33ac92fSHawking Zhang #define regCP_DEBUG_DATA_BASE_IDX 0 2042f33ac92fSHawking Zhang #define regCP_PRIV_VIOLATION_ADDR 0x0f9a 2043f33ac92fSHawking Zhang #define regCP_PRIV_VIOLATION_ADDR_BASE_IDX 0 2044f33ac92fSHawking Zhang 2045f33ac92fSHawking Zhang 2046f33ac92fSHawking Zhang // addressBlock: gc_padec 2047f33ac92fSHawking Zhang // base address: 0x8800 2048f33ac92fSHawking Zhang #define regVGT_DMA_DATA_FIFO_DEPTH 0x0fcd 2049f33ac92fSHawking Zhang #define regVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX 0 2050f33ac92fSHawking Zhang #define regVGT_DMA_REQ_FIFO_DEPTH 0x0fce 2051f33ac92fSHawking Zhang #define regVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX 0 2052f33ac92fSHawking Zhang #define regVGT_DRAW_INIT_FIFO_DEPTH 0x0fcf 2053f33ac92fSHawking Zhang #define regVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX 0 2054f33ac92fSHawking Zhang #define regVGT_MC_LAT_CNTL 0x0fd6 2055f33ac92fSHawking Zhang #define regVGT_MC_LAT_CNTL_BASE_IDX 0 2056f33ac92fSHawking Zhang #define regIA_UTCL1_STATUS_2 0x0fd7 2057f33ac92fSHawking Zhang #define regIA_UTCL1_STATUS_2_BASE_IDX 0 2058f33ac92fSHawking Zhang #define regWD_CNTL_STATUS 0x0fdf 2059f33ac92fSHawking Zhang #define regWD_CNTL_STATUS_BASE_IDX 0 2060f33ac92fSHawking Zhang #define regCC_GC_PRIM_CONFIG 0x0fe0 2061f33ac92fSHawking Zhang #define regCC_GC_PRIM_CONFIG_BASE_IDX 0 2062f33ac92fSHawking Zhang #define regWD_QOS 0x0fe2 2063f33ac92fSHawking Zhang #define regWD_QOS_BASE_IDX 0 2064f33ac92fSHawking Zhang #define regWD_UTCL1_CNTL 0x0fe3 2065f33ac92fSHawking Zhang #define regWD_UTCL1_CNTL_BASE_IDX 0 2066f33ac92fSHawking Zhang #define regWD_UTCL1_STATUS 0x0fe4 2067f33ac92fSHawking Zhang #define regWD_UTCL1_STATUS_BASE_IDX 0 2068f33ac92fSHawking Zhang #define regIA_UTCL1_CNTL 0x0fe6 2069f33ac92fSHawking Zhang #define regIA_UTCL1_CNTL_BASE_IDX 0 2070f33ac92fSHawking Zhang #define regIA_UTCL1_STATUS 0x0fe7 2071f33ac92fSHawking Zhang #define regIA_UTCL1_STATUS_BASE_IDX 0 2072f33ac92fSHawking Zhang #define regCC_GC_SA_UNIT_DISABLE 0x0fe9 2073f33ac92fSHawking Zhang #define regCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 2074f33ac92fSHawking Zhang #define regGE_RATE_CNTL_1 0x0ff4 2075f33ac92fSHawking Zhang #define regGE_RATE_CNTL_1_BASE_IDX 0 2076f33ac92fSHawking Zhang #define regGE_RATE_CNTL_2 0x0ff5 2077f33ac92fSHawking Zhang #define regGE_RATE_CNTL_2_BASE_IDX 0 2078f33ac92fSHawking Zhang #define regVGT_SYS_CONFIG 0x1003 2079f33ac92fSHawking Zhang #define regVGT_SYS_CONFIG_BASE_IDX 0 2080f33ac92fSHawking Zhang #define regGE_PRIV_CONTROL 0x1004 2081f33ac92fSHawking Zhang #define regGE_PRIV_CONTROL_BASE_IDX 0 2082f33ac92fSHawking Zhang #define regGE_STATUS 0x1005 2083f33ac92fSHawking Zhang #define regGE_STATUS_BASE_IDX 0 2084f33ac92fSHawking Zhang #define regVGT_GS_MAX_WAVE_ID 0x1009 2085f33ac92fSHawking Zhang #define regVGT_GS_MAX_WAVE_ID_BASE_IDX 0 2086f33ac92fSHawking Zhang #define regGFX_PIPE_CONTROL 0x100d 2087f33ac92fSHawking Zhang #define regGFX_PIPE_CONTROL_BASE_IDX 0 2088f33ac92fSHawking Zhang #define regCC_GC_SHADER_ARRAY_CONFIG 0x100f 2089f33ac92fSHawking Zhang #define regCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX 0 2090f33ac92fSHawking Zhang #define regGE2_SE_CNTL_STATUS 0x1011 2091f33ac92fSHawking Zhang #define regGE2_SE_CNTL_STATUS_BASE_IDX 0 2092f33ac92fSHawking Zhang #define regGE_SPI_IF_SAFE_REG 0x1018 2093f33ac92fSHawking Zhang #define regGE_SPI_IF_SAFE_REG_BASE_IDX 0 2094f33ac92fSHawking Zhang #define regGE_PA_IF_SAFE_REG 0x1019 2095f33ac92fSHawking Zhang #define regGE_PA_IF_SAFE_REG_BASE_IDX 0 2096f33ac92fSHawking Zhang #define regPA_CL_CNTL_STATUS 0x1024 2097f33ac92fSHawking Zhang #define regPA_CL_CNTL_STATUS_BASE_IDX 0 2098f33ac92fSHawking Zhang #define regPA_CL_ENHANCE 0x1025 2099f33ac92fSHawking Zhang #define regPA_CL_ENHANCE_BASE_IDX 0 2100f33ac92fSHawking Zhang #define regPA_SU_CNTL_STATUS 0x1034 2101f33ac92fSHawking Zhang #define regPA_SU_CNTL_STATUS_BASE_IDX 0 2102f33ac92fSHawking Zhang #define regPA_SC_FIFO_DEPTH_CNTL 0x1035 2103f33ac92fSHawking Zhang #define regPA_SC_FIFO_DEPTH_CNTL_BASE_IDX 0 2104f33ac92fSHawking Zhang 2105f33ac92fSHawking Zhang 2106f33ac92fSHawking Zhang // addressBlock: gc_sqdec 2107f33ac92fSHawking Zhang // base address: 0x8c00 2108f33ac92fSHawking Zhang #define regSQ_CONFIG 0x10a0 2109f33ac92fSHawking Zhang #define regSQ_CONFIG_BASE_IDX 0 2110f33ac92fSHawking Zhang #define regSQC_CONFIG 0x10a1 2111f33ac92fSHawking Zhang #define regSQC_CONFIG_BASE_IDX 0 2112f33ac92fSHawking Zhang #define regLDS_CONFIG 0x10a2 2113f33ac92fSHawking Zhang #define regLDS_CONFIG_BASE_IDX 0 2114f33ac92fSHawking Zhang #define regSQ_RANDOM_WAVE_PRI 0x10a3 2115f33ac92fSHawking Zhang #define regSQ_RANDOM_WAVE_PRI_BASE_IDX 0 2116f33ac92fSHawking Zhang #define regSQG_STATUS 0x10a4 2117f33ac92fSHawking Zhang #define regSQG_STATUS_BASE_IDX 0 2118f33ac92fSHawking Zhang #define regSQ_FIFO_SIZES 0x10a5 2119f33ac92fSHawking Zhang #define regSQ_FIFO_SIZES_BASE_IDX 0 2120f33ac92fSHawking Zhang #define regSQ_DSM_CNTL 0x10a6 2121f33ac92fSHawking Zhang #define regSQ_DSM_CNTL_BASE_IDX 0 2122f33ac92fSHawking Zhang #define regSQ_DSM_CNTL2 0x10a7 2123f33ac92fSHawking Zhang #define regSQ_DSM_CNTL2_BASE_IDX 0 2124f33ac92fSHawking Zhang #define regSP_CONFIG 0x10ab 2125f33ac92fSHawking Zhang #define regSP_CONFIG_BASE_IDX 0 2126f33ac92fSHawking Zhang #define regSQ_ARB_CONFIG 0x10ac 2127f33ac92fSHawking Zhang #define regSQ_ARB_CONFIG_BASE_IDX 0 2128f33ac92fSHawking Zhang #define regSQ_DEBUG_HOST_TRAP_STATUS 0x10b6 2129f33ac92fSHawking Zhang #define regSQ_DEBUG_HOST_TRAP_STATUS_BASE_IDX 0 2130f33ac92fSHawking Zhang #define regSQG_GL1H_STATUS 0x10b9 2131f33ac92fSHawking Zhang #define regSQG_GL1H_STATUS_BASE_IDX 0 2132f33ac92fSHawking Zhang #define regSQG_CONFIG 0x10ba 2133f33ac92fSHawking Zhang #define regSQG_CONFIG_BASE_IDX 0 2134f33ac92fSHawking Zhang #define regSQ_PERF_SNAPSHOT_CTRL 0x10bb 2135f33ac92fSHawking Zhang #define regSQ_PERF_SNAPSHOT_CTRL_BASE_IDX 0 2136f33ac92fSHawking Zhang #define regCC_GC_SHADER_RATE_CONFIG 0x10bc 2137f33ac92fSHawking Zhang #define regCC_GC_SHADER_RATE_CONFIG_BASE_IDX 0 2138f33ac92fSHawking Zhang #define regSQ_INTERRUPT_AUTO_MASK 0x10be 2139f33ac92fSHawking Zhang #define regSQ_INTERRUPT_AUTO_MASK_BASE_IDX 0 2140f33ac92fSHawking Zhang #define regSQ_INTERRUPT_MSG_CTRL 0x10bf 2141f33ac92fSHawking Zhang #define regSQ_INTERRUPT_MSG_CTRL_BASE_IDX 0 2142f33ac92fSHawking Zhang #define regSQ_WATCH0_ADDR_H 0x10d0 2143f33ac92fSHawking Zhang #define regSQ_WATCH0_ADDR_H_BASE_IDX 0 2144f33ac92fSHawking Zhang #define regSQ_WATCH0_ADDR_L 0x10d1 2145f33ac92fSHawking Zhang #define regSQ_WATCH0_ADDR_L_BASE_IDX 0 2146f33ac92fSHawking Zhang #define regSQ_WATCH0_CNTL 0x10d2 2147f33ac92fSHawking Zhang #define regSQ_WATCH0_CNTL_BASE_IDX 0 2148f33ac92fSHawking Zhang #define regSQ_WATCH1_ADDR_H 0x10d3 2149f33ac92fSHawking Zhang #define regSQ_WATCH1_ADDR_H_BASE_IDX 0 2150f33ac92fSHawking Zhang #define regSQ_WATCH1_ADDR_L 0x10d4 2151f33ac92fSHawking Zhang #define regSQ_WATCH1_ADDR_L_BASE_IDX 0 2152f33ac92fSHawking Zhang #define regSQ_WATCH1_CNTL 0x10d5 2153f33ac92fSHawking Zhang #define regSQ_WATCH1_CNTL_BASE_IDX 0 2154f33ac92fSHawking Zhang #define regSQ_WATCH2_ADDR_H 0x10d6 2155f33ac92fSHawking Zhang #define regSQ_WATCH2_ADDR_H_BASE_IDX 0 2156f33ac92fSHawking Zhang #define regSQ_WATCH2_ADDR_L 0x10d7 2157f33ac92fSHawking Zhang #define regSQ_WATCH2_ADDR_L_BASE_IDX 0 2158f33ac92fSHawking Zhang #define regSQ_WATCH2_CNTL 0x10d8 2159f33ac92fSHawking Zhang #define regSQ_WATCH2_CNTL_BASE_IDX 0 2160f33ac92fSHawking Zhang #define regSQ_WATCH3_ADDR_H 0x10d9 2161f33ac92fSHawking Zhang #define regSQ_WATCH3_ADDR_H_BASE_IDX 0 2162f33ac92fSHawking Zhang #define regSQ_WATCH3_ADDR_L 0x10da 2163f33ac92fSHawking Zhang #define regSQ_WATCH3_ADDR_L_BASE_IDX 0 2164f33ac92fSHawking Zhang #define regSQ_WATCH3_CNTL 0x10db 2165f33ac92fSHawking Zhang #define regSQ_WATCH3_CNTL_BASE_IDX 0 2166f33ac92fSHawking Zhang #define regSQ_IND_INDEX 0x1118 2167f33ac92fSHawking Zhang #define regSQ_IND_INDEX_BASE_IDX 0 2168f33ac92fSHawking Zhang #define regSQ_IND_DATA 0x1119 2169f33ac92fSHawking Zhang #define regSQ_IND_DATA_BASE_IDX 0 2170f33ac92fSHawking Zhang #define regSQ_CMD 0x111b 2171f33ac92fSHawking Zhang #define regSQ_CMD_BASE_IDX 0 2172f33ac92fSHawking Zhang 2173f33ac92fSHawking Zhang 2174f33ac92fSHawking Zhang // addressBlock: gc_shsdec 2175f33ac92fSHawking Zhang // base address: 0x9000 2176f33ac92fSHawking Zhang #define regSX_DEBUG_1 0x11b8 2177f33ac92fSHawking Zhang #define regSX_DEBUG_1_BASE_IDX 0 2178f33ac92fSHawking Zhang #define regSPI_PS_MAX_WAVE_ID 0x11da 2179f33ac92fSHawking Zhang #define regSPI_PS_MAX_WAVE_ID_BASE_IDX 0 2180f33ac92fSHawking Zhang #define regSPI_GFX_CNTL 0x11dc 2181f33ac92fSHawking Zhang #define regSPI_GFX_CNTL_BASE_IDX 0 2182f33ac92fSHawking Zhang #define regSPI_DSM_CNTL 0x11e3 2183f33ac92fSHawking Zhang #define regSPI_DSM_CNTL_BASE_IDX 0 2184f33ac92fSHawking Zhang #define regSPI_DSM_CNTL2 0x11e4 2185f33ac92fSHawking Zhang #define regSPI_DSM_CNTL2_BASE_IDX 0 2186f33ac92fSHawking Zhang #define regSPI_EDC_CNT 0x11e5 2187f33ac92fSHawking Zhang #define regSPI_EDC_CNT_BASE_IDX 0 2188f33ac92fSHawking Zhang #define regSPI_CONFIG_PS_CU_EN 0x11f2 2189f33ac92fSHawking Zhang #define regSPI_CONFIG_PS_CU_EN_BASE_IDX 0 2190f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_CNTL 0x124a 2191f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_CNTL_BASE_IDX 0 2192f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_LIMIT_0 0x124b 2193f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_LIMIT_0_BASE_IDX 0 2194f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_LIMIT_1 0x124c 2195f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_LIMIT_1_BASE_IDX 0 2196f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_LIMIT_2 0x124d 2197f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_LIMIT_2_BASE_IDX 0 2198f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_LIMIT_3 0x124e 2199f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_LIMIT_3_BASE_IDX 0 2200f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_LIMIT_4 0x124f 2201f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_LIMIT_4_BASE_IDX 0 2202f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_LIMIT_5 0x1250 2203f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_LIMIT_5_BASE_IDX 0 2204f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_0 0x1255 2205f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_0_BASE_IDX 0 2206f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_2 0x1257 2207f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_2_BASE_IDX 0 2208f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_4 0x1259 2209f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_4_BASE_IDX 0 2210f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_6 0x125b 2211f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_6_BASE_IDX 0 2212f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_7 0x125c 2213f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_7_BASE_IDX 0 2214f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_9 0x125e 2215f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_9_BASE_IDX 0 2216f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_11 0x1260 2217f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_11_BASE_IDX 0 2218f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_13 0x1262 2219f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_13_BASE_IDX 0 2220f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_14 0x1263 2221f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_14_BASE_IDX 0 2222f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_15 0x1264 2223f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_15_BASE_IDX 0 2224f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_16 0x1265 2225f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_16_BASE_IDX 0 2226f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_17 0x1266 2227f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_17_BASE_IDX 0 2228f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_18 0x1267 2229f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_18_BASE_IDX 0 2230f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_19 0x1268 2231f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_19_BASE_IDX 0 2232f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_20 0x1269 2233f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_20_BASE_IDX 0 2234f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_21 0x126b 2235f33ac92fSHawking Zhang #define regSPI_WF_LIFETIME_STATUS_21_BASE_IDX 0 2236f33ac92fSHawking Zhang #define regSPI_LB_CTR_CTRL 0x1274 2237f33ac92fSHawking Zhang #define regSPI_LB_CTR_CTRL_BASE_IDX 0 2238f33ac92fSHawking Zhang #define regSPI_LB_WGP_MASK 0x1275 2239f33ac92fSHawking Zhang #define regSPI_LB_WGP_MASK_BASE_IDX 0 2240f33ac92fSHawking Zhang #define regSPI_LB_DATA_REG 0x1276 2241f33ac92fSHawking Zhang #define regSPI_LB_DATA_REG_BASE_IDX 0 2242f33ac92fSHawking Zhang #define regSPI_PG_ENABLE_STATIC_WGP_MASK 0x1277 2243f33ac92fSHawking Zhang #define regSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX 0 2244f33ac92fSHawking Zhang #define regSPI_GDS_CREDITS 0x1278 2245f33ac92fSHawking Zhang #define regSPI_GDS_CREDITS_BASE_IDX 0 2246f33ac92fSHawking Zhang #define regSPI_SX_EXPORT_BUFFER_SIZES 0x1279 2247f33ac92fSHawking Zhang #define regSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX 0 2248f33ac92fSHawking Zhang #define regSPI_SX_SCOREBOARD_BUFFER_SIZES 0x127a 2249f33ac92fSHawking Zhang #define regSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX 0 2250f33ac92fSHawking Zhang #define regSPI_CSQ_WF_ACTIVE_STATUS 0x127b 2251f33ac92fSHawking Zhang #define regSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX 0 2252f33ac92fSHawking Zhang #define regSPI_CSQ_WF_ACTIVE_COUNT_0 0x127c 2253f33ac92fSHawking Zhang #define regSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX 0 2254f33ac92fSHawking Zhang #define regSPI_CSQ_WF_ACTIVE_COUNT_1 0x127d 2255f33ac92fSHawking Zhang #define regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX 0 2256f33ac92fSHawking Zhang #define regSPI_CSQ_WF_ACTIVE_COUNT_2 0x127e 2257f33ac92fSHawking Zhang #define regSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX 0 2258f33ac92fSHawking Zhang #define regSPI_CSQ_WF_ACTIVE_COUNT_3 0x127f 2259f33ac92fSHawking Zhang #define regSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX 0 2260f33ac92fSHawking Zhang #define regSPI_LB_DATA_WAVES 0x1284 2261f33ac92fSHawking Zhang #define regSPI_LB_DATA_WAVES_BASE_IDX 0 2262f33ac92fSHawking Zhang #define regSPI_P0_TRAP_SCREEN_PSBA_LO 0x128c 2263f33ac92fSHawking Zhang #define regSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 2264f33ac92fSHawking Zhang #define regSPI_P0_TRAP_SCREEN_PSBA_HI 0x128d 2265f33ac92fSHawking Zhang #define regSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 2266f33ac92fSHawking Zhang #define regSPI_P0_TRAP_SCREEN_PSMA_LO 0x128e 2267f33ac92fSHawking Zhang #define regSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 2268f33ac92fSHawking Zhang #define regSPI_P0_TRAP_SCREEN_PSMA_HI 0x128f 2269f33ac92fSHawking Zhang #define regSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 2270f33ac92fSHawking Zhang #define regSPI_P0_TRAP_SCREEN_GPR_MIN 0x1290 2271f33ac92fSHawking Zhang #define regSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 2272f33ac92fSHawking Zhang #define regSPI_P1_TRAP_SCREEN_PSBA_LO 0x1291 2273f33ac92fSHawking Zhang #define regSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 2274f33ac92fSHawking Zhang #define regSPI_P1_TRAP_SCREEN_PSBA_HI 0x1292 2275f33ac92fSHawking Zhang #define regSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 2276f33ac92fSHawking Zhang #define regSPI_P1_TRAP_SCREEN_PSMA_LO 0x1293 2277f33ac92fSHawking Zhang #define regSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 2278f33ac92fSHawking Zhang #define regSPI_P1_TRAP_SCREEN_PSMA_HI 0x1294 2279f33ac92fSHawking Zhang #define regSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 2280f33ac92fSHawking Zhang #define regSPI_P1_TRAP_SCREEN_GPR_MIN 0x1295 2281f33ac92fSHawking Zhang #define regSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 2282f33ac92fSHawking Zhang 2283f33ac92fSHawking Zhang 2284f33ac92fSHawking Zhang // addressBlock: gc_tpdec 2285f33ac92fSHawking Zhang // base address: 0x9400 2286f33ac92fSHawking Zhang #define regTD_STATUS 0x12c6 2287f33ac92fSHawking Zhang #define regTD_STATUS_BASE_IDX 0 2288f33ac92fSHawking Zhang #define regTD_DSM_CNTL 0x12cf 2289f33ac92fSHawking Zhang #define regTD_DSM_CNTL_BASE_IDX 0 2290f33ac92fSHawking Zhang #define regTD_DSM_CNTL2 0x12d0 2291f33ac92fSHawking Zhang #define regTD_DSM_CNTL2_BASE_IDX 0 2292f33ac92fSHawking Zhang #define regTD_SCRATCH 0x12d3 2293f33ac92fSHawking Zhang #define regTD_SCRATCH_BASE_IDX 0 2294f33ac92fSHawking Zhang #define regTA_CNTL 0x12e1 2295f33ac92fSHawking Zhang #define regTA_CNTL_BASE_IDX 0 2296f33ac92fSHawking Zhang #define regTA_CNTL_AUX 0x12e2 2297f33ac92fSHawking Zhang #define regTA_CNTL_AUX_BASE_IDX 0 2298f33ac92fSHawking Zhang #define regTA_CNTL2 0x12e5 2299f33ac92fSHawking Zhang #define regTA_CNTL2_BASE_IDX 0 2300f33ac92fSHawking Zhang #define regTA_STATUS 0x12e8 2301f33ac92fSHawking Zhang #define regTA_STATUS_BASE_IDX 0 2302f33ac92fSHawking Zhang #define regTA_SCRATCH 0x1304 2303f33ac92fSHawking Zhang #define regTA_SCRATCH_BASE_IDX 0 2304f33ac92fSHawking Zhang 2305f33ac92fSHawking Zhang 2306f33ac92fSHawking Zhang // addressBlock: gc_gdsdec 2307f33ac92fSHawking Zhang // base address: 0x9700 2308f33ac92fSHawking Zhang #define regGDS_CONFIG 0x1360 2309f33ac92fSHawking Zhang #define regGDS_CONFIG_BASE_IDX 0 2310f33ac92fSHawking Zhang #define regGDS_CNTL_STATUS 0x1361 2311f33ac92fSHawking Zhang #define regGDS_CNTL_STATUS_BASE_IDX 0 2312f33ac92fSHawking Zhang #define regGDS_ENHANCE 0x1362 2313f33ac92fSHawking Zhang #define regGDS_ENHANCE_BASE_IDX 0 2314f33ac92fSHawking Zhang #define regGDS_PROTECTION_FAULT 0x1363 2315f33ac92fSHawking Zhang #define regGDS_PROTECTION_FAULT_BASE_IDX 0 2316f33ac92fSHawking Zhang #define regGDS_VM_PROTECTION_FAULT 0x1364 2317f33ac92fSHawking Zhang #define regGDS_VM_PROTECTION_FAULT_BASE_IDX 0 2318f33ac92fSHawking Zhang #define regGDS_EDC_CNT 0x1365 2319f33ac92fSHawking Zhang #define regGDS_EDC_CNT_BASE_IDX 0 2320f33ac92fSHawking Zhang #define regGDS_EDC_GRBM_CNT 0x1366 2321f33ac92fSHawking Zhang #define regGDS_EDC_GRBM_CNT_BASE_IDX 0 2322f33ac92fSHawking Zhang #define regGDS_EDC_OA_DED 0x1367 2323f33ac92fSHawking Zhang #define regGDS_EDC_OA_DED_BASE_IDX 0 2324f33ac92fSHawking Zhang #define regGDS_DSM_CNTL 0x136a 2325f33ac92fSHawking Zhang #define regGDS_DSM_CNTL_BASE_IDX 0 2326f33ac92fSHawking Zhang #define regGDS_EDC_OA_PHY_CNT 0x136b 2327f33ac92fSHawking Zhang #define regGDS_EDC_OA_PHY_CNT_BASE_IDX 0 2328f33ac92fSHawking Zhang #define regGDS_EDC_OA_PIPE_CNT 0x136c 2329f33ac92fSHawking Zhang #define regGDS_EDC_OA_PIPE_CNT_BASE_IDX 0 2330f33ac92fSHawking Zhang #define regGDS_DSM_CNTL2 0x136d 2331f33ac92fSHawking Zhang #define regGDS_DSM_CNTL2_BASE_IDX 0 2332f33ac92fSHawking Zhang 2333f33ac92fSHawking Zhang 2334f33ac92fSHawking Zhang // addressBlock: gc_rbdec 2335f33ac92fSHawking Zhang // base address: 0x9800 2336f33ac92fSHawking Zhang #define regDB_DEBUG 0x13ac 2337f33ac92fSHawking Zhang #define regDB_DEBUG_BASE_IDX 0 2338f33ac92fSHawking Zhang #define regDB_DEBUG2 0x13ad 2339f33ac92fSHawking Zhang #define regDB_DEBUG2_BASE_IDX 0 2340f33ac92fSHawking Zhang #define regDB_DEBUG3 0x13ae 2341f33ac92fSHawking Zhang #define regDB_DEBUG3_BASE_IDX 0 2342f33ac92fSHawking Zhang #define regDB_DEBUG4 0x13af 2343f33ac92fSHawking Zhang #define regDB_DEBUG4_BASE_IDX 0 2344f33ac92fSHawking Zhang #define regDB_ETILE_STUTTER_CONTROL 0x13b0 2345f33ac92fSHawking Zhang #define regDB_ETILE_STUTTER_CONTROL_BASE_IDX 0 2346f33ac92fSHawking Zhang #define regDB_LTILE_STUTTER_CONTROL 0x13b1 2347f33ac92fSHawking Zhang #define regDB_LTILE_STUTTER_CONTROL_BASE_IDX 0 2348f33ac92fSHawking Zhang #define regDB_EQUAD_STUTTER_CONTROL 0x13b2 2349f33ac92fSHawking Zhang #define regDB_EQUAD_STUTTER_CONTROL_BASE_IDX 0 2350f33ac92fSHawking Zhang #define regDB_LQUAD_STUTTER_CONTROL 0x13b3 2351f33ac92fSHawking Zhang #define regDB_LQUAD_STUTTER_CONTROL_BASE_IDX 0 2352f33ac92fSHawking Zhang #define regDB_CREDIT_LIMIT 0x13b4 2353f33ac92fSHawking Zhang #define regDB_CREDIT_LIMIT_BASE_IDX 0 2354f33ac92fSHawking Zhang #define regDB_WATERMARKS 0x13b5 2355f33ac92fSHawking Zhang #define regDB_WATERMARKS_BASE_IDX 0 2356f33ac92fSHawking Zhang #define regDB_SUBTILE_CONTROL 0x13b6 2357f33ac92fSHawking Zhang #define regDB_SUBTILE_CONTROL_BASE_IDX 0 2358f33ac92fSHawking Zhang #define regDB_FREE_CACHELINES 0x13b7 2359f33ac92fSHawking Zhang #define regDB_FREE_CACHELINES_BASE_IDX 0 2360f33ac92fSHawking Zhang #define regDB_FIFO_DEPTH1 0x13b8 2361f33ac92fSHawking Zhang #define regDB_FIFO_DEPTH1_BASE_IDX 0 2362f33ac92fSHawking Zhang #define regDB_FIFO_DEPTH2 0x13b9 2363f33ac92fSHawking Zhang #define regDB_FIFO_DEPTH2_BASE_IDX 0 2364f33ac92fSHawking Zhang #define regDB_LAST_OF_BURST_CONFIG 0x13ba 2365f33ac92fSHawking Zhang #define regDB_LAST_OF_BURST_CONFIG_BASE_IDX 0 2366f33ac92fSHawking Zhang #define regDB_RING_CONTROL 0x13bb 2367f33ac92fSHawking Zhang #define regDB_RING_CONTROL_BASE_IDX 0 2368f33ac92fSHawking Zhang #define regDB_MEM_ARB_WATERMARKS 0x13bc 2369f33ac92fSHawking Zhang #define regDB_MEM_ARB_WATERMARKS_BASE_IDX 0 2370f33ac92fSHawking Zhang #define regDB_FIFO_DEPTH3 0x13bd 2371f33ac92fSHawking Zhang #define regDB_FIFO_DEPTH3_BASE_IDX 0 2372f33ac92fSHawking Zhang #define regDB_DEBUG6 0x13be 2373f33ac92fSHawking Zhang #define regDB_DEBUG6_BASE_IDX 0 2374f33ac92fSHawking Zhang #define regDB_EXCEPTION_CONTROL 0x13bf 2375f33ac92fSHawking Zhang #define regDB_EXCEPTION_CONTROL_BASE_IDX 0 2376f33ac92fSHawking Zhang #define regDB_DEBUG7 0x13d0 2377f33ac92fSHawking Zhang #define regDB_DEBUG7_BASE_IDX 0 2378f33ac92fSHawking Zhang #define regDB_DEBUG5 0x13d1 2379f33ac92fSHawking Zhang #define regDB_DEBUG5_BASE_IDX 0 2380f33ac92fSHawking Zhang #define regDB_FGCG_SRAMS_CLK_CTRL 0x13d7 2381f33ac92fSHawking Zhang #define regDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX 0 2382f33ac92fSHawking Zhang #define regDB_FGCG_INTERFACES_CLK_CTRL 0x13d8 2383f33ac92fSHawking Zhang #define regDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX 0 2384f33ac92fSHawking Zhang #define regDB_FIFO_DEPTH4 0x13d9 2385f33ac92fSHawking Zhang #define regDB_FIFO_DEPTH4_BASE_IDX 0 2386f33ac92fSHawking Zhang #define regCC_RB_REDUNDANCY 0x13dc 2387f33ac92fSHawking Zhang #define regCC_RB_REDUNDANCY_BASE_IDX 0 2388f33ac92fSHawking Zhang #define regCC_RB_BACKEND_DISABLE 0x13dd 2389f33ac92fSHawking Zhang #define regCC_RB_BACKEND_DISABLE_BASE_IDX 0 2390f33ac92fSHawking Zhang #define regGB_ADDR_CONFIG 0x13de 2391f33ac92fSHawking Zhang #define regGB_ADDR_CONFIG_BASE_IDX 0 2392f33ac92fSHawking Zhang #define regGB_BACKEND_MAP 0x13df 2393f33ac92fSHawking Zhang #define regGB_BACKEND_MAP_BASE_IDX 0 2394f33ac92fSHawking Zhang #define regGB_GPU_ID 0x13e0 2395f33ac92fSHawking Zhang #define regGB_GPU_ID_BASE_IDX 0 2396f33ac92fSHawking Zhang #define regCC_RB_DAISY_CHAIN 0x13e1 2397f33ac92fSHawking Zhang #define regCC_RB_DAISY_CHAIN_BASE_IDX 0 2398f33ac92fSHawking Zhang #define regGB_ADDR_CONFIG_READ 0x13e2 2399f33ac92fSHawking Zhang #define regGB_ADDR_CONFIG_READ_BASE_IDX 0 2400f33ac92fSHawking Zhang #define regCB_HW_CONTROL_4 0x1422 2401f33ac92fSHawking Zhang #define regCB_HW_CONTROL_4_BASE_IDX 0 2402f33ac92fSHawking Zhang #define regCB_HW_CONTROL_3 0x1423 2403f33ac92fSHawking Zhang #define regCB_HW_CONTROL_3_BASE_IDX 0 2404f33ac92fSHawking Zhang #define regCB_HW_CONTROL 0x1424 2405f33ac92fSHawking Zhang #define regCB_HW_CONTROL_BASE_IDX 0 2406f33ac92fSHawking Zhang #define regCB_HW_CONTROL_1 0x1425 2407f33ac92fSHawking Zhang #define regCB_HW_CONTROL_1_BASE_IDX 0 2408f33ac92fSHawking Zhang #define regCB_HW_CONTROL_2 0x1426 2409f33ac92fSHawking Zhang #define regCB_HW_CONTROL_2_BASE_IDX 0 2410f33ac92fSHawking Zhang #define regCB_DCC_CONFIG 0x1427 2411f33ac92fSHawking Zhang #define regCB_DCC_CONFIG_BASE_IDX 0 2412f33ac92fSHawking Zhang #define regCB_HW_MEM_ARBITER_RD 0x1428 2413f33ac92fSHawking Zhang #define regCB_HW_MEM_ARBITER_RD_BASE_IDX 0 2414f33ac92fSHawking Zhang #define regCB_HW_MEM_ARBITER_WR 0x1429 2415f33ac92fSHawking Zhang #define regCB_HW_MEM_ARBITER_WR_BASE_IDX 0 2416f33ac92fSHawking Zhang #define regCB_FGCG_SRAM_OVERRIDE 0x142a 2417f33ac92fSHawking Zhang #define regCB_FGCG_SRAM_OVERRIDE_BASE_IDX 0 2418f33ac92fSHawking Zhang #define regCB_DCC_CONFIG2 0x142b 2419f33ac92fSHawking Zhang #define regCB_DCC_CONFIG2_BASE_IDX 0 2420f33ac92fSHawking Zhang #define regCHICKEN_BITS 0x142d 2421f33ac92fSHawking Zhang #define regCHICKEN_BITS_BASE_IDX 0 2422f33ac92fSHawking Zhang #define regCB_CACHE_EVICT_POINTS 0x142e 2423f33ac92fSHawking Zhang #define regCB_CACHE_EVICT_POINTS_BASE_IDX 0 2424f33ac92fSHawking Zhang 2425f33ac92fSHawking Zhang 2426f33ac92fSHawking Zhang // addressBlock: gc_gceadec 2427f33ac92fSHawking Zhang // base address: 0xa800 2428f33ac92fSHawking Zhang #define regGCEA_DRAM_RD_CLI2GRP_MAP0 0x17a0 2429f33ac92fSHawking Zhang #define regGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 2430f33ac92fSHawking Zhang #define regGCEA_DRAM_RD_CLI2GRP_MAP1 0x17a1 2431f33ac92fSHawking Zhang #define regGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 2432f33ac92fSHawking Zhang #define regGCEA_DRAM_WR_CLI2GRP_MAP0 0x17a2 2433f33ac92fSHawking Zhang #define regGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 2434f33ac92fSHawking Zhang #define regGCEA_DRAM_WR_CLI2GRP_MAP1 0x17a3 2435f33ac92fSHawking Zhang #define regGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 2436f33ac92fSHawking Zhang #define regGCEA_DRAM_RD_GRP2VC_MAP 0x17a4 2437f33ac92fSHawking Zhang #define regGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 2438f33ac92fSHawking Zhang #define regGCEA_DRAM_WR_GRP2VC_MAP 0x17a5 2439f33ac92fSHawking Zhang #define regGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 2440f33ac92fSHawking Zhang #define regGCEA_DRAM_RD_LAZY 0x17a6 2441f33ac92fSHawking Zhang #define regGCEA_DRAM_RD_LAZY_BASE_IDX 0 2442f33ac92fSHawking Zhang #define regGCEA_DRAM_WR_LAZY 0x17a7 2443f33ac92fSHawking Zhang #define regGCEA_DRAM_WR_LAZY_BASE_IDX 0 2444f33ac92fSHawking Zhang #define regGCEA_DRAM_RD_CAM_CNTL 0x17a8 2445f33ac92fSHawking Zhang #define regGCEA_DRAM_RD_CAM_CNTL_BASE_IDX 0 2446f33ac92fSHawking Zhang #define regGCEA_DRAM_WR_CAM_CNTL 0x17a9 2447f33ac92fSHawking Zhang #define regGCEA_DRAM_WR_CAM_CNTL_BASE_IDX 0 2448f33ac92fSHawking Zhang #define regGCEA_DRAM_PAGE_BURST 0x17aa 2449f33ac92fSHawking Zhang #define regGCEA_DRAM_PAGE_BURST_BASE_IDX 0 2450f33ac92fSHawking Zhang #define regGCEA_DRAM_RD_PRI_AGE 0x17ab 2451f33ac92fSHawking Zhang #define regGCEA_DRAM_RD_PRI_AGE_BASE_IDX 0 2452f33ac92fSHawking Zhang #define regGCEA_DRAM_WR_PRI_AGE 0x17ac 2453f33ac92fSHawking Zhang #define regGCEA_DRAM_WR_PRI_AGE_BASE_IDX 0 2454f33ac92fSHawking Zhang #define regGCEA_DRAM_RD_PRI_QUEUING 0x17ad 2455f33ac92fSHawking Zhang #define regGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX 0 2456f33ac92fSHawking Zhang #define regGCEA_DRAM_WR_PRI_QUEUING 0x17ae 2457f33ac92fSHawking Zhang #define regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX 0 2458f33ac92fSHawking Zhang #define regGCEA_DRAM_RD_PRI_FIXED 0x17af 2459f33ac92fSHawking Zhang #define regGCEA_DRAM_RD_PRI_FIXED_BASE_IDX 0 2460f33ac92fSHawking Zhang #define regGCEA_DRAM_WR_PRI_FIXED 0x17b0 2461f33ac92fSHawking Zhang #define regGCEA_DRAM_WR_PRI_FIXED_BASE_IDX 0 2462f33ac92fSHawking Zhang #define regGCEA_DRAM_RD_PRI_URGENCY 0x17b1 2463f33ac92fSHawking Zhang #define regGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX 0 2464f33ac92fSHawking Zhang #define regGCEA_DRAM_WR_PRI_URGENCY 0x17b2 2465f33ac92fSHawking Zhang #define regGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX 0 2466f33ac92fSHawking Zhang #define regGCEA_DRAM_RD_PRI_QUANT_PRI1 0x17b3 2467f33ac92fSHawking Zhang #define regGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 2468f33ac92fSHawking Zhang #define regGCEA_DRAM_RD_PRI_QUANT_PRI2 0x17b4 2469f33ac92fSHawking Zhang #define regGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 2470f33ac92fSHawking Zhang #define regGCEA_DRAM_RD_PRI_QUANT_PRI3 0x17b5 2471f33ac92fSHawking Zhang #define regGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 2472f33ac92fSHawking Zhang #define regGCEA_DRAM_WR_PRI_QUANT_PRI1 0x17b6 2473f33ac92fSHawking Zhang #define regGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 2474f33ac92fSHawking Zhang #define regGCEA_DRAM_WR_PRI_QUANT_PRI2 0x17b7 2475f33ac92fSHawking Zhang #define regGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 2476f33ac92fSHawking Zhang #define regGCEA_DRAM_WR_PRI_QUANT_PRI3 0x17b8 2477f33ac92fSHawking Zhang #define regGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 2478f33ac92fSHawking Zhang #define regGCEA_IO_RD_CLI2GRP_MAP0 0x187d 2479f33ac92fSHawking Zhang #define regGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 2480f33ac92fSHawking Zhang #define regGCEA_IO_RD_CLI2GRP_MAP1 0x187e 2481f33ac92fSHawking Zhang #define regGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 2482f33ac92fSHawking Zhang #define regGCEA_IO_WR_CLI2GRP_MAP0 0x187f 2483f33ac92fSHawking Zhang #define regGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 2484f33ac92fSHawking Zhang #define regGCEA_IO_WR_CLI2GRP_MAP1 0x1880 2485f33ac92fSHawking Zhang #define regGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 2486f33ac92fSHawking Zhang #define regGCEA_IO_RD_COMBINE_FLUSH 0x1881 2487f33ac92fSHawking Zhang #define regGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX 0 2488f33ac92fSHawking Zhang #define regGCEA_IO_WR_COMBINE_FLUSH 0x1882 2489f33ac92fSHawking Zhang #define regGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX 0 2490f33ac92fSHawking Zhang #define regGCEA_IO_GROUP_BURST 0x1883 2491f33ac92fSHawking Zhang #define regGCEA_IO_GROUP_BURST_BASE_IDX 0 2492f33ac92fSHawking Zhang #define regGCEA_IO_RD_PRI_AGE 0x1884 2493f33ac92fSHawking Zhang #define regGCEA_IO_RD_PRI_AGE_BASE_IDX 0 2494f33ac92fSHawking Zhang #define regGCEA_IO_WR_PRI_AGE 0x1885 2495f33ac92fSHawking Zhang #define regGCEA_IO_WR_PRI_AGE_BASE_IDX 0 2496f33ac92fSHawking Zhang #define regGCEA_IO_RD_PRI_QUEUING 0x1886 2497f33ac92fSHawking Zhang #define regGCEA_IO_RD_PRI_QUEUING_BASE_IDX 0 2498f33ac92fSHawking Zhang #define regGCEA_IO_WR_PRI_QUEUING 0x1887 2499f33ac92fSHawking Zhang #define regGCEA_IO_WR_PRI_QUEUING_BASE_IDX 0 2500f33ac92fSHawking Zhang #define regGCEA_IO_RD_PRI_FIXED 0x1888 2501f33ac92fSHawking Zhang #define regGCEA_IO_RD_PRI_FIXED_BASE_IDX 0 2502f33ac92fSHawking Zhang #define regGCEA_IO_WR_PRI_FIXED 0x1889 2503f33ac92fSHawking Zhang #define regGCEA_IO_WR_PRI_FIXED_BASE_IDX 0 2504f33ac92fSHawking Zhang #define regGCEA_IO_RD_PRI_URGENCY 0x188a 2505f33ac92fSHawking Zhang #define regGCEA_IO_RD_PRI_URGENCY_BASE_IDX 0 2506f33ac92fSHawking Zhang #define regGCEA_IO_WR_PRI_URGENCY 0x188b 2507f33ac92fSHawking Zhang #define regGCEA_IO_WR_PRI_URGENCY_BASE_IDX 0 2508f33ac92fSHawking Zhang #define regGCEA_IO_RD_PRI_URGENCY_MASKING 0x188c 2509f33ac92fSHawking Zhang #define regGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 2510f33ac92fSHawking Zhang #define regGCEA_IO_WR_PRI_URGENCY_MASKING 0x188d 2511f33ac92fSHawking Zhang #define regGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 2512f33ac92fSHawking Zhang #define regGCEA_IO_RD_PRI_QUANT_PRI1 0x188e 2513f33ac92fSHawking Zhang #define regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 2514f33ac92fSHawking Zhang #define regGCEA_IO_RD_PRI_QUANT_PRI2 0x188f 2515f33ac92fSHawking Zhang #define regGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 2516f33ac92fSHawking Zhang #define regGCEA_IO_RD_PRI_QUANT_PRI3 0x1890 2517f33ac92fSHawking Zhang #define regGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 2518f33ac92fSHawking Zhang #define regGCEA_IO_WR_PRI_QUANT_PRI1 0x1891 2519f33ac92fSHawking Zhang #define regGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 2520f33ac92fSHawking Zhang #define regGCEA_IO_WR_PRI_QUANT_PRI2 0x1892 2521f33ac92fSHawking Zhang #define regGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 2522f33ac92fSHawking Zhang #define regGCEA_IO_WR_PRI_QUANT_PRI3 0x1893 2523f33ac92fSHawking Zhang #define regGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 2524f33ac92fSHawking Zhang #define regGCEA_SDP_ARB_FINAL 0x1896 2525f33ac92fSHawking Zhang #define regGCEA_SDP_ARB_FINAL_BASE_IDX 0 2526f33ac92fSHawking Zhang #define regGCEA_SDP_IO_PRIORITY 0x1899 2527f33ac92fSHawking Zhang #define regGCEA_SDP_IO_PRIORITY_BASE_IDX 0 2528f33ac92fSHawking Zhang #define regGCEA_SDP_CREDITS 0x189a 2529f33ac92fSHawking Zhang #define regGCEA_SDP_CREDITS_BASE_IDX 0 2530f33ac92fSHawking Zhang #define regGCEA_SDP_TAG_RESERVE0 0x189b 2531f33ac92fSHawking Zhang #define regGCEA_SDP_TAG_RESERVE0_BASE_IDX 0 2532f33ac92fSHawking Zhang #define regGCEA_SDP_TAG_RESERVE1 0x189c 2533f33ac92fSHawking Zhang #define regGCEA_SDP_TAG_RESERVE1_BASE_IDX 0 2534f33ac92fSHawking Zhang #define regGCEA_SDP_VCC_RESERVE0 0x189d 2535f33ac92fSHawking Zhang #define regGCEA_SDP_VCC_RESERVE0_BASE_IDX 0 2536f33ac92fSHawking Zhang #define regGCEA_SDP_VCC_RESERVE1 0x189e 2537f33ac92fSHawking Zhang #define regGCEA_SDP_VCC_RESERVE1_BASE_IDX 0 2538f33ac92fSHawking Zhang 2539f33ac92fSHawking Zhang 2540f33ac92fSHawking Zhang // addressBlock: gc_gceadec2 2541f33ac92fSHawking Zhang // base address: 0x9c00 2542f33ac92fSHawking Zhang #define regGCEA_MISC 0x14a2 2543f33ac92fSHawking Zhang #define regGCEA_MISC_BASE_IDX 0 2544f33ac92fSHawking Zhang #define regGCEA_LATENCY_SAMPLING 0x14a3 2545f33ac92fSHawking Zhang #define regGCEA_LATENCY_SAMPLING_BASE_IDX 0 2546f33ac92fSHawking Zhang #define regGCEA_MAM_CTRL2 0x14a9 2547f33ac92fSHawking Zhang #define regGCEA_MAM_CTRL2_BASE_IDX 0 2548f33ac92fSHawking Zhang #define regGCEA_MAM_CTRL 0x14ab 2549f33ac92fSHawking Zhang #define regGCEA_MAM_CTRL_BASE_IDX 0 2550f33ac92fSHawking Zhang #define regGCEA_EDC_CNT 0x14b2 2551f33ac92fSHawking Zhang #define regGCEA_EDC_CNT_BASE_IDX 0 2552f33ac92fSHawking Zhang #define regGCEA_EDC_CNT2 0x14b3 2553f33ac92fSHawking Zhang #define regGCEA_EDC_CNT2_BASE_IDX 0 2554f33ac92fSHawking Zhang #define regGCEA_DSM_CNTL 0x14b4 2555f33ac92fSHawking Zhang #define regGCEA_DSM_CNTL_BASE_IDX 0 2556f33ac92fSHawking Zhang #define regGCEA_DSM_CNTLA 0x14b5 2557f33ac92fSHawking Zhang #define regGCEA_DSM_CNTLA_BASE_IDX 0 2558f33ac92fSHawking Zhang #define regGCEA_DSM_CNTLB 0x14b6 2559f33ac92fSHawking Zhang #define regGCEA_DSM_CNTLB_BASE_IDX 0 2560f33ac92fSHawking Zhang #define regGCEA_DSM_CNTL2 0x14b7 2561f33ac92fSHawking Zhang #define regGCEA_DSM_CNTL2_BASE_IDX 0 2562f33ac92fSHawking Zhang #define regGCEA_DSM_CNTL2A 0x14b8 2563f33ac92fSHawking Zhang #define regGCEA_DSM_CNTL2A_BASE_IDX 0 2564f33ac92fSHawking Zhang #define regGCEA_DSM_CNTL2B 0x14b9 2565f33ac92fSHawking Zhang #define regGCEA_DSM_CNTL2B_BASE_IDX 0 2566f33ac92fSHawking Zhang #define regGCEA_GL2C_XBR_CREDITS 0x14ba 2567f33ac92fSHawking Zhang #define regGCEA_GL2C_XBR_CREDITS_BASE_IDX 0 2568f33ac92fSHawking Zhang #define regGCEA_GL2C_XBR_MAXBURST 0x14bb 2569f33ac92fSHawking Zhang #define regGCEA_GL2C_XBR_MAXBURST_BASE_IDX 0 2570f33ac92fSHawking Zhang #define regGCEA_PROBE_CNTL 0x14bc 2571f33ac92fSHawking Zhang #define regGCEA_PROBE_CNTL_BASE_IDX 0 2572f33ac92fSHawking Zhang #define regGCEA_PROBE_MAP 0x14bd 2573f33ac92fSHawking Zhang #define regGCEA_PROBE_MAP_BASE_IDX 0 2574f33ac92fSHawking Zhang #define regGCEA_ERR_STATUS 0x14be 2575f33ac92fSHawking Zhang #define regGCEA_ERR_STATUS_BASE_IDX 0 2576f33ac92fSHawking Zhang #define regGCEA_MISC2 0x14bf 2577f33ac92fSHawking Zhang #define regGCEA_MISC2_BASE_IDX 0 2578f33ac92fSHawking Zhang 2579f33ac92fSHawking Zhang 2580f33ac92fSHawking Zhang // addressBlock: gc_gceadec3 2581f33ac92fSHawking Zhang // base address: 0x9dc0 2582f33ac92fSHawking Zhang #define regGCEA_RRET_MEM_RESERVE 0x1518 2583f33ac92fSHawking Zhang #define regGCEA_RRET_MEM_RESERVE_BASE_IDX 0 2584f33ac92fSHawking Zhang #define regGCEA_EDC_CNT3 0x151a 2585f33ac92fSHawking Zhang #define regGCEA_EDC_CNT3_BASE_IDX 0 2586f33ac92fSHawking Zhang #define regGCEA_SDP_ENABLE 0x151e 2587f33ac92fSHawking Zhang #define regGCEA_SDP_ENABLE_BASE_IDX 0 2588f33ac92fSHawking Zhang 2589f33ac92fSHawking Zhang 2590f33ac92fSHawking Zhang // addressBlock: gc_spipdec2 2591f33ac92fSHawking Zhang // base address: 0x9c80 2592f33ac92fSHawking Zhang #define regSPI_PQEV_CTRL 0x14c0 2593f33ac92fSHawking Zhang #define regSPI_PQEV_CTRL_BASE_IDX 0 2594f33ac92fSHawking Zhang #define regSPI_EXP_THROTTLE_CTRL 0x14c3 2595f33ac92fSHawking Zhang #define regSPI_EXP_THROTTLE_CTRL_BASE_IDX 0 2596f33ac92fSHawking Zhang 2597f33ac92fSHawking Zhang 2598f33ac92fSHawking Zhang // addressBlock: gc_rmi_rmidec 2599f33ac92fSHawking Zhang // base address: 0x2e200 2600f33ac92fSHawking Zhang #define regRMI_GENERAL_CNTL 0x1880 2601f33ac92fSHawking Zhang #define regRMI_GENERAL_CNTL_BASE_IDX 1 2602f33ac92fSHawking Zhang #define regRMI_GENERAL_CNTL1 0x1881 2603f33ac92fSHawking Zhang #define regRMI_GENERAL_CNTL1_BASE_IDX 1 2604f33ac92fSHawking Zhang #define regRMI_GENERAL_STATUS 0x1882 2605f33ac92fSHawking Zhang #define regRMI_GENERAL_STATUS_BASE_IDX 1 2606f33ac92fSHawking Zhang #define regRMI_SUBBLOCK_STATUS0 0x1883 2607f33ac92fSHawking Zhang #define regRMI_SUBBLOCK_STATUS0_BASE_IDX 1 2608f33ac92fSHawking Zhang #define regRMI_SUBBLOCK_STATUS1 0x1884 2609f33ac92fSHawking Zhang #define regRMI_SUBBLOCK_STATUS1_BASE_IDX 1 2610f33ac92fSHawking Zhang #define regRMI_SUBBLOCK_STATUS2 0x1885 2611f33ac92fSHawking Zhang #define regRMI_SUBBLOCK_STATUS2_BASE_IDX 1 2612f33ac92fSHawking Zhang #define regRMI_SUBBLOCK_STATUS3 0x1886 2613f33ac92fSHawking Zhang #define regRMI_SUBBLOCK_STATUS3_BASE_IDX 1 2614f33ac92fSHawking Zhang #define regRMI_XBAR_CONFIG 0x1887 2615f33ac92fSHawking Zhang #define regRMI_XBAR_CONFIG_BASE_IDX 1 2616f33ac92fSHawking Zhang #define regRMI_PROBE_POP_LOGIC_CNTL 0x1888 2617f33ac92fSHawking Zhang #define regRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX 1 2618f33ac92fSHawking Zhang #define regRMI_UTC_XNACK_N_MISC_CNTL 0x1889 2619f33ac92fSHawking Zhang #define regRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX 1 2620f33ac92fSHawking Zhang #define regRMI_DEMUX_CNTL 0x188a 2621f33ac92fSHawking Zhang #define regRMI_DEMUX_CNTL_BASE_IDX 1 2622f33ac92fSHawking Zhang #define regRMI_UTCL1_CNTL1 0x188b 2623f33ac92fSHawking Zhang #define regRMI_UTCL1_CNTL1_BASE_IDX 1 2624f33ac92fSHawking Zhang #define regRMI_UTCL1_CNTL2 0x188c 2625f33ac92fSHawking Zhang #define regRMI_UTCL1_CNTL2_BASE_IDX 1 2626f33ac92fSHawking Zhang #define regRMI_UTC_UNIT_CONFIG 0x188d 2627f33ac92fSHawking Zhang #define regRMI_UTC_UNIT_CONFIG_BASE_IDX 1 2628f33ac92fSHawking Zhang #define regRMI_TCIW_FORMATTER0_CNTL 0x188e 2629f33ac92fSHawking Zhang #define regRMI_TCIW_FORMATTER0_CNTL_BASE_IDX 1 2630f33ac92fSHawking Zhang #define regRMI_TCIW_FORMATTER1_CNTL 0x188f 2631f33ac92fSHawking Zhang #define regRMI_TCIW_FORMATTER1_CNTL_BASE_IDX 1 2632f33ac92fSHawking Zhang #define regRMI_SCOREBOARD_CNTL 0x1890 2633f33ac92fSHawking Zhang #define regRMI_SCOREBOARD_CNTL_BASE_IDX 1 2634f33ac92fSHawking Zhang #define regRMI_SCOREBOARD_STATUS0 0x1891 2635f33ac92fSHawking Zhang #define regRMI_SCOREBOARD_STATUS0_BASE_IDX 1 2636f33ac92fSHawking Zhang #define regRMI_SCOREBOARD_STATUS1 0x1892 2637f33ac92fSHawking Zhang #define regRMI_SCOREBOARD_STATUS1_BASE_IDX 1 2638f33ac92fSHawking Zhang #define regRMI_SCOREBOARD_STATUS2 0x1893 2639f33ac92fSHawking Zhang #define regRMI_SCOREBOARD_STATUS2_BASE_IDX 1 2640f33ac92fSHawking Zhang #define regRMI_XBAR_ARBITER_CONFIG 0x1894 2641f33ac92fSHawking Zhang #define regRMI_XBAR_ARBITER_CONFIG_BASE_IDX 1 2642f33ac92fSHawking Zhang #define regRMI_XBAR_ARBITER_CONFIG_1 0x1895 2643f33ac92fSHawking Zhang #define regRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX 1 2644f33ac92fSHawking Zhang #define regRMI_CLOCK_CNTRL 0x1896 2645f33ac92fSHawking Zhang #define regRMI_CLOCK_CNTRL_BASE_IDX 1 2646f33ac92fSHawking Zhang #define regRMI_UTCL1_STATUS 0x1897 2647f33ac92fSHawking Zhang #define regRMI_UTCL1_STATUS_BASE_IDX 1 2648f33ac92fSHawking Zhang #define regRMI_RB_GLX_CID_MAP 0x1898 2649f33ac92fSHawking Zhang #define regRMI_RB_GLX_CID_MAP_BASE_IDX 1 2650f33ac92fSHawking Zhang #define regRMI_SPARE 0x189f 2651f33ac92fSHawking Zhang #define regRMI_SPARE_BASE_IDX 1 2652f33ac92fSHawking Zhang #define regRMI_SPARE_1 0x18a0 2653f33ac92fSHawking Zhang #define regRMI_SPARE_1_BASE_IDX 1 2654f33ac92fSHawking Zhang #define regRMI_SPARE_2 0x18a1 2655f33ac92fSHawking Zhang #define regRMI_SPARE_2_BASE_IDX 1 2656f33ac92fSHawking Zhang #define regCC_RMI_REDUNDANCY 0x18a2 2657f33ac92fSHawking Zhang #define regCC_RMI_REDUNDANCY_BASE_IDX 1 2658f33ac92fSHawking Zhang 2659f33ac92fSHawking Zhang 2660f33ac92fSHawking Zhang // addressBlock: gc_pmmdec 2661f33ac92fSHawking Zhang // base address: 0x9f80 2662f33ac92fSHawking Zhang #define regGCR_PIO_CNTL 0x1580 2663f33ac92fSHawking Zhang #define regGCR_PIO_CNTL_BASE_IDX 0 2664f33ac92fSHawking Zhang #define regGCR_PIO_DATA 0x1581 2665f33ac92fSHawking Zhang #define regGCR_PIO_DATA_BASE_IDX 0 2666f33ac92fSHawking Zhang #define regPMM_CNTL 0x1582 2667f33ac92fSHawking Zhang #define regPMM_CNTL_BASE_IDX 0 2668f33ac92fSHawking Zhang #define regPMM_STATUS 0x1583 2669f33ac92fSHawking Zhang #define regPMM_STATUS_BASE_IDX 0 2670f33ac92fSHawking Zhang 2671f33ac92fSHawking Zhang 2672f33ac92fSHawking Zhang // addressBlock: gc_utcl1dec 2673f33ac92fSHawking Zhang // base address: 0x9fb0 2674f33ac92fSHawking Zhang #define regUTCL1_CTRL_1 0x158c 2675f33ac92fSHawking Zhang #define regUTCL1_CTRL_1_BASE_IDX 0 2676f33ac92fSHawking Zhang #define regUTCL1_ALOG 0x158f 2677f33ac92fSHawking Zhang #define regUTCL1_ALOG_BASE_IDX 0 2678f33ac92fSHawking Zhang #define regUTCL1_STATUS 0x1594 2679f33ac92fSHawking Zhang #define regUTCL1_STATUS_BASE_IDX 0 2680f33ac92fSHawking Zhang 2681f33ac92fSHawking Zhang 2682f33ac92fSHawking Zhang // addressBlock: gc_gcvmsharedpfdec 2683f33ac92fSHawking Zhang // base address: 0xa000 2684f33ac92fSHawking Zhang #define regGCMC_VM_NB_TOP_OF_DRAM_SLOT1 0x15a4 2685f33ac92fSHawking Zhang #define regGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0 2686f33ac92fSHawking Zhang #define regGCMC_VM_NB_LOWER_TOP_OF_DRAM2 0x15a5 2687f33ac92fSHawking Zhang #define regGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0 2688f33ac92fSHawking Zhang #define regGCMC_VM_NB_UPPER_TOP_OF_DRAM2 0x15a6 2689f33ac92fSHawking Zhang #define regGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0 2690f33ac92fSHawking Zhang #define regGCMC_VM_FB_OFFSET 0x15a7 2691f33ac92fSHawking Zhang #define regGCMC_VM_FB_OFFSET_BASE_IDX 0 2692f33ac92fSHawking Zhang #define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x15a8 2693f33ac92fSHawking Zhang #define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 2694f33ac92fSHawking Zhang #define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x15a9 2695f33ac92fSHawking Zhang #define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 2696f33ac92fSHawking Zhang #define regGCMC_VM_STEERING 0x15aa 2697f33ac92fSHawking Zhang #define regGCMC_VM_STEERING_BASE_IDX 0 2698f33ac92fSHawking Zhang #define regGCMC_MEM_POWER_LS 0x15ac 2699f33ac92fSHawking Zhang #define regGCMC_MEM_POWER_LS_BASE_IDX 0 2700f33ac92fSHawking Zhang #define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x15ad 2701f33ac92fSHawking Zhang #define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 2702f33ac92fSHawking Zhang #define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x15ae 2703f33ac92fSHawking Zhang #define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0 2704f33ac92fSHawking Zhang #define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START 0x15af 2705f33ac92fSHawking Zhang #define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX 0 2706f33ac92fSHawking Zhang #define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END 0x15b0 2707f33ac92fSHawking Zhang #define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX 0 2708f33ac92fSHawking Zhang #define regGCMC_VM_APT_CNTL 0x15b1 2709f33ac92fSHawking Zhang #define regGCMC_VM_APT_CNTL_BASE_IDX 0 2710f33ac92fSHawking Zhang #define regGCMC_VM_LOCAL_FB_ADDRESS_START 0x15b2 2711f33ac92fSHawking Zhang #define regGCMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX 0 2712f33ac92fSHawking Zhang #define regGCMC_VM_LOCAL_FB_ADDRESS_END 0x15b3 2713f33ac92fSHawking Zhang #define regGCMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX 0 2714f33ac92fSHawking Zhang #define regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL 0x15b4 2715f33ac92fSHawking Zhang #define regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX 0 2716f33ac92fSHawking Zhang #define regGCUTCL2_ICG_CTRL 0x15b5 2717f33ac92fSHawking Zhang #define regGCUTCL2_ICG_CTRL_BASE_IDX 0 2718f33ac92fSHawking Zhang #define regGCUTCL2_CGTT_BUSY_CTRL 0x15b7 2719f33ac92fSHawking Zhang #define regGCUTCL2_CGTT_BUSY_CTRL_BASE_IDX 0 2720f33ac92fSHawking Zhang #define regGCMC_VM_FB_NOALLOC_CNTL 0x15b8 2721f33ac92fSHawking Zhang #define regGCMC_VM_FB_NOALLOC_CNTL_BASE_IDX 0 2722f33ac92fSHawking Zhang #define regGCUTCL2_HARVEST_BYPASS_GROUPS 0x15b9 2723f33ac92fSHawking Zhang #define regGCUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX 0 2724f33ac92fSHawking Zhang #define regGCUTCL2_GROUP_RET_FAULT_STATUS 0x15bb 2725f33ac92fSHawking Zhang #define regGCUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX 0 2726f33ac92fSHawking Zhang 2727f33ac92fSHawking Zhang 2728f33ac92fSHawking Zhang // addressBlock: gc_gcvml2pfdec 2729f33ac92fSHawking Zhang // base address: 0xa070 2730f33ac92fSHawking Zhang #define regGCVM_L2_CNTL 0x15bc 2731f33ac92fSHawking Zhang #define regGCVM_L2_CNTL_BASE_IDX 0 2732f33ac92fSHawking Zhang #define regGCVM_L2_CNTL2 0x15bd 2733f33ac92fSHawking Zhang #define regGCVM_L2_CNTL2_BASE_IDX 0 2734f33ac92fSHawking Zhang #define regGCVM_L2_CNTL3 0x15be 2735f33ac92fSHawking Zhang #define regGCVM_L2_CNTL3_BASE_IDX 0 2736f33ac92fSHawking Zhang #define regGCVM_L2_STATUS 0x15bf 2737f33ac92fSHawking Zhang #define regGCVM_L2_STATUS_BASE_IDX 0 2738f33ac92fSHawking Zhang #define regGCVM_DUMMY_PAGE_FAULT_CNTL 0x15c0 2739f33ac92fSHawking Zhang #define regGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 2740f33ac92fSHawking Zhang #define regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x15c1 2741f33ac92fSHawking Zhang #define regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 2742f33ac92fSHawking Zhang #define regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x15c2 2743f33ac92fSHawking Zhang #define regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 2744f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_CNTL 0x15c3 2745f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_CNTL_BASE_IDX 0 2746f33ac92fSHawking Zhang #define regGCVM_L2_PROTECTION_FAULT_CNTL 0x15c4 2747f33ac92fSHawking Zhang #define regGCVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0 2748f33ac92fSHawking Zhang #define regGCVM_L2_PROTECTION_FAULT_CNTL2 0x15c5 2749f33ac92fSHawking Zhang #define regGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 2750f33ac92fSHawking Zhang #define regGCVM_L2_PROTECTION_FAULT_MM_CNTL3 0x15c6 2751f33ac92fSHawking Zhang #define regGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 2752f33ac92fSHawking Zhang #define regGCVM_L2_PROTECTION_FAULT_MM_CNTL4 0x15c7 2753f33ac92fSHawking Zhang #define regGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 2754f33ac92fSHawking Zhang #define regGCVM_L2_PROTECTION_FAULT_STATUS 0x15c8 2755f33ac92fSHawking Zhang #define regGCVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0 2756f33ac92fSHawking Zhang #define regGCVM_L2_PROTECTION_FAULT_ADDR_LO32 0x15c9 2757f33ac92fSHawking Zhang #define regGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 2758f33ac92fSHawking Zhang #define regGCVM_L2_PROTECTION_FAULT_ADDR_HI32 0x15ca 2759f33ac92fSHawking Zhang #define regGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 2760f33ac92fSHawking Zhang #define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x15cb 2761f33ac92fSHawking Zhang #define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 2762f33ac92fSHawking Zhang #define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x15cc 2763f33ac92fSHawking Zhang #define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 2764f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x15ce 2765f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 2766f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x15cf 2767f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 2768f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x15d0 2769f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 2770f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x15d1 2771f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 2772f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x15d2 2773f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 2774f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x15d3 2775f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 2776f33ac92fSHawking Zhang #define regGCVM_L2_CNTL4 0x15d4 2777f33ac92fSHawking Zhang #define regGCVM_L2_CNTL4_BASE_IDX 0 2778f33ac92fSHawking Zhang #define regGCVM_L2_MM_GROUP_RT_CLASSES 0x15d5 2779f33ac92fSHawking Zhang #define regGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 2780f33ac92fSHawking Zhang #define regGCVM_L2_BANK_SELECT_RESERVED_CID 0x15d6 2781f33ac92fSHawking Zhang #define regGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 2782f33ac92fSHawking Zhang #define regGCVM_L2_BANK_SELECT_RESERVED_CID2 0x15d7 2783f33ac92fSHawking Zhang #define regGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 2784f33ac92fSHawking Zhang #define regGCVM_L2_CACHE_PARITY_CNTL 0x15d8 2785f33ac92fSHawking Zhang #define regGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 2786f33ac92fSHawking Zhang #define regGCVM_L2_ICG_CTRL 0x15d9 2787f33ac92fSHawking Zhang #define regGCVM_L2_ICG_CTRL_BASE_IDX 0 2788f33ac92fSHawking Zhang #define regGCVM_L2_CNTL5 0x15da 2789f33ac92fSHawking Zhang #define regGCVM_L2_CNTL5_BASE_IDX 0 2790f33ac92fSHawking Zhang #define regGCVM_L2_GCR_CNTL 0x15db 2791f33ac92fSHawking Zhang #define regGCVM_L2_GCR_CNTL_BASE_IDX 0 2792f33ac92fSHawking Zhang #define regGCVML2_WALKER_MACRO_THROTTLE_TIME 0x15dc 2793f33ac92fSHawking Zhang #define regGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX 0 2794f33ac92fSHawking Zhang #define regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT 0x15dd 2795f33ac92fSHawking Zhang #define regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX 0 2796f33ac92fSHawking Zhang #define regGCVML2_WALKER_MICRO_THROTTLE_TIME 0x15de 2797f33ac92fSHawking Zhang #define regGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX 0 2798f33ac92fSHawking Zhang #define regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT 0x15df 2799f33ac92fSHawking Zhang #define regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX 0 2800f33ac92fSHawking Zhang #define regGCVM_L2_CGTT_BUSY_CTRL 0x15e0 2801f33ac92fSHawking Zhang #define regGCVM_L2_CGTT_BUSY_CTRL_BASE_IDX 0 2802f33ac92fSHawking Zhang #define regGCVM_L2_PTE_CACHE_DUMP_CNTL 0x15e1 2803f33ac92fSHawking Zhang #define regGCVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX 0 2804f33ac92fSHawking Zhang #define regGCVM_L2_PTE_CACHE_DUMP_READ 0x15e2 2805f33ac92fSHawking Zhang #define regGCVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX 0 2806f33ac92fSHawking Zhang #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 0x15e5 2807f33ac92fSHawking Zhang #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX 0 2808f33ac92fSHawking Zhang #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 0x15e6 2809f33ac92fSHawking Zhang #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX 0 2810f33ac92fSHawking Zhang #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 0x15e7 2811f33ac92fSHawking Zhang #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX 0 2812f33ac92fSHawking Zhang #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 0x15e8 2813f33ac92fSHawking Zhang #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX 0 2814f33ac92fSHawking Zhang #define regGCVM_L2_BANK_SELECT_MASKS 0x15e9 2815f33ac92fSHawking Zhang #define regGCVM_L2_BANK_SELECT_MASKS_BASE_IDX 0 2816f33ac92fSHawking Zhang #define regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC 0x15ea 2817f33ac92fSHawking Zhang #define regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX 0 2818f33ac92fSHawking Zhang #define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC 0x15eb 2819f33ac92fSHawking Zhang #define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX 0 2820f33ac92fSHawking Zhang #define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC 0x15ec 2821f33ac92fSHawking Zhang #define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX 0 2822f33ac92fSHawking Zhang #define regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT 0x15ed 2823f33ac92fSHawking Zhang #define regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX 0 2824f33ac92fSHawking Zhang #define regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ 0x15ee 2825f33ac92fSHawking Zhang #define regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX 0 2826f33ac92fSHawking Zhang 2827f33ac92fSHawking Zhang 2828f33ac92fSHawking Zhang // addressBlock: gc_gcvmsharedvcdec 2829f33ac92fSHawking Zhang // base address: 0xa360 2830f33ac92fSHawking Zhang #define regGCMC_VM_FB_LOCATION_BASE 0x1678 2831f33ac92fSHawking Zhang #define regGCMC_VM_FB_LOCATION_BASE_BASE_IDX 0 2832f33ac92fSHawking Zhang #define regGCMC_VM_FB_LOCATION_TOP 0x1679 2833f33ac92fSHawking Zhang #define regGCMC_VM_FB_LOCATION_TOP_BASE_IDX 0 2834f33ac92fSHawking Zhang #define regGCMC_VM_AGP_TOP 0x167a 2835f33ac92fSHawking Zhang #define regGCMC_VM_AGP_TOP_BASE_IDX 0 2836f33ac92fSHawking Zhang #define regGCMC_VM_AGP_BOT 0x167b 2837f33ac92fSHawking Zhang #define regGCMC_VM_AGP_BOT_BASE_IDX 0 2838f33ac92fSHawking Zhang #define regGCMC_VM_AGP_BASE 0x167c 2839f33ac92fSHawking Zhang #define regGCMC_VM_AGP_BASE_BASE_IDX 0 2840f33ac92fSHawking Zhang #define regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x167d 2841f33ac92fSHawking Zhang #define regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0 2842f33ac92fSHawking Zhang #define regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x167e 2843f33ac92fSHawking Zhang #define regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0 2844f33ac92fSHawking Zhang #define regGCMC_VM_MX_L1_TLB_CNTL 0x167f 2845f33ac92fSHawking Zhang #define regGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 2846f33ac92fSHawking Zhang 2847f33ac92fSHawking Zhang 2848f33ac92fSHawking Zhang // addressBlock: gc_gcvml2vcdec 2849f33ac92fSHawking Zhang // base address: 0xa3a0 2850f33ac92fSHawking Zhang #define regGCVM_CONTEXT0_CNTL 0x1688 2851f33ac92fSHawking Zhang #define regGCVM_CONTEXT0_CNTL_BASE_IDX 0 2852f33ac92fSHawking Zhang #define regGCVM_CONTEXT1_CNTL 0x1689 2853f33ac92fSHawking Zhang #define regGCVM_CONTEXT1_CNTL_BASE_IDX 0 2854f33ac92fSHawking Zhang #define regGCVM_CONTEXT2_CNTL 0x168a 2855f33ac92fSHawking Zhang #define regGCVM_CONTEXT2_CNTL_BASE_IDX 0 2856f33ac92fSHawking Zhang #define regGCVM_CONTEXT3_CNTL 0x168b 2857f33ac92fSHawking Zhang #define regGCVM_CONTEXT3_CNTL_BASE_IDX 0 2858f33ac92fSHawking Zhang #define regGCVM_CONTEXT4_CNTL 0x168c 2859f33ac92fSHawking Zhang #define regGCVM_CONTEXT4_CNTL_BASE_IDX 0 2860f33ac92fSHawking Zhang #define regGCVM_CONTEXT5_CNTL 0x168d 2861f33ac92fSHawking Zhang #define regGCVM_CONTEXT5_CNTL_BASE_IDX 0 2862f33ac92fSHawking Zhang #define regGCVM_CONTEXT6_CNTL 0x168e 2863f33ac92fSHawking Zhang #define regGCVM_CONTEXT6_CNTL_BASE_IDX 0 2864f33ac92fSHawking Zhang #define regGCVM_CONTEXT7_CNTL 0x168f 2865f33ac92fSHawking Zhang #define regGCVM_CONTEXT7_CNTL_BASE_IDX 0 2866f33ac92fSHawking Zhang #define regGCVM_CONTEXT8_CNTL 0x1690 2867f33ac92fSHawking Zhang #define regGCVM_CONTEXT8_CNTL_BASE_IDX 0 2868f33ac92fSHawking Zhang #define regGCVM_CONTEXT9_CNTL 0x1691 2869f33ac92fSHawking Zhang #define regGCVM_CONTEXT9_CNTL_BASE_IDX 0 2870f33ac92fSHawking Zhang #define regGCVM_CONTEXT10_CNTL 0x1692 2871f33ac92fSHawking Zhang #define regGCVM_CONTEXT10_CNTL_BASE_IDX 0 2872f33ac92fSHawking Zhang #define regGCVM_CONTEXT11_CNTL 0x1693 2873f33ac92fSHawking Zhang #define regGCVM_CONTEXT11_CNTL_BASE_IDX 0 2874f33ac92fSHawking Zhang #define regGCVM_CONTEXT12_CNTL 0x1694 2875f33ac92fSHawking Zhang #define regGCVM_CONTEXT12_CNTL_BASE_IDX 0 2876f33ac92fSHawking Zhang #define regGCVM_CONTEXT13_CNTL 0x1695 2877f33ac92fSHawking Zhang #define regGCVM_CONTEXT13_CNTL_BASE_IDX 0 2878f33ac92fSHawking Zhang #define regGCVM_CONTEXT14_CNTL 0x1696 2879f33ac92fSHawking Zhang #define regGCVM_CONTEXT14_CNTL_BASE_IDX 0 2880f33ac92fSHawking Zhang #define regGCVM_CONTEXT15_CNTL 0x1697 2881f33ac92fSHawking Zhang #define regGCVM_CONTEXT15_CNTL_BASE_IDX 0 2882f33ac92fSHawking Zhang #define regGCVM_CONTEXTS_DISABLE 0x1698 2883f33ac92fSHawking Zhang #define regGCVM_CONTEXTS_DISABLE_BASE_IDX 0 2884f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG0_SEM 0x1699 2885f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 2886f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG1_SEM 0x169a 2887f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 2888f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG2_SEM 0x169b 2889f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 2890f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG3_SEM 0x169c 2891f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 2892f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG4_SEM 0x169d 2893f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 2894f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG5_SEM 0x169e 2895f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 2896f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG6_SEM 0x169f 2897f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 2898f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG7_SEM 0x16a0 2899f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 2900f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG8_SEM 0x16a1 2901f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 2902f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG9_SEM 0x16a2 2903f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 2904f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG10_SEM 0x16a3 2905f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 2906f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG11_SEM 0x16a4 2907f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 2908f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG12_SEM 0x16a5 2909f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 2910f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG13_SEM 0x16a6 2911f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 2912f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG14_SEM 0x16a7 2913f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 2914f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG15_SEM 0x16a8 2915f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 2916f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG16_SEM 0x16a9 2917f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 2918f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG17_SEM 0x16aa 2919f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 2920f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG0_REQ 0x16ab 2921f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 2922f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG1_REQ 0x16ac 2923f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 2924f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG2_REQ 0x16ad 2925f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 2926f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG3_REQ 0x16ae 2927f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 2928f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG4_REQ 0x16af 2929f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 2930f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG5_REQ 0x16b0 2931f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 2932f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG6_REQ 0x16b1 2933f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 2934f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG7_REQ 0x16b2 2935f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 2936f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG8_REQ 0x16b3 2937f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 2938f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG9_REQ 0x16b4 2939f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 2940f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG10_REQ 0x16b5 2941f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 2942f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG11_REQ 0x16b6 2943f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 2944f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG12_REQ 0x16b7 2945f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 2946f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG13_REQ 0x16b8 2947f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 2948f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG14_REQ 0x16b9 2949f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 2950f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG15_REQ 0x16ba 2951f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 2952f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG16_REQ 0x16bb 2953f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 2954f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG17_REQ 0x16bc 2955f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 2956f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG0_ACK 0x16bd 2957f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 2958f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG1_ACK 0x16be 2959f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 2960f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG2_ACK 0x16bf 2961f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 2962f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG3_ACK 0x16c0 2963f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 2964f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG4_ACK 0x16c1 2965f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 2966f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG5_ACK 0x16c2 2967f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 2968f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG6_ACK 0x16c3 2969f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 2970f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG7_ACK 0x16c4 2971f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 2972f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG8_ACK 0x16c5 2973f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 2974f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG9_ACK 0x16c6 2975f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 2976f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG10_ACK 0x16c7 2977f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 2978f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG11_ACK 0x16c8 2979f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 2980f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG12_ACK 0x16c9 2981f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 2982f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG13_ACK 0x16ca 2983f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 2984f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG14_ACK 0x16cb 2985f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 2986f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG15_ACK 0x16cc 2987f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 2988f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG16_ACK 0x16cd 2989f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 2990f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG17_ACK 0x16ce 2991f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 2992f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x16cf 2993f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 2994f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x16d0 2995f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 2996f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x16d1 2997f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 2998f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x16d2 2999f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 3000f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x16d3 3001f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 3002f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x16d4 3003f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 3004f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x16d5 3005f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 3006f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x16d6 3007f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 3008f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x16d7 3009f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 3010f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x16d8 3011f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 3012f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x16d9 3013f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 3014f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x16da 3015f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 3016f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x16db 3017f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 3018f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x16dc 3019f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 3020f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x16dd 3021f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 3022f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x16de 3023f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 3024f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x16df 3025f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 3026f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x16e0 3027f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 3028f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x16e1 3029f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 3030f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x16e2 3031f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 3032f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x16e3 3033f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 3034f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x16e4 3035f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 3036f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x16e5 3037f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 3038f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x16e6 3039f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 3040f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x16e7 3041f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 3042f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x16e8 3043f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 3044f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x16e9 3045f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 3046f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x16ea 3047f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 3048f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x16eb 3049f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 3050f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x16ec 3051f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 3052f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x16ed 3053f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 3054f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x16ee 3055f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 3056f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x16ef 3057f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 3058f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x16f0 3059f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 3060f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x16f1 3061f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 3062f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x16f2 3063f33ac92fSHawking Zhang #define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 3064f33ac92fSHawking Zhang #define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x16f3 3065f33ac92fSHawking Zhang #define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 3066f33ac92fSHawking Zhang #define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x16f4 3067f33ac92fSHawking Zhang #define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 3068f33ac92fSHawking Zhang #define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x16f5 3069f33ac92fSHawking Zhang #define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 3070f33ac92fSHawking Zhang #define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x16f6 3071f33ac92fSHawking Zhang #define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 3072f33ac92fSHawking Zhang #define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x16f7 3073f33ac92fSHawking Zhang #define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 3074f33ac92fSHawking Zhang #define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x16f8 3075f33ac92fSHawking Zhang #define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 3076f33ac92fSHawking Zhang #define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x16f9 3077f33ac92fSHawking Zhang #define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 3078f33ac92fSHawking Zhang #define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x16fa 3079f33ac92fSHawking Zhang #define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 3080f33ac92fSHawking Zhang #define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x16fb 3081f33ac92fSHawking Zhang #define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 3082f33ac92fSHawking Zhang #define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x16fc 3083f33ac92fSHawking Zhang #define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 3084f33ac92fSHawking Zhang #define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x16fd 3085f33ac92fSHawking Zhang #define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 3086f33ac92fSHawking Zhang #define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x16fe 3087f33ac92fSHawking Zhang #define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 3088f33ac92fSHawking Zhang #define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x16ff 3089f33ac92fSHawking Zhang #define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 3090f33ac92fSHawking Zhang #define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x1700 3091f33ac92fSHawking Zhang #define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 3092f33ac92fSHawking Zhang #define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x1701 3093f33ac92fSHawking Zhang #define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 3094f33ac92fSHawking Zhang #define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x1702 3095f33ac92fSHawking Zhang #define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 3096f33ac92fSHawking Zhang #define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x1703 3097f33ac92fSHawking Zhang #define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 3098f33ac92fSHawking Zhang #define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x1704 3099f33ac92fSHawking Zhang #define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 3100f33ac92fSHawking Zhang #define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x1705 3101f33ac92fSHawking Zhang #define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 3102f33ac92fSHawking Zhang #define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x1706 3103f33ac92fSHawking Zhang #define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 3104f33ac92fSHawking Zhang #define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x1707 3105f33ac92fSHawking Zhang #define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 3106f33ac92fSHawking Zhang #define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x1708 3107f33ac92fSHawking Zhang #define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 3108f33ac92fSHawking Zhang #define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x1709 3109f33ac92fSHawking Zhang #define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 3110f33ac92fSHawking Zhang #define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x170a 3111f33ac92fSHawking Zhang #define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 3112f33ac92fSHawking Zhang #define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x170b 3113f33ac92fSHawking Zhang #define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 3114f33ac92fSHawking Zhang #define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x170c 3115f33ac92fSHawking Zhang #define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 3116f33ac92fSHawking Zhang #define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x170d 3117f33ac92fSHawking Zhang #define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 3118f33ac92fSHawking Zhang #define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x170e 3119f33ac92fSHawking Zhang #define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 3120f33ac92fSHawking Zhang #define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x170f 3121f33ac92fSHawking Zhang #define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 3122f33ac92fSHawking Zhang #define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x1710 3123f33ac92fSHawking Zhang #define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 3124f33ac92fSHawking Zhang #define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x1711 3125f33ac92fSHawking Zhang #define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 3126f33ac92fSHawking Zhang #define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x1712 3127f33ac92fSHawking Zhang #define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 3128f33ac92fSHawking Zhang #define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x1713 3129f33ac92fSHawking Zhang #define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 3130f33ac92fSHawking Zhang #define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x1714 3131f33ac92fSHawking Zhang #define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 3132f33ac92fSHawking Zhang #define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x1715 3133f33ac92fSHawking Zhang #define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 3134f33ac92fSHawking Zhang #define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x1716 3135f33ac92fSHawking Zhang #define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 3136f33ac92fSHawking Zhang #define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x1717 3137f33ac92fSHawking Zhang #define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 3138f33ac92fSHawking Zhang #define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x1718 3139f33ac92fSHawking Zhang #define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 3140f33ac92fSHawking Zhang #define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x1719 3141f33ac92fSHawking Zhang #define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 3142f33ac92fSHawking Zhang #define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x171a 3143f33ac92fSHawking Zhang #define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 3144f33ac92fSHawking Zhang #define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x171b 3145f33ac92fSHawking Zhang #define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 3146f33ac92fSHawking Zhang #define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x171c 3147f33ac92fSHawking Zhang #define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 3148f33ac92fSHawking Zhang #define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x171d 3149f33ac92fSHawking Zhang #define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 3150f33ac92fSHawking Zhang #define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x171e 3151f33ac92fSHawking Zhang #define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 3152f33ac92fSHawking Zhang #define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x171f 3153f33ac92fSHawking Zhang #define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 3154f33ac92fSHawking Zhang #define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x1720 3155f33ac92fSHawking Zhang #define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 3156f33ac92fSHawking Zhang #define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x1721 3157f33ac92fSHawking Zhang #define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 3158f33ac92fSHawking Zhang #define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x1722 3159f33ac92fSHawking Zhang #define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 3160f33ac92fSHawking Zhang #define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x1723 3161f33ac92fSHawking Zhang #define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 3162f33ac92fSHawking Zhang #define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x1724 3163f33ac92fSHawking Zhang #define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 3164f33ac92fSHawking Zhang #define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x1725 3165f33ac92fSHawking Zhang #define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 3166f33ac92fSHawking Zhang #define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x1726 3167f33ac92fSHawking Zhang #define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 3168f33ac92fSHawking Zhang #define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x1727 3169f33ac92fSHawking Zhang #define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 3170f33ac92fSHawking Zhang #define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x1728 3171f33ac92fSHawking Zhang #define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 3172f33ac92fSHawking Zhang #define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x1729 3173f33ac92fSHawking Zhang #define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 3174f33ac92fSHawking Zhang #define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x172a 3175f33ac92fSHawking Zhang #define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 3176f33ac92fSHawking Zhang #define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x172b 3177f33ac92fSHawking Zhang #define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 3178f33ac92fSHawking Zhang #define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x172c 3179f33ac92fSHawking Zhang #define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 3180f33ac92fSHawking Zhang #define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x172d 3181f33ac92fSHawking Zhang #define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 3182f33ac92fSHawking Zhang #define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x172e 3183f33ac92fSHawking Zhang #define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 3184f33ac92fSHawking Zhang #define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x172f 3185f33ac92fSHawking Zhang #define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 3186f33ac92fSHawking Zhang #define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x1730 3187f33ac92fSHawking Zhang #define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 3188f33ac92fSHawking Zhang #define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x1731 3189f33ac92fSHawking Zhang #define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 3190f33ac92fSHawking Zhang #define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x1732 3191f33ac92fSHawking Zhang #define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 3192f33ac92fSHawking Zhang #define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x1733 3193f33ac92fSHawking Zhang #define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3194f33ac92fSHawking Zhang #define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x1734 3195f33ac92fSHawking Zhang #define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3196f33ac92fSHawking Zhang #define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x1735 3197f33ac92fSHawking Zhang #define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3198f33ac92fSHawking Zhang #define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x1736 3199f33ac92fSHawking Zhang #define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3200f33ac92fSHawking Zhang #define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x1737 3201f33ac92fSHawking Zhang #define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3202f33ac92fSHawking Zhang #define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x1738 3203f33ac92fSHawking Zhang #define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3204f33ac92fSHawking Zhang #define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x1739 3205f33ac92fSHawking Zhang #define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3206f33ac92fSHawking Zhang #define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x173a 3207f33ac92fSHawking Zhang #define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3208f33ac92fSHawking Zhang #define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x173b 3209f33ac92fSHawking Zhang #define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3210f33ac92fSHawking Zhang #define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x173c 3211f33ac92fSHawking Zhang #define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3212f33ac92fSHawking Zhang #define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x173d 3213f33ac92fSHawking Zhang #define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3214f33ac92fSHawking Zhang #define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x173e 3215f33ac92fSHawking Zhang #define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3216f33ac92fSHawking Zhang #define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x173f 3217f33ac92fSHawking Zhang #define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3218f33ac92fSHawking Zhang #define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x1740 3219f33ac92fSHawking Zhang #define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3220f33ac92fSHawking Zhang #define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x1741 3221f33ac92fSHawking Zhang #define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3222f33ac92fSHawking Zhang #define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x1742 3223f33ac92fSHawking Zhang #define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3224f33ac92fSHawking Zhang #define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x1743 3225f33ac92fSHawking Zhang #define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3226f33ac92fSHawking Zhang #define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x1744 3227f33ac92fSHawking Zhang #define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3228f33ac92fSHawking Zhang #define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x1745 3229f33ac92fSHawking Zhang #define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3230f33ac92fSHawking Zhang #define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x1746 3231f33ac92fSHawking Zhang #define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3232f33ac92fSHawking Zhang #define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x1747 3233f33ac92fSHawking Zhang #define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3234f33ac92fSHawking Zhang #define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x1748 3235f33ac92fSHawking Zhang #define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3236f33ac92fSHawking Zhang #define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x1749 3237f33ac92fSHawking Zhang #define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3238f33ac92fSHawking Zhang #define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x174a 3239f33ac92fSHawking Zhang #define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3240f33ac92fSHawking Zhang #define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x174b 3241f33ac92fSHawking Zhang #define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3242f33ac92fSHawking Zhang #define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x174c 3243f33ac92fSHawking Zhang #define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3244f33ac92fSHawking Zhang #define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x174d 3245f33ac92fSHawking Zhang #define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3246f33ac92fSHawking Zhang #define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x174e 3247f33ac92fSHawking Zhang #define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3248f33ac92fSHawking Zhang #define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x174f 3249f33ac92fSHawking Zhang #define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3250f33ac92fSHawking Zhang #define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x1750 3251f33ac92fSHawking Zhang #define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3252f33ac92fSHawking Zhang #define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x1751 3253f33ac92fSHawking Zhang #define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 3254f33ac92fSHawking Zhang #define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x1752 3255f33ac92fSHawking Zhang #define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 3256f33ac92fSHawking Zhang #define regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1753 3257f33ac92fSHawking Zhang #define regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 3258f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1754 3259f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 3260f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1755 3261f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 3262f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1756 3263f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 3264f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1757 3265f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 3266f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1758 3267f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 3268f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1759 3269f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 3270f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x175a 3271f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 3272f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x175b 3273f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 3274f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x175c 3275f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 3276f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x175d 3277f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 3278f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x175e 3279f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 3280f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x175f 3281f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 3282f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1760 3283f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 3284f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1761 3285f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 3286f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1762 3287f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 3288f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1763 3289f33ac92fSHawking Zhang #define regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 3290f33ac92fSHawking Zhang 3291f33ac92fSHawking Zhang 3292f33ac92fSHawking Zhang // addressBlock: gc_gcvml2perfddec 3293f33ac92fSHawking Zhang // base address: 0x35380 3294f33ac92fSHawking Zhang #define regGCVML2_PERFCOUNTER2_0_LO 0x34e0 3295f33ac92fSHawking Zhang #define regGCVML2_PERFCOUNTER2_0_LO_BASE_IDX 1 3296f33ac92fSHawking Zhang #define regGCVML2_PERFCOUNTER2_1_LO 0x34e1 3297f33ac92fSHawking Zhang #define regGCVML2_PERFCOUNTER2_1_LO_BASE_IDX 1 3298f33ac92fSHawking Zhang #define regGCVML2_PERFCOUNTER2_0_HI 0x34e2 3299f33ac92fSHawking Zhang #define regGCVML2_PERFCOUNTER2_0_HI_BASE_IDX 1 3300f33ac92fSHawking Zhang #define regGCVML2_PERFCOUNTER2_1_HI 0x34e3 3301f33ac92fSHawking Zhang #define regGCVML2_PERFCOUNTER2_1_HI_BASE_IDX 1 3302f33ac92fSHawking Zhang 3303f33ac92fSHawking Zhang 3304f33ac92fSHawking Zhang // addressBlock: gc_gcvml2prdec 3305f33ac92fSHawking Zhang // base address: 0x35390 3306f33ac92fSHawking Zhang #define regGCMC_VM_L2_PERFCOUNTER_LO 0x34e4 3307f33ac92fSHawking Zhang #define regGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1 3308f33ac92fSHawking Zhang #define regGCMC_VM_L2_PERFCOUNTER_HI 0x34e5 3309f33ac92fSHawking Zhang #define regGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1 3310f33ac92fSHawking Zhang #define regGCUTCL2_PERFCOUNTER_LO 0x34e6 3311f33ac92fSHawking Zhang #define regGCUTCL2_PERFCOUNTER_LO_BASE_IDX 1 3312f33ac92fSHawking Zhang #define regGCUTCL2_PERFCOUNTER_HI 0x34e7 3313f33ac92fSHawking Zhang #define regGCUTCL2_PERFCOUNTER_HI_BASE_IDX 1 3314f33ac92fSHawking Zhang 3315f33ac92fSHawking Zhang 3316f33ac92fSHawking Zhang // addressBlock: gc_gcvml2perfsdec 3317f33ac92fSHawking Zhang // base address: 0x37480 3318f33ac92fSHawking Zhang #define regGCVML2_PERFCOUNTER2_0_SELECT 0x3d20 3319f33ac92fSHawking Zhang #define regGCVML2_PERFCOUNTER2_0_SELECT_BASE_IDX 1 3320f33ac92fSHawking Zhang #define regGCVML2_PERFCOUNTER2_1_SELECT 0x3d21 3321f33ac92fSHawking Zhang #define regGCVML2_PERFCOUNTER2_1_SELECT_BASE_IDX 1 3322f33ac92fSHawking Zhang #define regGCVML2_PERFCOUNTER2_0_SELECT1 0x3d22 3323f33ac92fSHawking Zhang #define regGCVML2_PERFCOUNTER2_0_SELECT1_BASE_IDX 1 3324f33ac92fSHawking Zhang #define regGCVML2_PERFCOUNTER2_1_SELECT1 0x3d23 3325f33ac92fSHawking Zhang #define regGCVML2_PERFCOUNTER2_1_SELECT1_BASE_IDX 1 3326f33ac92fSHawking Zhang #define regGCVML2_PERFCOUNTER2_0_MODE 0x3d24 3327f33ac92fSHawking Zhang #define regGCVML2_PERFCOUNTER2_0_MODE_BASE_IDX 1 3328f33ac92fSHawking Zhang #define regGCVML2_PERFCOUNTER2_1_MODE 0x3d25 3329f33ac92fSHawking Zhang #define regGCVML2_PERFCOUNTER2_1_MODE_BASE_IDX 1 3330f33ac92fSHawking Zhang 3331f33ac92fSHawking Zhang 3332f33ac92fSHawking Zhang // addressBlock: gc_gcvml2pldec 3333f33ac92fSHawking Zhang // base address: 0x374c0 3334f33ac92fSHawking Zhang #define regGCMC_VM_L2_PERFCOUNTER0_CFG 0x3d30 3335f33ac92fSHawking Zhang #define regGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1 3336f33ac92fSHawking Zhang #define regGCMC_VM_L2_PERFCOUNTER1_CFG 0x3d31 3337f33ac92fSHawking Zhang #define regGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1 3338f33ac92fSHawking Zhang #define regGCMC_VM_L2_PERFCOUNTER2_CFG 0x3d32 3339f33ac92fSHawking Zhang #define regGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1 3340f33ac92fSHawking Zhang #define regGCMC_VM_L2_PERFCOUNTER3_CFG 0x3d33 3341f33ac92fSHawking Zhang #define regGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1 3342f33ac92fSHawking Zhang #define regGCMC_VM_L2_PERFCOUNTER4_CFG 0x3d34 3343f33ac92fSHawking Zhang #define regGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1 3344f33ac92fSHawking Zhang #define regGCMC_VM_L2_PERFCOUNTER5_CFG 0x3d35 3345f33ac92fSHawking Zhang #define regGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1 3346f33ac92fSHawking Zhang #define regGCMC_VM_L2_PERFCOUNTER6_CFG 0x3d36 3347f33ac92fSHawking Zhang #define regGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1 3348f33ac92fSHawking Zhang #define regGCMC_VM_L2_PERFCOUNTER7_CFG 0x3d37 3349f33ac92fSHawking Zhang #define regGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1 3350f33ac92fSHawking Zhang #define regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x3d38 3351f33ac92fSHawking Zhang #define regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 3352f33ac92fSHawking Zhang #define regGCUTCL2_PERFCOUNTER0_CFG 0x3d39 3353f33ac92fSHawking Zhang #define regGCUTCL2_PERFCOUNTER0_CFG_BASE_IDX 1 3354f33ac92fSHawking Zhang #define regGCUTCL2_PERFCOUNTER1_CFG 0x3d3a 3355f33ac92fSHawking Zhang #define regGCUTCL2_PERFCOUNTER1_CFG_BASE_IDX 1 3356f33ac92fSHawking Zhang #define regGCUTCL2_PERFCOUNTER2_CFG 0x3d3b 3357f33ac92fSHawking Zhang #define regGCUTCL2_PERFCOUNTER2_CFG_BASE_IDX 1 3358f33ac92fSHawking Zhang #define regGCUTCL2_PERFCOUNTER3_CFG 0x3d3c 3359f33ac92fSHawking Zhang #define regGCUTCL2_PERFCOUNTER3_CFG_BASE_IDX 1 3360f33ac92fSHawking Zhang #define regGCUTCL2_PERFCOUNTER_RSLT_CNTL 0x3d3d 3361f33ac92fSHawking Zhang #define regGCUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 3362f33ac92fSHawking Zhang 3363f33ac92fSHawking Zhang 3364f33ac92fSHawking Zhang // addressBlock: gc_gcvmsharedhvdec 3365f33ac92fSHawking Zhang // base address: 0x3ea00 3366f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF0 0x5a80 3367f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1 3368f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF1 0x5a81 3369f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1 3370f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF2 0x5a82 3371f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1 3372f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF3 0x5a83 3373f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1 3374f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF4 0x5a84 3375f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1 3376f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF5 0x5a85 3377f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1 3378f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF6 0x5a86 3379f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1 3380f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF7 0x5a87 3381f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1 3382f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF8 0x5a88 3383f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 1 3384f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF9 0x5a89 3385f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 1 3386f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF10 0x5a8a 3387f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 1 3388f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF11 0x5a8b 3389f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 1 3390f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF12 0x5a8c 3391f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 1 3392f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF13 0x5a8d 3393f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 1 3394f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF14 0x5a8e 3395f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 1 3396f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF15 0x5a8f 3397f33ac92fSHawking Zhang #define regGCMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 1 3398f33ac92fSHawking Zhang 3399f33ac92fSHawking Zhang 3400f33ac92fSHawking Zhang // addressBlock: gc_gcvml2pspdec 3401f33ac92fSHawking Zhang // base address: 0x3f900 3402f33ac92fSHawking Zhang #define regGCUTCL2_TRANSLATION_BYPASS_BY_VMID 0x5e41 3403f33ac92fSHawking Zhang #define regGCUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX 1 3404f33ac92fSHawking Zhang #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL 0x5e44 3405f33ac92fSHawking Zhang #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX 1 3406f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_0 0x5e48 3407f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_0_BASE_IDX 1 3408f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_1 0x5e49 3409f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_1_BASE_IDX 1 3410f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_2 0x5e4a 3411f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_2_BASE_IDX 1 3412f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_3 0x5e4b 3413f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_3_BASE_IDX 1 3414f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_4 0x5e4c 3415f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_4_BASE_IDX 1 3416f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_5 0x5e4d 3417f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_5_BASE_IDX 1 3418f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_6 0x5e4e 3419f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_6_BASE_IDX 1 3420f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_7 0x5e4f 3421f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_7_BASE_IDX 1 3422f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_8 0x5e50 3423f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_8_BASE_IDX 1 3424f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_9 0x5e51 3425f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_9_BASE_IDX 1 3426f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_10 0x5e52 3427f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_10_BASE_IDX 1 3428f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_11 0x5e53 3429f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_11_BASE_IDX 1 3430f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_12 0x5e54 3431f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_12_BASE_IDX 1 3432f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_13 0x5e55 3433f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_13_BASE_IDX 1 3434f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_14 0x5e56 3435f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_14_BASE_IDX 1 3436f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_15 0x5e57 3437f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_LO_15_BASE_IDX 1 3438f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_0 0x5e58 3439f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_0_BASE_IDX 1 3440f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_1 0x5e59 3441f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_1_BASE_IDX 1 3442f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_2 0x5e5a 3443f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_2_BASE_IDX 1 3444f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_3 0x5e5b 3445f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_3_BASE_IDX 1 3446f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_4 0x5e5c 3447f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_4_BASE_IDX 1 3448f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_5 0x5e5d 3449f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_5_BASE_IDX 1 3450f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_6 0x5e5e 3451f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_6_BASE_IDX 1 3452f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_7 0x5e5f 3453f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_7_BASE_IDX 1 3454f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_8 0x5e60 3455f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_8_BASE_IDX 1 3456f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_9 0x5e61 3457f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_9_BASE_IDX 1 3458f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_10 0x5e62 3459f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_10_BASE_IDX 1 3460f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_11 0x5e63 3461f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_11_BASE_IDX 1 3462f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_12 0x5e64 3463f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_12_BASE_IDX 1 3464f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_13 0x5e65 3465f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_13_BASE_IDX 1 3466f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_14 0x5e66 3467f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_14_BASE_IDX 1 3468f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_15 0x5e67 3469f33ac92fSHawking Zhang #define regGCMC_VM_MARC_BASE_HI_15_BASE_IDX 1 3470f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_0 0x5e68 3471f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_0_BASE_IDX 1 3472f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_1 0x5e69 3473f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_1_BASE_IDX 1 3474f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_2 0x5e6a 3475f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_2_BASE_IDX 1 3476f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_3 0x5e6b 3477f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_3_BASE_IDX 1 3478f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_4 0x5e6c 3479f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_4_BASE_IDX 1 3480f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_5 0x5e6d 3481f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_5_BASE_IDX 1 3482f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_6 0x5e6e 3483f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_6_BASE_IDX 1 3484f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_7 0x5e6f 3485f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_7_BASE_IDX 1 3486f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_8 0x5e70 3487f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_8_BASE_IDX 1 3488f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_9 0x5e71 3489f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_9_BASE_IDX 1 3490f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_10 0x5e72 3491f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_10_BASE_IDX 1 3492f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_11 0x5e73 3493f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_11_BASE_IDX 1 3494f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_12 0x5e74 3495f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_12_BASE_IDX 1 3496f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_13 0x5e75 3497f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_13_BASE_IDX 1 3498f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_14 0x5e76 3499f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_14_BASE_IDX 1 3500f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_15 0x5e77 3501f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_LO_15_BASE_IDX 1 3502f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_0 0x5e78 3503f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_0_BASE_IDX 1 3504f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_1 0x5e79 3505f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_1_BASE_IDX 1 3506f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_2 0x5e7a 3507f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_2_BASE_IDX 1 3508f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_3 0x5e7b 3509f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_3_BASE_IDX 1 3510f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_4 0x5e7c 3511f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_4_BASE_IDX 1 3512f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_5 0x5e7d 3513f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_5_BASE_IDX 1 3514f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_6 0x5e7e 3515f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_6_BASE_IDX 1 3516f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_7 0x5e7f 3517f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_7_BASE_IDX 1 3518f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_8 0x5e80 3519f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_8_BASE_IDX 1 3520f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_9 0x5e81 3521f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_9_BASE_IDX 1 3522f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_10 0x5e82 3523f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_10_BASE_IDX 1 3524f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_11 0x5e83 3525f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_11_BASE_IDX 1 3526f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_12 0x5e84 3527f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_12_BASE_IDX 1 3528f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_13 0x5e85 3529f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_13_BASE_IDX 1 3530f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_14 0x5e86 3531f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_14_BASE_IDX 1 3532f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_15 0x5e87 3533f33ac92fSHawking Zhang #define regGCMC_VM_MARC_RELOC_HI_15_BASE_IDX 1 3534f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_0 0x5e88 3535f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_0_BASE_IDX 1 3536f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_1 0x5e89 3537f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_1_BASE_IDX 1 3538f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_2 0x5e8a 3539f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_2_BASE_IDX 1 3540f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_3 0x5e8b 3541f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_3_BASE_IDX 1 3542f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_4 0x5e8c 3543f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_4_BASE_IDX 1 3544f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_5 0x5e8d 3545f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_5_BASE_IDX 1 3546f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_6 0x5e8e 3547f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_6_BASE_IDX 1 3548f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_7 0x5e8f 3549f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_7_BASE_IDX 1 3550f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_8 0x5e90 3551f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_8_BASE_IDX 1 3552f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_9 0x5e91 3553f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_9_BASE_IDX 1 3554f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_10 0x5e92 3555f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_10_BASE_IDX 1 3556f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_11 0x5e93 3557f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_11_BASE_IDX 1 3558f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_12 0x5e94 3559f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_12_BASE_IDX 1 3560f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_13 0x5e95 3561f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_13_BASE_IDX 1 3562f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_14 0x5e96 3563f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_14_BASE_IDX 1 3564f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_15 0x5e97 3565f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_LO_15_BASE_IDX 1 3566f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_0 0x5e98 3567f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_0_BASE_IDX 1 3568f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_1 0x5e99 3569f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_1_BASE_IDX 1 3570f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_2 0x5e9a 3571f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_2_BASE_IDX 1 3572f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_3 0x5e9b 3573f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_3_BASE_IDX 1 3574f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_4 0x5e9c 3575f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_4_BASE_IDX 1 3576f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_5 0x5e9d 3577f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_5_BASE_IDX 1 3578f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_6 0x5e9e 3579f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_6_BASE_IDX 1 3580f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_7 0x5e9f 3581f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_7_BASE_IDX 1 3582f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_8 0x5ea0 3583f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_8_BASE_IDX 1 3584f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_9 0x5ea1 3585f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_9_BASE_IDX 1 3586f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_10 0x5ea2 3587f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_10_BASE_IDX 1 3588f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_11 0x5ea3 3589f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_11_BASE_IDX 1 3590f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_12 0x5ea4 3591f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_12_BASE_IDX 1 3592f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_13 0x5ea5 3593f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_13_BASE_IDX 1 3594f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_14 0x5ea6 3595f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_14_BASE_IDX 1 3596f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_15 0x5ea7 3597f33ac92fSHawking Zhang #define regGCMC_VM_MARC_LEN_HI_15_BASE_IDX 1 3598f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_0 0x5ea8 3599f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_0_BASE_IDX 1 3600f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_1 0x5ea9 3601f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_1_BASE_IDX 1 3602f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_2 0x5eaa 3603f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_2_BASE_IDX 1 3604f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_3 0x5eab 3605f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_3_BASE_IDX 1 3606f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_4 0x5eac 3607f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_4_BASE_IDX 1 3608f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_5 0x5ead 3609f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_5_BASE_IDX 1 3610f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_6 0x5eae 3611f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_6_BASE_IDX 1 3612f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_7 0x5eaf 3613f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_7_BASE_IDX 1 3614f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_8 0x5eb0 3615f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_8_BASE_IDX 1 3616f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_9 0x5eb1 3617f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_9_BASE_IDX 1 3618f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_10 0x5eb2 3619f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_10_BASE_IDX 1 3620f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_11 0x5eb3 3621f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_11_BASE_IDX 1 3622f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_12 0x5eb4 3623f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_12_BASE_IDX 1 3624f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_13 0x5eb5 3625f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_13_BASE_IDX 1 3626f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_14 0x5eb6 3627f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_14_BASE_IDX 1 3628f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_15 0x5eb7 3629f33ac92fSHawking Zhang #define regGCMC_VM_MARC_PFVF_MAPPING_15_BASE_IDX 1 3630f33ac92fSHawking Zhang #define regGCUTC_TRANSLATION_FAULT_CNTL0 0x5eb8 3631f33ac92fSHawking Zhang #define regGCUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX 1 3632f33ac92fSHawking Zhang #define regGCUTC_TRANSLATION_FAULT_CNTL1 0x5eb9 3633f33ac92fSHawking Zhang #define regGCUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX 1 3634f33ac92fSHawking Zhang 3635f33ac92fSHawking Zhang 3636f33ac92fSHawking Zhang // addressBlock: gc_shdec 3637f33ac92fSHawking Zhang // base address: 0xb000 3638f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_RSRC4_PS 0x19a1 3639f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_RSRC4_PS_BASE_IDX 0 3640f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_CHKSUM_PS 0x19a6 3641f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX 0 3642f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_RSRC3_PS 0x19a7 3643f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_RSRC3_PS_BASE_IDX 0 3644f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_LO_PS 0x19a8 3645f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_LO_PS_BASE_IDX 0 3646f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_HI_PS 0x19a9 3647f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_HI_PS_BASE_IDX 0 3648f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_RSRC1_PS 0x19aa 3649f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_RSRC1_PS_BASE_IDX 0 3650f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_RSRC2_PS 0x19ab 3651f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_RSRC2_PS_BASE_IDX 0 3652f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_0 0x19ac 3653f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_0_BASE_IDX 0 3654f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_1 0x19ad 3655f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_1_BASE_IDX 0 3656f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_2 0x19ae 3657f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_2_BASE_IDX 0 3658f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_3 0x19af 3659f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_3_BASE_IDX 0 3660f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_4 0x19b0 3661f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_4_BASE_IDX 0 3662f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_5 0x19b1 3663f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_5_BASE_IDX 0 3664f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_6 0x19b2 3665f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_6_BASE_IDX 0 3666f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_7 0x19b3 3667f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_7_BASE_IDX 0 3668f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_8 0x19b4 3669f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_8_BASE_IDX 0 3670f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_9 0x19b5 3671f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_9_BASE_IDX 0 3672f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_10 0x19b6 3673f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_10_BASE_IDX 0 3674f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_11 0x19b7 3675f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_11_BASE_IDX 0 3676f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_12 0x19b8 3677f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_12_BASE_IDX 0 3678f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_13 0x19b9 3679f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_13_BASE_IDX 0 3680f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_14 0x19ba 3681f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_14_BASE_IDX 0 3682f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_15 0x19bb 3683f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_15_BASE_IDX 0 3684f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_16 0x19bc 3685f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_16_BASE_IDX 0 3686f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_17 0x19bd 3687f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_17_BASE_IDX 0 3688f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_18 0x19be 3689f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_18_BASE_IDX 0 3690f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_19 0x19bf 3691f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_19_BASE_IDX 0 3692f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_20 0x19c0 3693f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_20_BASE_IDX 0 3694f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_21 0x19c1 3695f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_21_BASE_IDX 0 3696f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_22 0x19c2 3697f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_22_BASE_IDX 0 3698f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_23 0x19c3 3699f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_23_BASE_IDX 0 3700f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_24 0x19c4 3701f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_24_BASE_IDX 0 3702f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_25 0x19c5 3703f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_25_BASE_IDX 0 3704f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_26 0x19c6 3705f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_26_BASE_IDX 0 3706f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_27 0x19c7 3707f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_27_BASE_IDX 0 3708f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_28 0x19c8 3709f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_28_BASE_IDX 0 3710f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_29 0x19c9 3711f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_29_BASE_IDX 0 3712f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_30 0x19ca 3713f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_30_BASE_IDX 0 3714f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_31 0x19cb 3715f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_PS_31_BASE_IDX 0 3716f33ac92fSHawking Zhang #define regSPI_SHADER_REQ_CTRL_PS 0x19d0 3717f33ac92fSHawking Zhang #define regSPI_SHADER_REQ_CTRL_PS_BASE_IDX 0 3718f33ac92fSHawking Zhang #define regSPI_SHADER_USER_ACCUM_PS_0 0x19d2 3719f33ac92fSHawking Zhang #define regSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX 0 3720f33ac92fSHawking Zhang #define regSPI_SHADER_USER_ACCUM_PS_1 0x19d3 3721f33ac92fSHawking Zhang #define regSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX 0 3722f33ac92fSHawking Zhang #define regSPI_SHADER_USER_ACCUM_PS_2 0x19d4 3723f33ac92fSHawking Zhang #define regSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX 0 3724f33ac92fSHawking Zhang #define regSPI_SHADER_USER_ACCUM_PS_3 0x19d5 3725f33ac92fSHawking Zhang #define regSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX 0 3726f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_CHKSUM_GS 0x1a20 3727f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX 0 3728f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_RSRC4_GS 0x1a21 3729f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_RSRC4_GS_BASE_IDX 0 3730f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_ADDR_LO_GS 0x1a22 3731f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX 0 3732f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_ADDR_HI_GS 0x1a23 3733f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX 0 3734f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_LO_ES_GS 0x1a24 3735f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_LO_ES_GS_BASE_IDX 0 3736f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_HI_ES_GS 0x1a25 3737f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_HI_ES_GS_BASE_IDX 0 3738f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_RSRC3_GS 0x1a27 3739f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_RSRC3_GS_BASE_IDX 0 3740f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_LO_GS 0x1a28 3741f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_LO_GS_BASE_IDX 0 3742f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_HI_GS 0x1a29 3743f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_HI_GS_BASE_IDX 0 3744f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_RSRC1_GS 0x1a2a 3745f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_RSRC1_GS_BASE_IDX 0 3746f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_RSRC2_GS 0x1a2b 3747f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_RSRC2_GS_BASE_IDX 0 3748f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_0 0x1a2c 3749f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_0_BASE_IDX 0 3750f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_1 0x1a2d 3751f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_1_BASE_IDX 0 3752f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_2 0x1a2e 3753f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_2_BASE_IDX 0 3754f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_3 0x1a2f 3755f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_3_BASE_IDX 0 3756f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_4 0x1a30 3757f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_4_BASE_IDX 0 3758f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_5 0x1a31 3759f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_5_BASE_IDX 0 3760f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_6 0x1a32 3761f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_6_BASE_IDX 0 3762f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_7 0x1a33 3763f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_7_BASE_IDX 0 3764f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_8 0x1a34 3765f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_8_BASE_IDX 0 3766f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_9 0x1a35 3767f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_9_BASE_IDX 0 3768f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_10 0x1a36 3769f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_10_BASE_IDX 0 3770f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_11 0x1a37 3771f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_11_BASE_IDX 0 3772f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_12 0x1a38 3773f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_12_BASE_IDX 0 3774f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_13 0x1a39 3775f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_13_BASE_IDX 0 3776f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_14 0x1a3a 3777f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_14_BASE_IDX 0 3778f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_15 0x1a3b 3779f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_15_BASE_IDX 0 3780f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_16 0x1a3c 3781f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_16_BASE_IDX 0 3782f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_17 0x1a3d 3783f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_17_BASE_IDX 0 3784f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_18 0x1a3e 3785f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_18_BASE_IDX 0 3786f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_19 0x1a3f 3787f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_19_BASE_IDX 0 3788f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_20 0x1a40 3789f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_20_BASE_IDX 0 3790f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_21 0x1a41 3791f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_21_BASE_IDX 0 3792f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_22 0x1a42 3793f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_22_BASE_IDX 0 3794f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_23 0x1a43 3795f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_23_BASE_IDX 0 3796f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_24 0x1a44 3797f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_24_BASE_IDX 0 3798f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_25 0x1a45 3799f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_25_BASE_IDX 0 3800f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_26 0x1a46 3801f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_26_BASE_IDX 0 3802f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_27 0x1a47 3803f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_27_BASE_IDX 0 3804f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_28 0x1a48 3805f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_28_BASE_IDX 0 3806f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_29 0x1a49 3807f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_29_BASE_IDX 0 3808f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_30 0x1a4a 3809f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_30_BASE_IDX 0 3810f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_31 0x1a4b 3811f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_GS_31_BASE_IDX 0 3812f33ac92fSHawking Zhang #define regSPI_SHADER_GS_MESHLET_DIM 0x1a4c 3813f33ac92fSHawking Zhang #define regSPI_SHADER_GS_MESHLET_DIM_BASE_IDX 0 3814f33ac92fSHawking Zhang #define regSPI_SHADER_GS_MESHLET_EXP_ALLOC 0x1a4d 3815f33ac92fSHawking Zhang #define regSPI_SHADER_GS_MESHLET_EXP_ALLOC_BASE_IDX 0 3816f33ac92fSHawking Zhang #define regSPI_SHADER_REQ_CTRL_ESGS 0x1a50 3817f33ac92fSHawking Zhang #define regSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX 0 3818f33ac92fSHawking Zhang #define regSPI_SHADER_USER_ACCUM_ESGS_0 0x1a52 3819f33ac92fSHawking Zhang #define regSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX 0 3820f33ac92fSHawking Zhang #define regSPI_SHADER_USER_ACCUM_ESGS_1 0x1a53 3821f33ac92fSHawking Zhang #define regSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX 0 3822f33ac92fSHawking Zhang #define regSPI_SHADER_USER_ACCUM_ESGS_2 0x1a54 3823f33ac92fSHawking Zhang #define regSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX 0 3824f33ac92fSHawking Zhang #define regSPI_SHADER_USER_ACCUM_ESGS_3 0x1a55 3825f33ac92fSHawking Zhang #define regSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX 0 3826f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_LO_ES 0x1a68 3827f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_LO_ES_BASE_IDX 0 3828f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_HI_ES 0x1a69 3829f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_HI_ES_BASE_IDX 0 3830f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_CHKSUM_HS 0x1aa0 3831f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX 0 3832f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_RSRC4_HS 0x1aa1 3833f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_RSRC4_HS_BASE_IDX 0 3834f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_ADDR_LO_HS 0x1aa2 3835f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX 0 3836f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_ADDR_HI_HS 0x1aa3 3837f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX 0 3838f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_LO_LS_HS 0x1aa4 3839f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_LO_LS_HS_BASE_IDX 0 3840f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_HI_LS_HS 0x1aa5 3841f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_HI_LS_HS_BASE_IDX 0 3842f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_RSRC3_HS 0x1aa7 3843f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_RSRC3_HS_BASE_IDX 0 3844f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_LO_HS 0x1aa8 3845f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_LO_HS_BASE_IDX 0 3846f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_HI_HS 0x1aa9 3847f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_HI_HS_BASE_IDX 0 3848f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_RSRC1_HS 0x1aaa 3849f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_RSRC1_HS_BASE_IDX 0 3850f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_RSRC2_HS 0x1aab 3851f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_RSRC2_HS_BASE_IDX 0 3852f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_0 0x1aac 3853f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_0_BASE_IDX 0 3854f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_1 0x1aad 3855f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_1_BASE_IDX 0 3856f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_2 0x1aae 3857f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_2_BASE_IDX 0 3858f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_3 0x1aaf 3859f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_3_BASE_IDX 0 3860f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_4 0x1ab0 3861f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_4_BASE_IDX 0 3862f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_5 0x1ab1 3863f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_5_BASE_IDX 0 3864f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_6 0x1ab2 3865f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_6_BASE_IDX 0 3866f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_7 0x1ab3 3867f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_7_BASE_IDX 0 3868f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_8 0x1ab4 3869f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_8_BASE_IDX 0 3870f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_9 0x1ab5 3871f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_9_BASE_IDX 0 3872f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_10 0x1ab6 3873f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_10_BASE_IDX 0 3874f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_11 0x1ab7 3875f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_11_BASE_IDX 0 3876f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_12 0x1ab8 3877f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_12_BASE_IDX 0 3878f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_13 0x1ab9 3879f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_13_BASE_IDX 0 3880f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_14 0x1aba 3881f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_14_BASE_IDX 0 3882f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_15 0x1abb 3883f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_15_BASE_IDX 0 3884f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_16 0x1abc 3885f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_16_BASE_IDX 0 3886f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_17 0x1abd 3887f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_17_BASE_IDX 0 3888f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_18 0x1abe 3889f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_18_BASE_IDX 0 3890f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_19 0x1abf 3891f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_19_BASE_IDX 0 3892f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_20 0x1ac0 3893f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_20_BASE_IDX 0 3894f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_21 0x1ac1 3895f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_21_BASE_IDX 0 3896f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_22 0x1ac2 3897f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_22_BASE_IDX 0 3898f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_23 0x1ac3 3899f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_23_BASE_IDX 0 3900f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_24 0x1ac4 3901f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_24_BASE_IDX 0 3902f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_25 0x1ac5 3903f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_25_BASE_IDX 0 3904f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_26 0x1ac6 3905f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_26_BASE_IDX 0 3906f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_27 0x1ac7 3907f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_27_BASE_IDX 0 3908f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_28 0x1ac8 3909f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_28_BASE_IDX 0 3910f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_29 0x1ac9 3911f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_29_BASE_IDX 0 3912f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_30 0x1aca 3913f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_30_BASE_IDX 0 3914f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_31 0x1acb 3915f33ac92fSHawking Zhang #define regSPI_SHADER_USER_DATA_HS_31_BASE_IDX 0 3916f33ac92fSHawking Zhang #define regSPI_SHADER_REQ_CTRL_LSHS 0x1ad0 3917f33ac92fSHawking Zhang #define regSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX 0 3918f33ac92fSHawking Zhang #define regSPI_SHADER_USER_ACCUM_LSHS_0 0x1ad2 3919f33ac92fSHawking Zhang #define regSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX 0 3920f33ac92fSHawking Zhang #define regSPI_SHADER_USER_ACCUM_LSHS_1 0x1ad3 3921f33ac92fSHawking Zhang #define regSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX 0 3922f33ac92fSHawking Zhang #define regSPI_SHADER_USER_ACCUM_LSHS_2 0x1ad4 3923f33ac92fSHawking Zhang #define regSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX 0 3924f33ac92fSHawking Zhang #define regSPI_SHADER_USER_ACCUM_LSHS_3 0x1ad5 3925f33ac92fSHawking Zhang #define regSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX 0 3926f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_LO_LS 0x1ae8 3927f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_LO_LS_BASE_IDX 0 3928f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_HI_LS 0x1ae9 3929f33ac92fSHawking Zhang #define regSPI_SHADER_PGM_HI_LS_BASE_IDX 0 3930f33ac92fSHawking Zhang #define regCOMPUTE_DISPATCH_INITIATOR 0x1ba0 3931f33ac92fSHawking Zhang #define regCOMPUTE_DISPATCH_INITIATOR_BASE_IDX 0 3932f33ac92fSHawking Zhang #define regCOMPUTE_DIM_X 0x1ba1 3933f33ac92fSHawking Zhang #define regCOMPUTE_DIM_X_BASE_IDX 0 3934f33ac92fSHawking Zhang #define regCOMPUTE_DIM_Y 0x1ba2 3935f33ac92fSHawking Zhang #define regCOMPUTE_DIM_Y_BASE_IDX 0 3936f33ac92fSHawking Zhang #define regCOMPUTE_DIM_Z 0x1ba3 3937f33ac92fSHawking Zhang #define regCOMPUTE_DIM_Z_BASE_IDX 0 3938f33ac92fSHawking Zhang #define regCOMPUTE_START_X 0x1ba4 3939f33ac92fSHawking Zhang #define regCOMPUTE_START_X_BASE_IDX 0 3940f33ac92fSHawking Zhang #define regCOMPUTE_START_Y 0x1ba5 3941f33ac92fSHawking Zhang #define regCOMPUTE_START_Y_BASE_IDX 0 3942f33ac92fSHawking Zhang #define regCOMPUTE_START_Z 0x1ba6 3943f33ac92fSHawking Zhang #define regCOMPUTE_START_Z_BASE_IDX 0 3944f33ac92fSHawking Zhang #define regCOMPUTE_NUM_THREAD_X 0x1ba7 3945f33ac92fSHawking Zhang #define regCOMPUTE_NUM_THREAD_X_BASE_IDX 0 3946f33ac92fSHawking Zhang #define regCOMPUTE_NUM_THREAD_Y 0x1ba8 3947f33ac92fSHawking Zhang #define regCOMPUTE_NUM_THREAD_Y_BASE_IDX 0 3948f33ac92fSHawking Zhang #define regCOMPUTE_NUM_THREAD_Z 0x1ba9 3949f33ac92fSHawking Zhang #define regCOMPUTE_NUM_THREAD_Z_BASE_IDX 0 3950f33ac92fSHawking Zhang #define regCOMPUTE_PIPELINESTAT_ENABLE 0x1baa 3951f33ac92fSHawking Zhang #define regCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX 0 3952f33ac92fSHawking Zhang #define regCOMPUTE_PERFCOUNT_ENABLE 0x1bab 3953f33ac92fSHawking Zhang #define regCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX 0 3954f33ac92fSHawking Zhang #define regCOMPUTE_PGM_LO 0x1bac 3955f33ac92fSHawking Zhang #define regCOMPUTE_PGM_LO_BASE_IDX 0 3956f33ac92fSHawking Zhang #define regCOMPUTE_PGM_HI 0x1bad 3957f33ac92fSHawking Zhang #define regCOMPUTE_PGM_HI_BASE_IDX 0 3958f33ac92fSHawking Zhang #define regCOMPUTE_DISPATCH_PKT_ADDR_LO 0x1bae 3959f33ac92fSHawking Zhang #define regCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX 0 3960f33ac92fSHawking Zhang #define regCOMPUTE_DISPATCH_PKT_ADDR_HI 0x1baf 3961f33ac92fSHawking Zhang #define regCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX 0 3962f33ac92fSHawking Zhang #define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO 0x1bb0 3963f33ac92fSHawking Zhang #define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX 0 3964f33ac92fSHawking Zhang #define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI 0x1bb1 3965f33ac92fSHawking Zhang #define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX 0 3966f33ac92fSHawking Zhang #define regCOMPUTE_PGM_RSRC1 0x1bb2 3967f33ac92fSHawking Zhang #define regCOMPUTE_PGM_RSRC1_BASE_IDX 0 3968f33ac92fSHawking Zhang #define regCOMPUTE_PGM_RSRC2 0x1bb3 3969f33ac92fSHawking Zhang #define regCOMPUTE_PGM_RSRC2_BASE_IDX 0 3970f33ac92fSHawking Zhang #define regCOMPUTE_VMID 0x1bb4 3971f33ac92fSHawking Zhang #define regCOMPUTE_VMID_BASE_IDX 0 3972f33ac92fSHawking Zhang #define regCOMPUTE_RESOURCE_LIMITS 0x1bb5 3973f33ac92fSHawking Zhang #define regCOMPUTE_RESOURCE_LIMITS_BASE_IDX 0 3974f33ac92fSHawking Zhang #define regCOMPUTE_DESTINATION_EN_SE0 0x1bb6 3975f33ac92fSHawking Zhang #define regCOMPUTE_DESTINATION_EN_SE0_BASE_IDX 0 3976f33ac92fSHawking Zhang #define regCOMPUTE_STATIC_THREAD_MGMT_SE0 0x1bb6 3977f33ac92fSHawking Zhang #define regCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX 0 3978f33ac92fSHawking Zhang #define regCOMPUTE_DESTINATION_EN_SE1 0x1bb7 3979f33ac92fSHawking Zhang #define regCOMPUTE_DESTINATION_EN_SE1_BASE_IDX 0 3980f33ac92fSHawking Zhang #define regCOMPUTE_STATIC_THREAD_MGMT_SE1 0x1bb7 3981f33ac92fSHawking Zhang #define regCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX 0 3982f33ac92fSHawking Zhang #define regCOMPUTE_TMPRING_SIZE 0x1bb8 3983f33ac92fSHawking Zhang #define regCOMPUTE_TMPRING_SIZE_BASE_IDX 0 3984f33ac92fSHawking Zhang #define regCOMPUTE_DESTINATION_EN_SE2 0x1bb9 3985f33ac92fSHawking Zhang #define regCOMPUTE_DESTINATION_EN_SE2_BASE_IDX 0 3986f33ac92fSHawking Zhang #define regCOMPUTE_STATIC_THREAD_MGMT_SE2 0x1bb9 3987f33ac92fSHawking Zhang #define regCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX 0 3988f33ac92fSHawking Zhang #define regCOMPUTE_DESTINATION_EN_SE3 0x1bba 3989f33ac92fSHawking Zhang #define regCOMPUTE_DESTINATION_EN_SE3_BASE_IDX 0 3990f33ac92fSHawking Zhang #define regCOMPUTE_STATIC_THREAD_MGMT_SE3 0x1bba 3991f33ac92fSHawking Zhang #define regCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX 0 3992f33ac92fSHawking Zhang #define regCOMPUTE_RESTART_X 0x1bbb 3993f33ac92fSHawking Zhang #define regCOMPUTE_RESTART_X_BASE_IDX 0 3994f33ac92fSHawking Zhang #define regCOMPUTE_RESTART_Y 0x1bbc 3995f33ac92fSHawking Zhang #define regCOMPUTE_RESTART_Y_BASE_IDX 0 3996f33ac92fSHawking Zhang #define regCOMPUTE_RESTART_Z 0x1bbd 3997f33ac92fSHawking Zhang #define regCOMPUTE_RESTART_Z_BASE_IDX 0 3998f33ac92fSHawking Zhang #define regCOMPUTE_THREAD_TRACE_ENABLE 0x1bbe 3999f33ac92fSHawking Zhang #define regCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX 0 4000f33ac92fSHawking Zhang #define regCOMPUTE_MISC_RESERVED 0x1bbf 4001f33ac92fSHawking Zhang #define regCOMPUTE_MISC_RESERVED_BASE_IDX 0 4002f33ac92fSHawking Zhang #define regCOMPUTE_DISPATCH_ID 0x1bc0 4003f33ac92fSHawking Zhang #define regCOMPUTE_DISPATCH_ID_BASE_IDX 0 4004f33ac92fSHawking Zhang #define regCOMPUTE_THREADGROUP_ID 0x1bc1 4005f33ac92fSHawking Zhang #define regCOMPUTE_THREADGROUP_ID_BASE_IDX 0 4006f33ac92fSHawking Zhang #define regCOMPUTE_REQ_CTRL 0x1bc2 4007f33ac92fSHawking Zhang #define regCOMPUTE_REQ_CTRL_BASE_IDX 0 4008f33ac92fSHawking Zhang #define regCOMPUTE_USER_ACCUM_0 0x1bc4 4009f33ac92fSHawking Zhang #define regCOMPUTE_USER_ACCUM_0_BASE_IDX 0 4010f33ac92fSHawking Zhang #define regCOMPUTE_USER_ACCUM_1 0x1bc5 4011f33ac92fSHawking Zhang #define regCOMPUTE_USER_ACCUM_1_BASE_IDX 0 4012f33ac92fSHawking Zhang #define regCOMPUTE_USER_ACCUM_2 0x1bc6 4013f33ac92fSHawking Zhang #define regCOMPUTE_USER_ACCUM_2_BASE_IDX 0 4014f33ac92fSHawking Zhang #define regCOMPUTE_USER_ACCUM_3 0x1bc7 4015f33ac92fSHawking Zhang #define regCOMPUTE_USER_ACCUM_3_BASE_IDX 0 4016f33ac92fSHawking Zhang #define regCOMPUTE_PGM_RSRC3 0x1bc8 4017f33ac92fSHawking Zhang #define regCOMPUTE_PGM_RSRC3_BASE_IDX 0 4018f33ac92fSHawking Zhang #define regCOMPUTE_DDID_INDEX 0x1bc9 4019f33ac92fSHawking Zhang #define regCOMPUTE_DDID_INDEX_BASE_IDX 0 4020f33ac92fSHawking Zhang #define regCOMPUTE_SHADER_CHKSUM 0x1bca 4021f33ac92fSHawking Zhang #define regCOMPUTE_SHADER_CHKSUM_BASE_IDX 0 4022f33ac92fSHawking Zhang #define regCOMPUTE_STATIC_THREAD_MGMT_SE4 0x1bcb 4023f33ac92fSHawking Zhang #define regCOMPUTE_STATIC_THREAD_MGMT_SE4_BASE_IDX 0 4024f33ac92fSHawking Zhang #define regCOMPUTE_STATIC_THREAD_MGMT_SE5 0x1bcc 4025f33ac92fSHawking Zhang #define regCOMPUTE_STATIC_THREAD_MGMT_SE5_BASE_IDX 0 4026f33ac92fSHawking Zhang #define regCOMPUTE_STATIC_THREAD_MGMT_SE6 0x1bcd 4027f33ac92fSHawking Zhang #define regCOMPUTE_STATIC_THREAD_MGMT_SE6_BASE_IDX 0 4028f33ac92fSHawking Zhang #define regCOMPUTE_STATIC_THREAD_MGMT_SE7 0x1bce 4029f33ac92fSHawking Zhang #define regCOMPUTE_STATIC_THREAD_MGMT_SE7_BASE_IDX 0 4030f33ac92fSHawking Zhang #define regCOMPUTE_DISPATCH_INTERLEAVE 0x1bcf 4031f33ac92fSHawking Zhang #define regCOMPUTE_DISPATCH_INTERLEAVE_BASE_IDX 0 4032f33ac92fSHawking Zhang #define regCOMPUTE_RELAUNCH 0x1bd0 4033f33ac92fSHawking Zhang #define regCOMPUTE_RELAUNCH_BASE_IDX 0 4034f33ac92fSHawking Zhang #define regCOMPUTE_WAVE_RESTORE_ADDR_LO 0x1bd1 4035f33ac92fSHawking Zhang #define regCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX 0 4036f33ac92fSHawking Zhang #define regCOMPUTE_WAVE_RESTORE_ADDR_HI 0x1bd2 4037f33ac92fSHawking Zhang #define regCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX 0 4038f33ac92fSHawking Zhang #define regCOMPUTE_RELAUNCH2 0x1bd3 4039f33ac92fSHawking Zhang #define regCOMPUTE_RELAUNCH2_BASE_IDX 0 4040f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_0 0x1be0 4041f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_0_BASE_IDX 0 4042f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_1 0x1be1 4043f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_1_BASE_IDX 0 4044f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_2 0x1be2 4045f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_2_BASE_IDX 0 4046f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_3 0x1be3 4047f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_3_BASE_IDX 0 4048f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_4 0x1be4 4049f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_4_BASE_IDX 0 4050f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_5 0x1be5 4051f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_5_BASE_IDX 0 4052f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_6 0x1be6 4053f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_6_BASE_IDX 0 4054f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_7 0x1be7 4055f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_7_BASE_IDX 0 4056f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_8 0x1be8 4057f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_8_BASE_IDX 0 4058f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_9 0x1be9 4059f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_9_BASE_IDX 0 4060f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_10 0x1bea 4061f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_10_BASE_IDX 0 4062f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_11 0x1beb 4063f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_11_BASE_IDX 0 4064f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_12 0x1bec 4065f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_12_BASE_IDX 0 4066f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_13 0x1bed 4067f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_13_BASE_IDX 0 4068f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_14 0x1bee 4069f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_14_BASE_IDX 0 4070f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_15 0x1bef 4071f33ac92fSHawking Zhang #define regCOMPUTE_USER_DATA_15_BASE_IDX 0 4072f33ac92fSHawking Zhang #define regCOMPUTE_DISPATCH_TUNNEL 0x1c1d 4073f33ac92fSHawking Zhang #define regCOMPUTE_DISPATCH_TUNNEL_BASE_IDX 0 4074f33ac92fSHawking Zhang #define regCOMPUTE_DISPATCH_END 0x1c1e 4075f33ac92fSHawking Zhang #define regCOMPUTE_DISPATCH_END_BASE_IDX 0 4076f33ac92fSHawking Zhang #define regCOMPUTE_NOWHERE 0x1c1f 4077f33ac92fSHawking Zhang #define regCOMPUTE_NOWHERE_BASE_IDX 0 4078f33ac92fSHawking Zhang #define regSH_RESERVED_REG0 0x1c20 4079f33ac92fSHawking Zhang #define regSH_RESERVED_REG0_BASE_IDX 0 4080f33ac92fSHawking Zhang #define regSH_RESERVED_REG1 0x1c21 4081f33ac92fSHawking Zhang #define regSH_RESERVED_REG1_BASE_IDX 0 4082f33ac92fSHawking Zhang 4083f33ac92fSHawking Zhang 4084f33ac92fSHawking Zhang // addressBlock: gc_cppdec 4085f33ac92fSHawking Zhang // base address: 0xc080 4086f33ac92fSHawking Zhang #define regCP_CU_MASK_ADDR_LO 0x1dd2 4087f33ac92fSHawking Zhang #define regCP_CU_MASK_ADDR_LO_BASE_IDX 0 4088f33ac92fSHawking Zhang #define regCP_CU_MASK_ADDR_HI 0x1dd3 4089f33ac92fSHawking Zhang #define regCP_CU_MASK_ADDR_HI_BASE_IDX 0 4090f33ac92fSHawking Zhang #define regCP_CU_MASK_CNTL 0x1dd4 4091f33ac92fSHawking Zhang #define regCP_CU_MASK_CNTL_BASE_IDX 0 4092f33ac92fSHawking Zhang #define regCP_EOPQ_WAIT_TIME 0x1dd5 4093f33ac92fSHawking Zhang #define regCP_EOPQ_WAIT_TIME_BASE_IDX 0 4094f33ac92fSHawking Zhang #define regCP_CPC_MGCG_SYNC_CNTL 0x1dd6 4095f33ac92fSHawking Zhang #define regCP_CPC_MGCG_SYNC_CNTL_BASE_IDX 0 4096f33ac92fSHawking Zhang #define regCPC_INT_INFO 0x1dd7 4097f33ac92fSHawking Zhang #define regCPC_INT_INFO_BASE_IDX 0 4098f33ac92fSHawking Zhang #define regCP_VIRT_STATUS 0x1dd8 4099f33ac92fSHawking Zhang #define regCP_VIRT_STATUS_BASE_IDX 0 4100f33ac92fSHawking Zhang #define regCPC_INT_ADDR 0x1dd9 4101f33ac92fSHawking Zhang #define regCPC_INT_ADDR_BASE_IDX 0 4102f33ac92fSHawking Zhang #define regCPC_INT_PASID 0x1dda 4103f33ac92fSHawking Zhang #define regCPC_INT_PASID_BASE_IDX 0 4104f33ac92fSHawking Zhang #define regCP_GFX_ERROR 0x1ddb 4105f33ac92fSHawking Zhang #define regCP_GFX_ERROR_BASE_IDX 0 4106f33ac92fSHawking Zhang #define regCPG_UTCL1_CNTL 0x1ddc 4107f33ac92fSHawking Zhang #define regCPG_UTCL1_CNTL_BASE_IDX 0 4108f33ac92fSHawking Zhang #define regCPC_UTCL1_CNTL 0x1ddd 4109f33ac92fSHawking Zhang #define regCPC_UTCL1_CNTL_BASE_IDX 0 4110f33ac92fSHawking Zhang #define regCPF_UTCL1_CNTL 0x1dde 4111f33ac92fSHawking Zhang #define regCPF_UTCL1_CNTL_BASE_IDX 0 4112f33ac92fSHawking Zhang #define regCP_AQL_SMM_STATUS 0x1ddf 4113f33ac92fSHawking Zhang #define regCP_AQL_SMM_STATUS_BASE_IDX 0 4114f33ac92fSHawking Zhang #define regCP_RB0_BASE 0x1de0 4115f33ac92fSHawking Zhang #define regCP_RB0_BASE_BASE_IDX 0 4116f33ac92fSHawking Zhang #define regCP_RB_BASE 0x1de0 4117f33ac92fSHawking Zhang #define regCP_RB_BASE_BASE_IDX 0 4118f33ac92fSHawking Zhang #define regCP_RB0_CNTL 0x1de1 4119f33ac92fSHawking Zhang #define regCP_RB0_CNTL_BASE_IDX 0 4120f33ac92fSHawking Zhang #define regCP_RB_CNTL 0x1de1 4121f33ac92fSHawking Zhang #define regCP_RB_CNTL_BASE_IDX 0 4122f33ac92fSHawking Zhang #define regCP_RB_RPTR_WR 0x1de2 4123f33ac92fSHawking Zhang #define regCP_RB_RPTR_WR_BASE_IDX 0 4124f33ac92fSHawking Zhang #define regCP_RB0_RPTR_ADDR 0x1de3 4125f33ac92fSHawking Zhang #define regCP_RB0_RPTR_ADDR_BASE_IDX 0 4126f33ac92fSHawking Zhang #define regCP_RB_RPTR_ADDR 0x1de3 4127f33ac92fSHawking Zhang #define regCP_RB_RPTR_ADDR_BASE_IDX 0 4128f33ac92fSHawking Zhang #define regCP_RB0_RPTR_ADDR_HI 0x1de4 4129f33ac92fSHawking Zhang #define regCP_RB0_RPTR_ADDR_HI_BASE_IDX 0 4130f33ac92fSHawking Zhang #define regCP_RB_RPTR_ADDR_HI 0x1de4 4131f33ac92fSHawking Zhang #define regCP_RB_RPTR_ADDR_HI_BASE_IDX 0 4132f33ac92fSHawking Zhang #define regCP_RB0_BUFSZ_MASK 0x1de5 4133f33ac92fSHawking Zhang #define regCP_RB0_BUFSZ_MASK_BASE_IDX 0 4134f33ac92fSHawking Zhang #define regCP_RB_BUFSZ_MASK 0x1de5 4135f33ac92fSHawking Zhang #define regCP_RB_BUFSZ_MASK_BASE_IDX 0 4136f33ac92fSHawking Zhang #define regCP_INT_CNTL 0x1de9 4137f33ac92fSHawking Zhang #define regCP_INT_CNTL_BASE_IDX 0 4138f33ac92fSHawking Zhang #define regCP_INT_STATUS 0x1dea 4139f33ac92fSHawking Zhang #define regCP_INT_STATUS_BASE_IDX 0 4140f33ac92fSHawking Zhang #define regCP_DEVICE_ID 0x1deb 4141f33ac92fSHawking Zhang #define regCP_DEVICE_ID_BASE_IDX 0 4142f33ac92fSHawking Zhang #define regCP_ME0_PIPE_PRIORITY_CNTS 0x1dec 4143f33ac92fSHawking Zhang #define regCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX 0 4144f33ac92fSHawking Zhang #define regCP_RING_PRIORITY_CNTS 0x1dec 4145f33ac92fSHawking Zhang #define regCP_RING_PRIORITY_CNTS_BASE_IDX 0 4146f33ac92fSHawking Zhang #define regCP_ME0_PIPE0_PRIORITY 0x1ded 4147f33ac92fSHawking Zhang #define regCP_ME0_PIPE0_PRIORITY_BASE_IDX 0 4148f33ac92fSHawking Zhang #define regCP_RING0_PRIORITY 0x1ded 4149f33ac92fSHawking Zhang #define regCP_RING0_PRIORITY_BASE_IDX 0 4150f33ac92fSHawking Zhang #define regCP_ME0_PIPE1_PRIORITY 0x1dee 4151f33ac92fSHawking Zhang #define regCP_ME0_PIPE1_PRIORITY_BASE_IDX 0 4152f33ac92fSHawking Zhang #define regCP_RING1_PRIORITY 0x1dee 4153f33ac92fSHawking Zhang #define regCP_RING1_PRIORITY_BASE_IDX 0 4154f33ac92fSHawking Zhang #define regCP_FATAL_ERROR 0x1df0 4155f33ac92fSHawking Zhang #define regCP_FATAL_ERROR_BASE_IDX 0 4156f33ac92fSHawking Zhang #define regCP_RB_VMID 0x1df1 4157f33ac92fSHawking Zhang #define regCP_RB_VMID_BASE_IDX 0 4158f33ac92fSHawking Zhang #define regCP_ME0_PIPE0_VMID 0x1df2 4159f33ac92fSHawking Zhang #define regCP_ME0_PIPE0_VMID_BASE_IDX 0 4160f33ac92fSHawking Zhang #define regCP_ME0_PIPE1_VMID 0x1df3 4161f33ac92fSHawking Zhang #define regCP_ME0_PIPE1_VMID_BASE_IDX 0 4162f33ac92fSHawking Zhang #define regCP_RB0_WPTR 0x1df4 4163f33ac92fSHawking Zhang #define regCP_RB0_WPTR_BASE_IDX 0 4164f33ac92fSHawking Zhang #define regCP_RB_WPTR 0x1df4 4165f33ac92fSHawking Zhang #define regCP_RB_WPTR_BASE_IDX 0 4166f33ac92fSHawking Zhang #define regCP_RB0_WPTR_HI 0x1df5 4167f33ac92fSHawking Zhang #define regCP_RB0_WPTR_HI_BASE_IDX 0 4168f33ac92fSHawking Zhang #define regCP_RB_WPTR_HI 0x1df5 4169f33ac92fSHawking Zhang #define regCP_RB_WPTR_HI_BASE_IDX 0 4170f33ac92fSHawking Zhang #define regCP_RB1_WPTR 0x1df6 4171f33ac92fSHawking Zhang #define regCP_RB1_WPTR_BASE_IDX 0 4172f33ac92fSHawking Zhang #define regCP_RB1_WPTR_HI 0x1df7 4173f33ac92fSHawking Zhang #define regCP_RB1_WPTR_HI_BASE_IDX 0 4174f33ac92fSHawking Zhang #define regCP_PROCESS_QUANTUM 0x1df9 4175f33ac92fSHawking Zhang #define regCP_PROCESS_QUANTUM_BASE_IDX 0 4176f33ac92fSHawking Zhang #define regCP_RB_DOORBELL_RANGE_LOWER 0x1dfa 4177f33ac92fSHawking Zhang #define regCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX 0 4178f33ac92fSHawking Zhang #define regCP_RB_DOORBELL_RANGE_UPPER 0x1dfb 4179f33ac92fSHawking Zhang #define regCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX 0 4180f33ac92fSHawking Zhang #define regCP_MEC_DOORBELL_RANGE_LOWER 0x1dfc 4181f33ac92fSHawking Zhang #define regCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX 0 4182f33ac92fSHawking Zhang #define regCP_MEC_DOORBELL_RANGE_UPPER 0x1dfd 4183f33ac92fSHawking Zhang #define regCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX 0 4184f33ac92fSHawking Zhang #define regCPG_UTCL1_ERROR 0x1dfe 4185f33ac92fSHawking Zhang #define regCPG_UTCL1_ERROR_BASE_IDX 0 4186f33ac92fSHawking Zhang #define regCPC_UTCL1_ERROR 0x1dff 4187f33ac92fSHawking Zhang #define regCPC_UTCL1_ERROR_BASE_IDX 0 4188f33ac92fSHawking Zhang #define regCP_RB1_BASE 0x1e00 4189f33ac92fSHawking Zhang #define regCP_RB1_BASE_BASE_IDX 0 4190f33ac92fSHawking Zhang #define regCP_RB1_CNTL 0x1e01 4191f33ac92fSHawking Zhang #define regCP_RB1_CNTL_BASE_IDX 0 4192f33ac92fSHawking Zhang #define regCP_RB1_RPTR_ADDR 0x1e02 4193f33ac92fSHawking Zhang #define regCP_RB1_RPTR_ADDR_BASE_IDX 0 4194f33ac92fSHawking Zhang #define regCP_RB1_RPTR_ADDR_HI 0x1e03 4195f33ac92fSHawking Zhang #define regCP_RB1_RPTR_ADDR_HI_BASE_IDX 0 4196f33ac92fSHawking Zhang #define regCP_RB1_BUFSZ_MASK 0x1e04 4197f33ac92fSHawking Zhang #define regCP_RB1_BUFSZ_MASK_BASE_IDX 0 4198f33ac92fSHawking Zhang #define regCP_INT_CNTL_RING0 0x1e0a 4199f33ac92fSHawking Zhang #define regCP_INT_CNTL_RING0_BASE_IDX 0 4200f33ac92fSHawking Zhang #define regCP_INT_CNTL_RING1 0x1e0b 4201f33ac92fSHawking Zhang #define regCP_INT_CNTL_RING1_BASE_IDX 0 4202f33ac92fSHawking Zhang #define regCP_INT_STATUS_RING0 0x1e0d 4203f33ac92fSHawking Zhang #define regCP_INT_STATUS_RING0_BASE_IDX 0 4204f33ac92fSHawking Zhang #define regCP_INT_STATUS_RING1 0x1e0e 4205f33ac92fSHawking Zhang #define regCP_INT_STATUS_RING1_BASE_IDX 0 4206f33ac92fSHawking Zhang #define regCP_ME_F32_INTERRUPT 0x1e13 4207f33ac92fSHawking Zhang #define regCP_ME_F32_INTERRUPT_BASE_IDX 0 4208f33ac92fSHawking Zhang #define regCP_PFP_F32_INTERRUPT 0x1e14 4209f33ac92fSHawking Zhang #define regCP_PFP_F32_INTERRUPT_BASE_IDX 0 4210f33ac92fSHawking Zhang #define regCP_MEC1_F32_INTERRUPT 0x1e16 4211f33ac92fSHawking Zhang #define regCP_MEC1_F32_INTERRUPT_BASE_IDX 0 4212f33ac92fSHawking Zhang #define regCP_MEC2_F32_INTERRUPT 0x1e17 4213f33ac92fSHawking Zhang #define regCP_MEC2_F32_INTERRUPT_BASE_IDX 0 4214f33ac92fSHawking Zhang #define regCP_PWR_CNTL 0x1e18 4215f33ac92fSHawking Zhang #define regCP_PWR_CNTL_BASE_IDX 0 4216f33ac92fSHawking Zhang #define regCP_ECC_FIRSTOCCURRENCE 0x1e1a 4217f33ac92fSHawking Zhang #define regCP_ECC_FIRSTOCCURRENCE_BASE_IDX 0 4218f33ac92fSHawking Zhang #define regCP_ECC_FIRSTOCCURRENCE_RING0 0x1e1b 4219f33ac92fSHawking Zhang #define regCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX 0 4220f33ac92fSHawking Zhang #define regCP_ECC_FIRSTOCCURRENCE_RING1 0x1e1c 4221f33ac92fSHawking Zhang #define regCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX 0 4222f33ac92fSHawking Zhang #define regGB_EDC_MODE 0x1e1e 4223f33ac92fSHawking Zhang #define regGB_EDC_MODE_BASE_IDX 0 42247c8e4a25SChengming Gui #define regCP_DEBUG 0x1e1f 4225f33ac92fSHawking Zhang #define regCP_DEBUG_BASE_IDX 0 4226f33ac92fSHawking Zhang #define regCP_CPC_DEBUG 0x1e21 4227f33ac92fSHawking Zhang #define regCP_CPC_DEBUG_BASE_IDX 0 4228f33ac92fSHawking Zhang #define regCP_PQ_WPTR_POLL_CNTL 0x1e23 4229f33ac92fSHawking Zhang #define regCP_PQ_WPTR_POLL_CNTL_BASE_IDX 0 4230f33ac92fSHawking Zhang #define regCP_PQ_WPTR_POLL_CNTL1 0x1e24 4231f33ac92fSHawking Zhang #define regCP_PQ_WPTR_POLL_CNTL1_BASE_IDX 0 4232f33ac92fSHawking Zhang #define regCP_ME1_PIPE0_INT_CNTL 0x1e25 4233f33ac92fSHawking Zhang #define regCP_ME1_PIPE0_INT_CNTL_BASE_IDX 0 4234f33ac92fSHawking Zhang #define regCP_ME1_PIPE1_INT_CNTL 0x1e26 4235f33ac92fSHawking Zhang #define regCP_ME1_PIPE1_INT_CNTL_BASE_IDX 0 4236f33ac92fSHawking Zhang #define regCP_ME1_PIPE2_INT_CNTL 0x1e27 4237f33ac92fSHawking Zhang #define regCP_ME1_PIPE2_INT_CNTL_BASE_IDX 0 4238f33ac92fSHawking Zhang #define regCP_ME1_PIPE3_INT_CNTL 0x1e28 4239f33ac92fSHawking Zhang #define regCP_ME1_PIPE3_INT_CNTL_BASE_IDX 0 4240f33ac92fSHawking Zhang #define regCP_ME2_PIPE0_INT_CNTL 0x1e29 4241f33ac92fSHawking Zhang #define regCP_ME2_PIPE0_INT_CNTL_BASE_IDX 0 4242f33ac92fSHawking Zhang #define regCP_ME2_PIPE1_INT_CNTL 0x1e2a 4243f33ac92fSHawking Zhang #define regCP_ME2_PIPE1_INT_CNTL_BASE_IDX 0 4244f33ac92fSHawking Zhang #define regCP_ME2_PIPE2_INT_CNTL 0x1e2b 4245f33ac92fSHawking Zhang #define regCP_ME2_PIPE2_INT_CNTL_BASE_IDX 0 4246f33ac92fSHawking Zhang #define regCP_ME2_PIPE3_INT_CNTL 0x1e2c 4247f33ac92fSHawking Zhang #define regCP_ME2_PIPE3_INT_CNTL_BASE_IDX 0 4248f33ac92fSHawking Zhang #define regCP_ME1_PIPE0_INT_STATUS 0x1e2d 4249f33ac92fSHawking Zhang #define regCP_ME1_PIPE0_INT_STATUS_BASE_IDX 0 4250f33ac92fSHawking Zhang #define regCP_ME1_PIPE1_INT_STATUS 0x1e2e 4251f33ac92fSHawking Zhang #define regCP_ME1_PIPE1_INT_STATUS_BASE_IDX 0 4252f33ac92fSHawking Zhang #define regCP_ME1_PIPE2_INT_STATUS 0x1e2f 4253f33ac92fSHawking Zhang #define regCP_ME1_PIPE2_INT_STATUS_BASE_IDX 0 4254f33ac92fSHawking Zhang #define regCP_ME1_PIPE3_INT_STATUS 0x1e30 4255f33ac92fSHawking Zhang #define regCP_ME1_PIPE3_INT_STATUS_BASE_IDX 0 4256f33ac92fSHawking Zhang #define regCP_ME2_PIPE0_INT_STATUS 0x1e31 4257f33ac92fSHawking Zhang #define regCP_ME2_PIPE0_INT_STATUS_BASE_IDX 0 4258f33ac92fSHawking Zhang #define regCP_ME2_PIPE1_INT_STATUS 0x1e32 4259f33ac92fSHawking Zhang #define regCP_ME2_PIPE1_INT_STATUS_BASE_IDX 0 4260f33ac92fSHawking Zhang #define regCP_ME2_PIPE2_INT_STATUS 0x1e33 4261f33ac92fSHawking Zhang #define regCP_ME2_PIPE2_INT_STATUS_BASE_IDX 0 4262f33ac92fSHawking Zhang #define regCP_ME2_PIPE3_INT_STATUS 0x1e34 4263f33ac92fSHawking Zhang #define regCP_ME2_PIPE3_INT_STATUS_BASE_IDX 0 4264f33ac92fSHawking Zhang #define regCP_GFX_QUEUE_INDEX 0x1e37 4265f33ac92fSHawking Zhang #define regCP_GFX_QUEUE_INDEX_BASE_IDX 0 4266f33ac92fSHawking Zhang #define regCC_GC_EDC_CONFIG 0x1e38 4267f33ac92fSHawking Zhang #define regCC_GC_EDC_CONFIG_BASE_IDX 0 4268f33ac92fSHawking Zhang #define regCP_ME1_PIPE_PRIORITY_CNTS 0x1e39 4269f33ac92fSHawking Zhang #define regCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX 0 4270f33ac92fSHawking Zhang #define regCP_ME1_PIPE0_PRIORITY 0x1e3a 4271f33ac92fSHawking Zhang #define regCP_ME1_PIPE0_PRIORITY_BASE_IDX 0 4272f33ac92fSHawking Zhang #define regCP_ME1_PIPE1_PRIORITY 0x1e3b 4273f33ac92fSHawking Zhang #define regCP_ME1_PIPE1_PRIORITY_BASE_IDX 0 4274f33ac92fSHawking Zhang #define regCP_ME1_PIPE2_PRIORITY 0x1e3c 4275f33ac92fSHawking Zhang #define regCP_ME1_PIPE2_PRIORITY_BASE_IDX 0 4276f33ac92fSHawking Zhang #define regCP_ME1_PIPE3_PRIORITY 0x1e3d 4277f33ac92fSHawking Zhang #define regCP_ME1_PIPE3_PRIORITY_BASE_IDX 0 4278f33ac92fSHawking Zhang #define regCP_ME2_PIPE_PRIORITY_CNTS 0x1e3e 4279f33ac92fSHawking Zhang #define regCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX 0 4280f33ac92fSHawking Zhang #define regCP_ME2_PIPE0_PRIORITY 0x1e3f 4281f33ac92fSHawking Zhang #define regCP_ME2_PIPE0_PRIORITY_BASE_IDX 0 4282f33ac92fSHawking Zhang #define regCP_ME2_PIPE1_PRIORITY 0x1e40 4283f33ac92fSHawking Zhang #define regCP_ME2_PIPE1_PRIORITY_BASE_IDX 0 4284f33ac92fSHawking Zhang #define regCP_ME2_PIPE2_PRIORITY 0x1e41 4285f33ac92fSHawking Zhang #define regCP_ME2_PIPE2_PRIORITY_BASE_IDX 0 4286f33ac92fSHawking Zhang #define regCP_ME2_PIPE3_PRIORITY 0x1e42 4287f33ac92fSHawking Zhang #define regCP_ME2_PIPE3_PRIORITY_BASE_IDX 0 4288f33ac92fSHawking Zhang #define regCP_PFP_PRGRM_CNTR_START 0x1e44 4289f33ac92fSHawking Zhang #define regCP_PFP_PRGRM_CNTR_START_BASE_IDX 0 4290f33ac92fSHawking Zhang #define regCP_ME_PRGRM_CNTR_START 0x1e45 4291f33ac92fSHawking Zhang #define regCP_ME_PRGRM_CNTR_START_BASE_IDX 0 4292f33ac92fSHawking Zhang #define regCP_MEC1_PRGRM_CNTR_START 0x1e46 4293f33ac92fSHawking Zhang #define regCP_MEC1_PRGRM_CNTR_START_BASE_IDX 0 4294f33ac92fSHawking Zhang #define regCP_MEC2_PRGRM_CNTR_START 0x1e47 4295f33ac92fSHawking Zhang #define regCP_MEC2_PRGRM_CNTR_START_BASE_IDX 0 4296f33ac92fSHawking Zhang #define regCP_PFP_INTR_ROUTINE_START 0x1e49 4297f33ac92fSHawking Zhang #define regCP_PFP_INTR_ROUTINE_START_BASE_IDX 0 4298f33ac92fSHawking Zhang #define regCP_ME_INTR_ROUTINE_START 0x1e4a 4299f33ac92fSHawking Zhang #define regCP_ME_INTR_ROUTINE_START_BASE_IDX 0 4300f33ac92fSHawking Zhang #define regCP_MEC1_INTR_ROUTINE_START 0x1e4b 4301f33ac92fSHawking Zhang #define regCP_MEC1_INTR_ROUTINE_START_BASE_IDX 0 4302f33ac92fSHawking Zhang #define regCP_MEC2_INTR_ROUTINE_START 0x1e4c 4303f33ac92fSHawking Zhang #define regCP_MEC2_INTR_ROUTINE_START_BASE_IDX 0 4304f33ac92fSHawking Zhang #define regCP_CONTEXT_CNTL 0x1e4d 4305f33ac92fSHawking Zhang #define regCP_CONTEXT_CNTL_BASE_IDX 0 4306f33ac92fSHawking Zhang #define regCP_MAX_CONTEXT 0x1e4e 4307f33ac92fSHawking Zhang #define regCP_MAX_CONTEXT_BASE_IDX 0 4308f33ac92fSHawking Zhang #define regCP_IQ_WAIT_TIME1 0x1e4f 4309f33ac92fSHawking Zhang #define regCP_IQ_WAIT_TIME1_BASE_IDX 0 4310f33ac92fSHawking Zhang #define regCP_IQ_WAIT_TIME2 0x1e50 4311f33ac92fSHawking Zhang #define regCP_IQ_WAIT_TIME2_BASE_IDX 0 4312f33ac92fSHawking Zhang #define regCP_RB0_BASE_HI 0x1e51 4313f33ac92fSHawking Zhang #define regCP_RB0_BASE_HI_BASE_IDX 0 4314f33ac92fSHawking Zhang #define regCP_RB1_BASE_HI 0x1e52 4315f33ac92fSHawking Zhang #define regCP_RB1_BASE_HI_BASE_IDX 0 4316f33ac92fSHawking Zhang #define regCP_VMID_RESET 0x1e53 4317f33ac92fSHawking Zhang #define regCP_VMID_RESET_BASE_IDX 0 4318f33ac92fSHawking Zhang #define regCPC_INT_CNTL 0x1e54 4319f33ac92fSHawking Zhang #define regCPC_INT_CNTL_BASE_IDX 0 4320f33ac92fSHawking Zhang #define regCPC_INT_STATUS 0x1e55 4321f33ac92fSHawking Zhang #define regCPC_INT_STATUS_BASE_IDX 0 4322f33ac92fSHawking Zhang #define regCP_VMID_PREEMPT 0x1e56 4323f33ac92fSHawking Zhang #define regCP_VMID_PREEMPT_BASE_IDX 0 4324f33ac92fSHawking Zhang #define regCPC_INT_CNTX_ID 0x1e57 4325f33ac92fSHawking Zhang #define regCPC_INT_CNTX_ID_BASE_IDX 0 4326f33ac92fSHawking Zhang #define regCP_PQ_STATUS 0x1e58 4327f33ac92fSHawking Zhang #define regCP_PQ_STATUS_BASE_IDX 0 4328f33ac92fSHawking Zhang #define regCP_PFP_PRGRM_CNTR_START_HI 0x1e59 4329f33ac92fSHawking Zhang #define regCP_PFP_PRGRM_CNTR_START_HI_BASE_IDX 0 4330f33ac92fSHawking Zhang #define regCP_MAX_DRAW_COUNT 0x1e5c 4331f33ac92fSHawking Zhang #define regCP_MAX_DRAW_COUNT_BASE_IDX 0 4332f33ac92fSHawking Zhang #define regCP_MEC1_F32_INT_DIS 0x1e5d 4333f33ac92fSHawking Zhang #define regCP_MEC1_F32_INT_DIS_BASE_IDX 0 4334f33ac92fSHawking Zhang #define regCP_MEC2_F32_INT_DIS 0x1e5e 4335f33ac92fSHawking Zhang #define regCP_MEC2_F32_INT_DIS_BASE_IDX 0 4336f33ac92fSHawking Zhang #define regCP_VMID_STATUS 0x1e5f 4337f33ac92fSHawking Zhang #define regCP_VMID_STATUS_BASE_IDX 0 4338f33ac92fSHawking Zhang #define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO 0x1e60 4339f33ac92fSHawking Zhang #define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0 4340f33ac92fSHawking Zhang #define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI 0x1e61 4341f33ac92fSHawking Zhang #define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0 4342f33ac92fSHawking Zhang #define regCPC_SUSPEND_CTX_SAVE_CONTROL 0x1e62 4343f33ac92fSHawking Zhang #define regCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX 0 4344f33ac92fSHawking Zhang #define regCPC_SUSPEND_CNTL_STACK_OFFSET 0x1e63 4345f33ac92fSHawking Zhang #define regCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX 0 4346f33ac92fSHawking Zhang #define regCPC_SUSPEND_CNTL_STACK_SIZE 0x1e64 4347f33ac92fSHawking Zhang #define regCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX 0 4348f33ac92fSHawking Zhang #define regCPC_SUSPEND_WG_STATE_OFFSET 0x1e65 4349f33ac92fSHawking Zhang #define regCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX 0 4350f33ac92fSHawking Zhang #define regCPC_SUSPEND_CTX_SAVE_SIZE 0x1e66 4351f33ac92fSHawking Zhang #define regCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX 0 4352f33ac92fSHawking Zhang #define regCPC_OS_PIPES 0x1e67 4353f33ac92fSHawking Zhang #define regCPC_OS_PIPES_BASE_IDX 0 4354f33ac92fSHawking Zhang #define regCP_SUSPEND_RESUME_REQ 0x1e68 4355f33ac92fSHawking Zhang #define regCP_SUSPEND_RESUME_REQ_BASE_IDX 0 4356f33ac92fSHawking Zhang #define regCP_SUSPEND_CNTL 0x1e69 4357f33ac92fSHawking Zhang #define regCP_SUSPEND_CNTL_BASE_IDX 0 4358f33ac92fSHawking Zhang #define regCP_IQ_WAIT_TIME3 0x1e6a 4359f33ac92fSHawking Zhang #define regCP_IQ_WAIT_TIME3_BASE_IDX 0 4360f33ac92fSHawking Zhang #define regCPC_DDID_BASE_ADDR_LO 0x1e6b 4361f33ac92fSHawking Zhang #define regCPC_DDID_BASE_ADDR_LO_BASE_IDX 0 4362f33ac92fSHawking Zhang #define regCP_DDID_BASE_ADDR_LO 0x1e6b 4363f33ac92fSHawking Zhang #define regCP_DDID_BASE_ADDR_LO_BASE_IDX 0 4364f33ac92fSHawking Zhang #define regCPC_DDID_BASE_ADDR_HI 0x1e6c 4365f33ac92fSHawking Zhang #define regCPC_DDID_BASE_ADDR_HI_BASE_IDX 0 4366f33ac92fSHawking Zhang #define regCP_DDID_BASE_ADDR_HI 0x1e6c 4367f33ac92fSHawking Zhang #define regCP_DDID_BASE_ADDR_HI_BASE_IDX 0 4368f33ac92fSHawking Zhang #define regCPC_DDID_CNTL 0x1e6d 4369f33ac92fSHawking Zhang #define regCPC_DDID_CNTL_BASE_IDX 0 4370f33ac92fSHawking Zhang #define regCP_DDID_CNTL 0x1e6d 4371f33ac92fSHawking Zhang #define regCP_DDID_CNTL_BASE_IDX 0 4372f33ac92fSHawking Zhang #define regCP_GFX_DDID_INFLIGHT_COUNT 0x1e6e 4373f33ac92fSHawking Zhang #define regCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX 0 4374f33ac92fSHawking Zhang #define regCP_GFX_DDID_WPTR 0x1e6f 4375f33ac92fSHawking Zhang #define regCP_GFX_DDID_WPTR_BASE_IDX 0 4376f33ac92fSHawking Zhang #define regCP_GFX_DDID_RPTR 0x1e70 4377f33ac92fSHawking Zhang #define regCP_GFX_DDID_RPTR_BASE_IDX 0 4378f33ac92fSHawking Zhang #define regCP_GFX_DDID_DELTA_RPT_COUNT 0x1e71 4379f33ac92fSHawking Zhang #define regCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX 0 4380f33ac92fSHawking Zhang #define regCP_GFX_HPD_STATUS0 0x1e72 4381f33ac92fSHawking Zhang #define regCP_GFX_HPD_STATUS0_BASE_IDX 0 4382f33ac92fSHawking Zhang #define regCP_GFX_HPD_CONTROL0 0x1e73 4383f33ac92fSHawking Zhang #define regCP_GFX_HPD_CONTROL0_BASE_IDX 0 4384f33ac92fSHawking Zhang #define regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO 0x1e74 4385f33ac92fSHawking Zhang #define regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX 0 4386f33ac92fSHawking Zhang #define regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI 0x1e75 4387f33ac92fSHawking Zhang #define regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX 0 4388f33ac92fSHawking Zhang #define regCP_GFX_HPD_OSPRE_FENCE_DATA_LO 0x1e76 4389f33ac92fSHawking Zhang #define regCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX 0 4390f33ac92fSHawking Zhang #define regCP_GFX_HPD_OSPRE_FENCE_DATA_HI 0x1e77 4391f33ac92fSHawking Zhang #define regCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX 0 4392f33ac92fSHawking Zhang #define regCP_GFX_INDEX_MUTEX 0x1e78 4393f33ac92fSHawking Zhang #define regCP_GFX_INDEX_MUTEX_BASE_IDX 0 4394f33ac92fSHawking Zhang #define regCP_ME_PRGRM_CNTR_START_HI 0x1e79 4395f33ac92fSHawking Zhang #define regCP_ME_PRGRM_CNTR_START_HI_BASE_IDX 0 4396f33ac92fSHawking Zhang #define regCP_PFP_INTR_ROUTINE_START_HI 0x1e7a 4397f33ac92fSHawking Zhang #define regCP_PFP_INTR_ROUTINE_START_HI_BASE_IDX 0 4398f33ac92fSHawking Zhang #define regCP_ME_INTR_ROUTINE_START_HI 0x1e7b 4399f33ac92fSHawking Zhang #define regCP_ME_INTR_ROUTINE_START_HI_BASE_IDX 0 4400f33ac92fSHawking Zhang #define regCP_GFX_MQD_BASE_ADDR 0x1e7e 4401f33ac92fSHawking Zhang #define regCP_GFX_MQD_BASE_ADDR_BASE_IDX 0 4402f33ac92fSHawking Zhang #define regCP_GFX_MQD_BASE_ADDR_HI 0x1e7f 4403f33ac92fSHawking Zhang #define regCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX 0 4404f33ac92fSHawking Zhang #define regCP_GFX_HQD_ACTIVE 0x1e80 4405f33ac92fSHawking Zhang #define regCP_GFX_HQD_ACTIVE_BASE_IDX 0 4406f33ac92fSHawking Zhang #define regCP_GFX_HQD_VMID 0x1e81 4407f33ac92fSHawking Zhang #define regCP_GFX_HQD_VMID_BASE_IDX 0 4408f33ac92fSHawking Zhang #define regCP_GFX_HQD_QUEUE_PRIORITY 0x1e84 4409f33ac92fSHawking Zhang #define regCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX 0 4410f33ac92fSHawking Zhang #define regCP_GFX_HQD_QUANTUM 0x1e85 4411f33ac92fSHawking Zhang #define regCP_GFX_HQD_QUANTUM_BASE_IDX 0 4412f33ac92fSHawking Zhang #define regCP_GFX_HQD_BASE 0x1e86 4413f33ac92fSHawking Zhang #define regCP_GFX_HQD_BASE_BASE_IDX 0 4414f33ac92fSHawking Zhang #define regCP_GFX_HQD_BASE_HI 0x1e87 4415f33ac92fSHawking Zhang #define regCP_GFX_HQD_BASE_HI_BASE_IDX 0 4416f33ac92fSHawking Zhang #define regCP_GFX_HQD_RPTR 0x1e88 4417f33ac92fSHawking Zhang #define regCP_GFX_HQD_RPTR_BASE_IDX 0 4418f33ac92fSHawking Zhang #define regCP_GFX_HQD_RPTR_ADDR 0x1e89 4419f33ac92fSHawking Zhang #define regCP_GFX_HQD_RPTR_ADDR_BASE_IDX 0 4420f33ac92fSHawking Zhang #define regCP_GFX_HQD_RPTR_ADDR_HI 0x1e8a 4421f33ac92fSHawking Zhang #define regCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX 0 4422f33ac92fSHawking Zhang #define regCP_RB_WPTR_POLL_ADDR_LO 0x1e8b 4423f33ac92fSHawking Zhang #define regCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 4424f33ac92fSHawking Zhang #define regCP_RB_WPTR_POLL_ADDR_HI 0x1e8c 4425f33ac92fSHawking Zhang #define regCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 4426f33ac92fSHawking Zhang #define regCP_RB_DOORBELL_CONTROL 0x1e8d 4427f33ac92fSHawking Zhang #define regCP_RB_DOORBELL_CONTROL_BASE_IDX 0 4428f33ac92fSHawking Zhang #define regCP_GFX_HQD_OFFSET 0x1e8e 4429f33ac92fSHawking Zhang #define regCP_GFX_HQD_OFFSET_BASE_IDX 0 4430f33ac92fSHawking Zhang #define regCP_GFX_HQD_CNTL 0x1e8f 4431f33ac92fSHawking Zhang #define regCP_GFX_HQD_CNTL_BASE_IDX 0 4432f33ac92fSHawking Zhang #define regCP_GFX_HQD_CSMD_RPTR 0x1e90 4433f33ac92fSHawking Zhang #define regCP_GFX_HQD_CSMD_RPTR_BASE_IDX 0 4434f33ac92fSHawking Zhang #define regCP_GFX_HQD_WPTR 0x1e91 4435f33ac92fSHawking Zhang #define regCP_GFX_HQD_WPTR_BASE_IDX 0 4436f33ac92fSHawking Zhang #define regCP_GFX_HQD_WPTR_HI 0x1e92 4437f33ac92fSHawking Zhang #define regCP_GFX_HQD_WPTR_HI_BASE_IDX 0 4438f33ac92fSHawking Zhang #define regCP_GFX_HQD_DEQUEUE_REQUEST 0x1e93 4439f33ac92fSHawking Zhang #define regCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX 0 4440f33ac92fSHawking Zhang #define regCP_GFX_HQD_MAPPED 0x1e94 4441f33ac92fSHawking Zhang #define regCP_GFX_HQD_MAPPED_BASE_IDX 0 4442f33ac92fSHawking Zhang #define regCP_GFX_HQD_QUE_MGR_CONTROL 0x1e95 4443f33ac92fSHawking Zhang #define regCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX 0 4444f33ac92fSHawking Zhang #define regCP_GFX_HQD_IQ_TIMER 0x1e96 4445f33ac92fSHawking Zhang #define regCP_GFX_HQD_IQ_TIMER_BASE_IDX 0 4446f33ac92fSHawking Zhang #define regCP_GFX_HQD_HQ_STATUS0 0x1e98 4447f33ac92fSHawking Zhang #define regCP_GFX_HQD_HQ_STATUS0_BASE_IDX 0 4448f33ac92fSHawking Zhang #define regCP_GFX_HQD_HQ_CONTROL0 0x1e99 4449f33ac92fSHawking Zhang #define regCP_GFX_HQD_HQ_CONTROL0_BASE_IDX 0 4450f33ac92fSHawking Zhang #define regCP_GFX_MQD_CONTROL 0x1e9a 4451f33ac92fSHawking Zhang #define regCP_GFX_MQD_CONTROL_BASE_IDX 0 4452f33ac92fSHawking Zhang #define regCP_HQD_GFX_CONTROL 0x1e9f 4453f33ac92fSHawking Zhang #define regCP_HQD_GFX_CONTROL_BASE_IDX 0 4454f33ac92fSHawking Zhang #define regCP_HQD_GFX_STATUS 0x1ea0 4455f33ac92fSHawking Zhang #define regCP_HQD_GFX_STATUS_BASE_IDX 0 4456f33ac92fSHawking Zhang #define regCP_DMA_WATCH0_ADDR_LO 0x1ec0 4457f33ac92fSHawking Zhang #define regCP_DMA_WATCH0_ADDR_LO_BASE_IDX 0 4458f33ac92fSHawking Zhang #define regCP_DMA_WATCH0_ADDR_HI 0x1ec1 4459f33ac92fSHawking Zhang #define regCP_DMA_WATCH0_ADDR_HI_BASE_IDX 0 4460f33ac92fSHawking Zhang #define regCP_DMA_WATCH0_MASK 0x1ec2 4461f33ac92fSHawking Zhang #define regCP_DMA_WATCH0_MASK_BASE_IDX 0 4462f33ac92fSHawking Zhang #define regCP_DMA_WATCH0_CNTL 0x1ec3 4463f33ac92fSHawking Zhang #define regCP_DMA_WATCH0_CNTL_BASE_IDX 0 4464f33ac92fSHawking Zhang #define regCP_DMA_WATCH1_ADDR_LO 0x1ec4 4465f33ac92fSHawking Zhang #define regCP_DMA_WATCH1_ADDR_LO_BASE_IDX 0 4466f33ac92fSHawking Zhang #define regCP_DMA_WATCH1_ADDR_HI 0x1ec5 4467f33ac92fSHawking Zhang #define regCP_DMA_WATCH1_ADDR_HI_BASE_IDX 0 4468f33ac92fSHawking Zhang #define regCP_DMA_WATCH1_MASK 0x1ec6 4469f33ac92fSHawking Zhang #define regCP_DMA_WATCH1_MASK_BASE_IDX 0 4470f33ac92fSHawking Zhang #define regCP_DMA_WATCH1_CNTL 0x1ec7 4471f33ac92fSHawking Zhang #define regCP_DMA_WATCH1_CNTL_BASE_IDX 0 4472f33ac92fSHawking Zhang #define regCP_DMA_WATCH2_ADDR_LO 0x1ec8 4473f33ac92fSHawking Zhang #define regCP_DMA_WATCH2_ADDR_LO_BASE_IDX 0 4474f33ac92fSHawking Zhang #define regCP_DMA_WATCH2_ADDR_HI 0x1ec9 4475f33ac92fSHawking Zhang #define regCP_DMA_WATCH2_ADDR_HI_BASE_IDX 0 4476f33ac92fSHawking Zhang #define regCP_DMA_WATCH2_MASK 0x1eca 4477f33ac92fSHawking Zhang #define regCP_DMA_WATCH2_MASK_BASE_IDX 0 4478f33ac92fSHawking Zhang #define regCP_DMA_WATCH2_CNTL 0x1ecb 4479f33ac92fSHawking Zhang #define regCP_DMA_WATCH2_CNTL_BASE_IDX 0 4480f33ac92fSHawking Zhang #define regCP_DMA_WATCH3_ADDR_LO 0x1ecc 4481f33ac92fSHawking Zhang #define regCP_DMA_WATCH3_ADDR_LO_BASE_IDX 0 4482f33ac92fSHawking Zhang #define regCP_DMA_WATCH3_ADDR_HI 0x1ecd 4483f33ac92fSHawking Zhang #define regCP_DMA_WATCH3_ADDR_HI_BASE_IDX 0 4484f33ac92fSHawking Zhang #define regCP_DMA_WATCH3_MASK 0x1ece 4485f33ac92fSHawking Zhang #define regCP_DMA_WATCH3_MASK_BASE_IDX 0 4486f33ac92fSHawking Zhang #define regCP_DMA_WATCH3_CNTL 0x1ecf 4487f33ac92fSHawking Zhang #define regCP_DMA_WATCH3_CNTL_BASE_IDX 0 4488f33ac92fSHawking Zhang #define regCP_DMA_WATCH_STAT_ADDR_LO 0x1ed0 4489f33ac92fSHawking Zhang #define regCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX 0 4490f33ac92fSHawking Zhang #define regCP_DMA_WATCH_STAT_ADDR_HI 0x1ed1 4491f33ac92fSHawking Zhang #define regCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX 0 4492f33ac92fSHawking Zhang #define regCP_DMA_WATCH_STAT 0x1ed2 4493f33ac92fSHawking Zhang #define regCP_DMA_WATCH_STAT_BASE_IDX 0 4494f33ac92fSHawking Zhang #define regCP_PFP_JT_STAT 0x1ed3 4495f33ac92fSHawking Zhang #define regCP_PFP_JT_STAT_BASE_IDX 0 4496f33ac92fSHawking Zhang #define regCP_MEC_JT_STAT 0x1ed5 4497f33ac92fSHawking Zhang #define regCP_MEC_JT_STAT_BASE_IDX 0 4498f33ac92fSHawking Zhang #define regCP_CPC_BUSY_HYSTERESIS 0x1edb 4499f33ac92fSHawking Zhang #define regCP_CPC_BUSY_HYSTERESIS_BASE_IDX 0 4500f33ac92fSHawking Zhang #define regCP_CPF_BUSY_HYSTERESIS1 0x1edc 4501f33ac92fSHawking Zhang #define regCP_CPF_BUSY_HYSTERESIS1_BASE_IDX 0 4502f33ac92fSHawking Zhang #define regCP_CPF_BUSY_HYSTERESIS2 0x1edd 4503f33ac92fSHawking Zhang #define regCP_CPF_BUSY_HYSTERESIS2_BASE_IDX 0 4504f33ac92fSHawking Zhang #define regCP_CPG_BUSY_HYSTERESIS1 0x1ede 4505f33ac92fSHawking Zhang #define regCP_CPG_BUSY_HYSTERESIS1_BASE_IDX 0 4506f33ac92fSHawking Zhang #define regCP_CPG_BUSY_HYSTERESIS2 0x1edf 4507f33ac92fSHawking Zhang #define regCP_CPG_BUSY_HYSTERESIS2_BASE_IDX 0 4508f33ac92fSHawking Zhang #define regCP_RB_DOORBELL_CLEAR 0x1f28 4509f33ac92fSHawking Zhang #define regCP_RB_DOORBELL_CLEAR_BASE_IDX 0 4510f33ac92fSHawking Zhang #define regCP_RB0_ACTIVE 0x1f40 4511f33ac92fSHawking Zhang #define regCP_RB0_ACTIVE_BASE_IDX 0 4512f33ac92fSHawking Zhang #define regCP_RB_ACTIVE 0x1f40 4513f33ac92fSHawking Zhang #define regCP_RB_ACTIVE_BASE_IDX 0 4514f33ac92fSHawking Zhang #define regCP_RB1_ACTIVE 0x1f41 4515f33ac92fSHawking Zhang #define regCP_RB1_ACTIVE_BASE_IDX 0 4516f33ac92fSHawking Zhang #define regCP_RB_STATUS 0x1f43 4517f33ac92fSHawking Zhang #define regCP_RB_STATUS_BASE_IDX 0 4518f33ac92fSHawking Zhang #define regCPG_RCIU_CAM_INDEX 0x1f44 4519f33ac92fSHawking Zhang #define regCPG_RCIU_CAM_INDEX_BASE_IDX 0 4520f33ac92fSHawking Zhang #define regCPG_RCIU_CAM_DATA 0x1f45 4521f33ac92fSHawking Zhang #define regCPG_RCIU_CAM_DATA_BASE_IDX 0 4522f33ac92fSHawking Zhang #define regCPG_RCIU_CAM_DATA_PHASE0 0x1f45 4523f33ac92fSHawking Zhang #define regCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX 0 4524f33ac92fSHawking Zhang #define regCPG_RCIU_CAM_DATA_PHASE1 0x1f45 4525f33ac92fSHawking Zhang #define regCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX 0 4526f33ac92fSHawking Zhang #define regCPG_RCIU_CAM_DATA_PHASE2 0x1f45 4527f33ac92fSHawking Zhang #define regCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX 0 4528f33ac92fSHawking Zhang #define regCP_GPU_TIMESTAMP_OFFSET_LO 0x1f4c 4529f33ac92fSHawking Zhang #define regCP_GPU_TIMESTAMP_OFFSET_LO_BASE_IDX 0 4530f33ac92fSHawking Zhang #define regCP_GPU_TIMESTAMP_OFFSET_HI 0x1f4d 4531f33ac92fSHawking Zhang #define regCP_GPU_TIMESTAMP_OFFSET_HI_BASE_IDX 0 4532f33ac92fSHawking Zhang #define regCP_SDMA_DMA_DONE 0x1f4e 4533f33ac92fSHawking Zhang #define regCP_SDMA_DMA_DONE_BASE_IDX 0 4534f33ac92fSHawking Zhang #define regCP_PFP_SDMA_CS 0x1f4f 4535f33ac92fSHawking Zhang #define regCP_PFP_SDMA_CS_BASE_IDX 0 4536f33ac92fSHawking Zhang #define regCP_ME_SDMA_CS 0x1f50 4537f33ac92fSHawking Zhang #define regCP_ME_SDMA_CS_BASE_IDX 0 4538f33ac92fSHawking Zhang #define regCPF_GCR_CNTL 0x1f53 4539f33ac92fSHawking Zhang #define regCPF_GCR_CNTL_BASE_IDX 0 4540f33ac92fSHawking Zhang #define regCPG_UTCL1_STATUS 0x1f54 4541f33ac92fSHawking Zhang #define regCPG_UTCL1_STATUS_BASE_IDX 0 4542f33ac92fSHawking Zhang #define regCPC_UTCL1_STATUS 0x1f55 4543f33ac92fSHawking Zhang #define regCPC_UTCL1_STATUS_BASE_IDX 0 4544f33ac92fSHawking Zhang #define regCPF_UTCL1_STATUS 0x1f56 4545f33ac92fSHawking Zhang #define regCPF_UTCL1_STATUS_BASE_IDX 0 4546f33ac92fSHawking Zhang #define regCP_SD_CNTL 0x1f57 4547f33ac92fSHawking Zhang #define regCP_SD_CNTL_BASE_IDX 0 4548f33ac92fSHawking Zhang #define regCP_SOFT_RESET_CNTL 0x1f59 4549f33ac92fSHawking Zhang #define regCP_SOFT_RESET_CNTL_BASE_IDX 0 4550f33ac92fSHawking Zhang #define regCP_CPC_GFX_CNTL 0x1f5a 4551f33ac92fSHawking Zhang #define regCP_CPC_GFX_CNTL_BASE_IDX 0 4552f33ac92fSHawking Zhang 4553f33ac92fSHawking Zhang 4554f33ac92fSHawking Zhang // addressBlock: gc_spipdec 4555f33ac92fSHawking Zhang // base address: 0xc700 4556f33ac92fSHawking Zhang #define regSPI_ARB_PRIORITY 0x1f60 4557f33ac92fSHawking Zhang #define regSPI_ARB_PRIORITY_BASE_IDX 0 4558f33ac92fSHawking Zhang #define regSPI_ARB_CYCLES_0 0x1f61 4559f33ac92fSHawking Zhang #define regSPI_ARB_CYCLES_0_BASE_IDX 0 4560f33ac92fSHawking Zhang #define regSPI_ARB_CYCLES_1 0x1f62 4561f33ac92fSHawking Zhang #define regSPI_ARB_CYCLES_1_BASE_IDX 0 4562f33ac92fSHawking Zhang #define regSPI_WCL_PIPE_PERCENT_GFX 0x1f67 4563f33ac92fSHawking Zhang #define regSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX 0 4564f33ac92fSHawking Zhang #define regSPI_WCL_PIPE_PERCENT_HP3D 0x1f68 4565f33ac92fSHawking Zhang #define regSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX 0 4566f33ac92fSHawking Zhang #define regSPI_WCL_PIPE_PERCENT_CS0 0x1f69 4567f33ac92fSHawking Zhang #define regSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX 0 4568f33ac92fSHawking Zhang #define regSPI_WCL_PIPE_PERCENT_CS1 0x1f6a 4569f33ac92fSHawking Zhang #define regSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX 0 4570f33ac92fSHawking Zhang #define regSPI_WCL_PIPE_PERCENT_CS2 0x1f6b 4571f33ac92fSHawking Zhang #define regSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX 0 4572f33ac92fSHawking Zhang #define regSPI_WCL_PIPE_PERCENT_CS3 0x1f6c 4573f33ac92fSHawking Zhang #define regSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX 0 4574f33ac92fSHawking Zhang #define regSPI_WCL_PIPE_PERCENT_CS4 0x1f6d 4575f33ac92fSHawking Zhang #define regSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX 0 4576f33ac92fSHawking Zhang #define regSPI_WCL_PIPE_PERCENT_CS5 0x1f6e 4577f33ac92fSHawking Zhang #define regSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX 0 4578f33ac92fSHawking Zhang #define regSPI_WCL_PIPE_PERCENT_CS6 0x1f6f 4579f33ac92fSHawking Zhang #define regSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX 0 4580f33ac92fSHawking Zhang #define regSPI_WCL_PIPE_PERCENT_CS7 0x1f70 4581f33ac92fSHawking Zhang #define regSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX 0 4582f33ac92fSHawking Zhang #define regSPI_USER_ACCUM_VMID_CNTL 0x1f71 4583f33ac92fSHawking Zhang #define regSPI_USER_ACCUM_VMID_CNTL_BASE_IDX 0 4584f33ac92fSHawking Zhang #define regSPI_GDBG_PER_VMID_CNTL 0x1f72 4585f33ac92fSHawking Zhang #define regSPI_GDBG_PER_VMID_CNTL_BASE_IDX 0 4586f33ac92fSHawking Zhang #define regSPI_COMPUTE_QUEUE_RESET 0x1f73 4587f33ac92fSHawking Zhang #define regSPI_COMPUTE_QUEUE_RESET_BASE_IDX 0 4588f33ac92fSHawking Zhang #define regSPI_COMPUTE_WF_CTX_SAVE 0x1f74 4589f33ac92fSHawking Zhang #define regSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX 0 4590f33ac92fSHawking Zhang 4591f33ac92fSHawking Zhang 4592f33ac92fSHawking Zhang // addressBlock: gc_cpphqddec 4593f33ac92fSHawking Zhang // base address: 0xc800 4594f33ac92fSHawking Zhang #define regCP_HPD_UTCL1_CNTL 0x1fa3 4595f33ac92fSHawking Zhang #define regCP_HPD_UTCL1_CNTL_BASE_IDX 0 4596f33ac92fSHawking Zhang #define regCP_HPD_UTCL1_ERROR 0x1fa7 4597f33ac92fSHawking Zhang #define regCP_HPD_UTCL1_ERROR_BASE_IDX 0 4598f33ac92fSHawking Zhang #define regCP_HPD_UTCL1_ERROR_ADDR 0x1fa8 4599f33ac92fSHawking Zhang #define regCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX 0 4600f33ac92fSHawking Zhang #define regCP_MQD_BASE_ADDR 0x1fa9 4601f33ac92fSHawking Zhang #define regCP_MQD_BASE_ADDR_BASE_IDX 0 4602f33ac92fSHawking Zhang #define regCP_MQD_BASE_ADDR_HI 0x1faa 4603f33ac92fSHawking Zhang #define regCP_MQD_BASE_ADDR_HI_BASE_IDX 0 4604f33ac92fSHawking Zhang #define regCP_HQD_ACTIVE 0x1fab 4605f33ac92fSHawking Zhang #define regCP_HQD_ACTIVE_BASE_IDX 0 4606f33ac92fSHawking Zhang #define regCP_HQD_VMID 0x1fac 4607f33ac92fSHawking Zhang #define regCP_HQD_VMID_BASE_IDX 0 4608f33ac92fSHawking Zhang #define regCP_HQD_PERSISTENT_STATE 0x1fad 4609f33ac92fSHawking Zhang #define regCP_HQD_PERSISTENT_STATE_BASE_IDX 0 4610f33ac92fSHawking Zhang #define regCP_HQD_PIPE_PRIORITY 0x1fae 4611f33ac92fSHawking Zhang #define regCP_HQD_PIPE_PRIORITY_BASE_IDX 0 4612f33ac92fSHawking Zhang #define regCP_HQD_QUEUE_PRIORITY 0x1faf 4613f33ac92fSHawking Zhang #define regCP_HQD_QUEUE_PRIORITY_BASE_IDX 0 4614f33ac92fSHawking Zhang #define regCP_HQD_QUANTUM 0x1fb0 4615f33ac92fSHawking Zhang #define regCP_HQD_QUANTUM_BASE_IDX 0 4616f33ac92fSHawking Zhang #define regCP_HQD_PQ_BASE 0x1fb1 4617f33ac92fSHawking Zhang #define regCP_HQD_PQ_BASE_BASE_IDX 0 4618f33ac92fSHawking Zhang #define regCP_HQD_PQ_BASE_HI 0x1fb2 4619f33ac92fSHawking Zhang #define regCP_HQD_PQ_BASE_HI_BASE_IDX 0 4620f33ac92fSHawking Zhang #define regCP_HQD_PQ_RPTR 0x1fb3 4621f33ac92fSHawking Zhang #define regCP_HQD_PQ_RPTR_BASE_IDX 0 4622f33ac92fSHawking Zhang #define regCP_HQD_PQ_RPTR_REPORT_ADDR 0x1fb4 4623f33ac92fSHawking Zhang #define regCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX 0 4624f33ac92fSHawking Zhang #define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1fb5 4625f33ac92fSHawking Zhang #define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX 0 4626f33ac92fSHawking Zhang #define regCP_HQD_PQ_WPTR_POLL_ADDR 0x1fb6 4627f33ac92fSHawking Zhang #define regCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX 0 4628f33ac92fSHawking Zhang #define regCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x1fb7 4629f33ac92fSHawking Zhang #define regCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX 0 4630f33ac92fSHawking Zhang #define regCP_HQD_PQ_DOORBELL_CONTROL 0x1fb8 4631f33ac92fSHawking Zhang #define regCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX 0 4632f33ac92fSHawking Zhang #define regCP_HQD_PQ_CONTROL 0x1fba 4633f33ac92fSHawking Zhang #define regCP_HQD_PQ_CONTROL_BASE_IDX 0 4634f33ac92fSHawking Zhang #define regCP_HQD_IB_BASE_ADDR 0x1fbb 4635f33ac92fSHawking Zhang #define regCP_HQD_IB_BASE_ADDR_BASE_IDX 0 4636f33ac92fSHawking Zhang #define regCP_HQD_IB_BASE_ADDR_HI 0x1fbc 4637f33ac92fSHawking Zhang #define regCP_HQD_IB_BASE_ADDR_HI_BASE_IDX 0 4638f33ac92fSHawking Zhang #define regCP_HQD_IB_RPTR 0x1fbd 4639f33ac92fSHawking Zhang #define regCP_HQD_IB_RPTR_BASE_IDX 0 4640f33ac92fSHawking Zhang #define regCP_HQD_IB_CONTROL 0x1fbe 4641f33ac92fSHawking Zhang #define regCP_HQD_IB_CONTROL_BASE_IDX 0 4642f33ac92fSHawking Zhang #define regCP_HQD_IQ_TIMER 0x1fbf 4643f33ac92fSHawking Zhang #define regCP_HQD_IQ_TIMER_BASE_IDX 0 4644f33ac92fSHawking Zhang #define regCP_HQD_IQ_RPTR 0x1fc0 4645f33ac92fSHawking Zhang #define regCP_HQD_IQ_RPTR_BASE_IDX 0 4646f33ac92fSHawking Zhang #define regCP_HQD_DEQUEUE_REQUEST 0x1fc1 4647f33ac92fSHawking Zhang #define regCP_HQD_DEQUEUE_REQUEST_BASE_IDX 0 4648f33ac92fSHawking Zhang #define regCP_HQD_DMA_OFFLOAD 0x1fc2 4649f33ac92fSHawking Zhang #define regCP_HQD_DMA_OFFLOAD_BASE_IDX 0 4650f33ac92fSHawking Zhang #define regCP_HQD_OFFLOAD 0x1fc2 4651f33ac92fSHawking Zhang #define regCP_HQD_OFFLOAD_BASE_IDX 0 4652f33ac92fSHawking Zhang #define regCP_HQD_SEMA_CMD 0x1fc3 4653f33ac92fSHawking Zhang #define regCP_HQD_SEMA_CMD_BASE_IDX 0 4654f33ac92fSHawking Zhang #define regCP_HQD_MSG_TYPE 0x1fc4 4655f33ac92fSHawking Zhang #define regCP_HQD_MSG_TYPE_BASE_IDX 0 4656f33ac92fSHawking Zhang #define regCP_HQD_ATOMIC0_PREOP_LO 0x1fc5 4657f33ac92fSHawking Zhang #define regCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX 0 4658f33ac92fSHawking Zhang #define regCP_HQD_ATOMIC0_PREOP_HI 0x1fc6 4659f33ac92fSHawking Zhang #define regCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX 0 4660f33ac92fSHawking Zhang #define regCP_HQD_ATOMIC1_PREOP_LO 0x1fc7 4661f33ac92fSHawking Zhang #define regCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX 0 4662f33ac92fSHawking Zhang #define regCP_HQD_ATOMIC1_PREOP_HI 0x1fc8 4663f33ac92fSHawking Zhang #define regCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX 0 4664f33ac92fSHawking Zhang #define regCP_HQD_HQ_SCHEDULER0 0x1fc9 4665f33ac92fSHawking Zhang #define regCP_HQD_HQ_SCHEDULER0_BASE_IDX 0 4666f33ac92fSHawking Zhang #define regCP_HQD_HQ_STATUS0 0x1fc9 4667f33ac92fSHawking Zhang #define regCP_HQD_HQ_STATUS0_BASE_IDX 0 4668f33ac92fSHawking Zhang #define regCP_HQD_HQ_CONTROL0 0x1fca 4669f33ac92fSHawking Zhang #define regCP_HQD_HQ_CONTROL0_BASE_IDX 0 4670f33ac92fSHawking Zhang #define regCP_HQD_HQ_SCHEDULER1 0x1fca 4671f33ac92fSHawking Zhang #define regCP_HQD_HQ_SCHEDULER1_BASE_IDX 0 4672f33ac92fSHawking Zhang #define regCP_MQD_CONTROL 0x1fcb 4673f33ac92fSHawking Zhang #define regCP_MQD_CONTROL_BASE_IDX 0 4674f33ac92fSHawking Zhang #define regCP_HQD_HQ_STATUS1 0x1fcc 4675f33ac92fSHawking Zhang #define regCP_HQD_HQ_STATUS1_BASE_IDX 0 4676f33ac92fSHawking Zhang #define regCP_HQD_HQ_CONTROL1 0x1fcd 4677f33ac92fSHawking Zhang #define regCP_HQD_HQ_CONTROL1_BASE_IDX 0 4678f33ac92fSHawking Zhang #define regCP_HQD_EOP_BASE_ADDR 0x1fce 4679f33ac92fSHawking Zhang #define regCP_HQD_EOP_BASE_ADDR_BASE_IDX 0 4680f33ac92fSHawking Zhang #define regCP_HQD_EOP_BASE_ADDR_HI 0x1fcf 4681f33ac92fSHawking Zhang #define regCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX 0 4682f33ac92fSHawking Zhang #define regCP_HQD_EOP_CONTROL 0x1fd0 4683f33ac92fSHawking Zhang #define regCP_HQD_EOP_CONTROL_BASE_IDX 0 4684f33ac92fSHawking Zhang #define regCP_HQD_EOP_RPTR 0x1fd1 4685f33ac92fSHawking Zhang #define regCP_HQD_EOP_RPTR_BASE_IDX 0 4686f33ac92fSHawking Zhang #define regCP_HQD_EOP_WPTR 0x1fd2 4687f33ac92fSHawking Zhang #define regCP_HQD_EOP_WPTR_BASE_IDX 0 4688f33ac92fSHawking Zhang #define regCP_HQD_EOP_EVENTS 0x1fd3 4689f33ac92fSHawking Zhang #define regCP_HQD_EOP_EVENTS_BASE_IDX 0 4690f33ac92fSHawking Zhang #define regCP_HQD_CTX_SAVE_BASE_ADDR_LO 0x1fd4 4691f33ac92fSHawking Zhang #define regCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0 4692f33ac92fSHawking Zhang #define regCP_HQD_CTX_SAVE_BASE_ADDR_HI 0x1fd5 4693f33ac92fSHawking Zhang #define regCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0 4694f33ac92fSHawking Zhang #define regCP_HQD_CTX_SAVE_CONTROL 0x1fd6 4695f33ac92fSHawking Zhang #define regCP_HQD_CTX_SAVE_CONTROL_BASE_IDX 0 4696f33ac92fSHawking Zhang #define regCP_HQD_CNTL_STACK_OFFSET 0x1fd7 4697f33ac92fSHawking Zhang #define regCP_HQD_CNTL_STACK_OFFSET_BASE_IDX 0 4698f33ac92fSHawking Zhang #define regCP_HQD_CNTL_STACK_SIZE 0x1fd8 4699f33ac92fSHawking Zhang #define regCP_HQD_CNTL_STACK_SIZE_BASE_IDX 0 4700f33ac92fSHawking Zhang #define regCP_HQD_WG_STATE_OFFSET 0x1fd9 4701f33ac92fSHawking Zhang #define regCP_HQD_WG_STATE_OFFSET_BASE_IDX 0 4702f33ac92fSHawking Zhang #define regCP_HQD_CTX_SAVE_SIZE 0x1fda 4703f33ac92fSHawking Zhang #define regCP_HQD_CTX_SAVE_SIZE_BASE_IDX 0 4704f33ac92fSHawking Zhang #define regCP_HQD_GDS_RESOURCE_STATE 0x1fdb 4705f33ac92fSHawking Zhang #define regCP_HQD_GDS_RESOURCE_STATE_BASE_IDX 0 4706f33ac92fSHawking Zhang #define regCP_HQD_ERROR 0x1fdc 4707f33ac92fSHawking Zhang #define regCP_HQD_ERROR_BASE_IDX 0 4708f33ac92fSHawking Zhang #define regCP_HQD_EOP_WPTR_MEM 0x1fdd 4709f33ac92fSHawking Zhang #define regCP_HQD_EOP_WPTR_MEM_BASE_IDX 0 4710f33ac92fSHawking Zhang #define regCP_HQD_AQL_CONTROL 0x1fde 4711f33ac92fSHawking Zhang #define regCP_HQD_AQL_CONTROL_BASE_IDX 0 4712f33ac92fSHawking Zhang #define regCP_HQD_PQ_WPTR_LO 0x1fdf 4713f33ac92fSHawking Zhang #define regCP_HQD_PQ_WPTR_LO_BASE_IDX 0 4714f33ac92fSHawking Zhang #define regCP_HQD_PQ_WPTR_HI 0x1fe0 4715f33ac92fSHawking Zhang #define regCP_HQD_PQ_WPTR_HI_BASE_IDX 0 4716f33ac92fSHawking Zhang #define regCP_HQD_SUSPEND_CNTL_STACK_OFFSET 0x1fe1 4717f33ac92fSHawking Zhang #define regCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX 0 4718f33ac92fSHawking Zhang #define regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT 0x1fe2 4719f33ac92fSHawking Zhang #define regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX 0 4720f33ac92fSHawking Zhang #define regCP_HQD_SUSPEND_WG_STATE_OFFSET 0x1fe3 4721f33ac92fSHawking Zhang #define regCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX 0 4722f33ac92fSHawking Zhang #define regCP_HQD_DDID_RPTR 0x1fe4 4723f33ac92fSHawking Zhang #define regCP_HQD_DDID_RPTR_BASE_IDX 0 4724f33ac92fSHawking Zhang #define regCP_HQD_DDID_WPTR 0x1fe5 4725f33ac92fSHawking Zhang #define regCP_HQD_DDID_WPTR_BASE_IDX 0 4726f33ac92fSHawking Zhang #define regCP_HQD_DDID_INFLIGHT_COUNT 0x1fe6 4727f33ac92fSHawking Zhang #define regCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX 0 4728f33ac92fSHawking Zhang #define regCP_HQD_DDID_DELTA_RPT_COUNT 0x1fe7 4729f33ac92fSHawking Zhang #define regCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX 0 4730f33ac92fSHawking Zhang #define regCP_HQD_DEQUEUE_STATUS 0x1fe8 4731f33ac92fSHawking Zhang #define regCP_HQD_DEQUEUE_STATUS_BASE_IDX 0 4732f33ac92fSHawking Zhang 4733f33ac92fSHawking Zhang 4734f33ac92fSHawking Zhang // addressBlock: gc_tcpdec 4735f33ac92fSHawking Zhang // base address: 0xca80 4736f33ac92fSHawking Zhang #define regTCP_WATCH0_ADDR_H 0x2048 4737f33ac92fSHawking Zhang #define regTCP_WATCH0_ADDR_H_BASE_IDX 0 4738f33ac92fSHawking Zhang #define regTCP_WATCH0_ADDR_L 0x2049 4739f33ac92fSHawking Zhang #define regTCP_WATCH0_ADDR_L_BASE_IDX 0 4740f33ac92fSHawking Zhang #define regTCP_WATCH0_CNTL 0x204a 4741f33ac92fSHawking Zhang #define regTCP_WATCH0_CNTL_BASE_IDX 0 4742f33ac92fSHawking Zhang #define regTCP_WATCH1_ADDR_H 0x204b 4743f33ac92fSHawking Zhang #define regTCP_WATCH1_ADDR_H_BASE_IDX 0 4744f33ac92fSHawking Zhang #define regTCP_WATCH1_ADDR_L 0x204c 4745f33ac92fSHawking Zhang #define regTCP_WATCH1_ADDR_L_BASE_IDX 0 4746f33ac92fSHawking Zhang #define regTCP_WATCH1_CNTL 0x204d 4747f33ac92fSHawking Zhang #define regTCP_WATCH1_CNTL_BASE_IDX 0 4748f33ac92fSHawking Zhang #define regTCP_WATCH2_ADDR_H 0x204e 4749f33ac92fSHawking Zhang #define regTCP_WATCH2_ADDR_H_BASE_IDX 0 4750f33ac92fSHawking Zhang #define regTCP_WATCH2_ADDR_L 0x204f 4751f33ac92fSHawking Zhang #define regTCP_WATCH2_ADDR_L_BASE_IDX 0 4752f33ac92fSHawking Zhang #define regTCP_WATCH2_CNTL 0x2050 4753f33ac92fSHawking Zhang #define regTCP_WATCH2_CNTL_BASE_IDX 0 4754f33ac92fSHawking Zhang #define regTCP_WATCH3_ADDR_H 0x2051 4755f33ac92fSHawking Zhang #define regTCP_WATCH3_ADDR_H_BASE_IDX 0 4756f33ac92fSHawking Zhang #define regTCP_WATCH3_ADDR_L 0x2052 4757f33ac92fSHawking Zhang #define regTCP_WATCH3_ADDR_L_BASE_IDX 0 4758f33ac92fSHawking Zhang #define regTCP_WATCH3_CNTL 0x2053 4759f33ac92fSHawking Zhang #define regTCP_WATCH3_CNTL_BASE_IDX 0 4760f33ac92fSHawking Zhang 4761f33ac92fSHawking Zhang 4762f33ac92fSHawking Zhang // addressBlock: gc_gdspdec 4763f33ac92fSHawking Zhang // base address: 0xcc00 4764f33ac92fSHawking Zhang #define regGDS_VMID0_BASE 0x20a0 4765f33ac92fSHawking Zhang #define regGDS_VMID0_BASE_BASE_IDX 0 4766f33ac92fSHawking Zhang #define regGDS_VMID0_SIZE 0x20a1 4767f33ac92fSHawking Zhang #define regGDS_VMID0_SIZE_BASE_IDX 0 4768f33ac92fSHawking Zhang #define regGDS_VMID1_BASE 0x20a2 4769f33ac92fSHawking Zhang #define regGDS_VMID1_BASE_BASE_IDX 0 4770f33ac92fSHawking Zhang #define regGDS_VMID1_SIZE 0x20a3 4771f33ac92fSHawking Zhang #define regGDS_VMID1_SIZE_BASE_IDX 0 4772f33ac92fSHawking Zhang #define regGDS_VMID2_BASE 0x20a4 4773f33ac92fSHawking Zhang #define regGDS_VMID2_BASE_BASE_IDX 0 4774f33ac92fSHawking Zhang #define regGDS_VMID2_SIZE 0x20a5 4775f33ac92fSHawking Zhang #define regGDS_VMID2_SIZE_BASE_IDX 0 4776f33ac92fSHawking Zhang #define regGDS_VMID3_BASE 0x20a6 4777f33ac92fSHawking Zhang #define regGDS_VMID3_BASE_BASE_IDX 0 4778f33ac92fSHawking Zhang #define regGDS_VMID3_SIZE 0x20a7 4779f33ac92fSHawking Zhang #define regGDS_VMID3_SIZE_BASE_IDX 0 4780f33ac92fSHawking Zhang #define regGDS_VMID4_BASE 0x20a8 4781f33ac92fSHawking Zhang #define regGDS_VMID4_BASE_BASE_IDX 0 4782f33ac92fSHawking Zhang #define regGDS_VMID4_SIZE 0x20a9 4783f33ac92fSHawking Zhang #define regGDS_VMID4_SIZE_BASE_IDX 0 4784f33ac92fSHawking Zhang #define regGDS_VMID5_BASE 0x20aa 4785f33ac92fSHawking Zhang #define regGDS_VMID5_BASE_BASE_IDX 0 4786f33ac92fSHawking Zhang #define regGDS_VMID5_SIZE 0x20ab 4787f33ac92fSHawking Zhang #define regGDS_VMID5_SIZE_BASE_IDX 0 4788f33ac92fSHawking Zhang #define regGDS_VMID6_BASE 0x20ac 4789f33ac92fSHawking Zhang #define regGDS_VMID6_BASE_BASE_IDX 0 4790f33ac92fSHawking Zhang #define regGDS_VMID6_SIZE 0x20ad 4791f33ac92fSHawking Zhang #define regGDS_VMID6_SIZE_BASE_IDX 0 4792f33ac92fSHawking Zhang #define regGDS_VMID7_BASE 0x20ae 4793f33ac92fSHawking Zhang #define regGDS_VMID7_BASE_BASE_IDX 0 4794f33ac92fSHawking Zhang #define regGDS_VMID7_SIZE 0x20af 4795f33ac92fSHawking Zhang #define regGDS_VMID7_SIZE_BASE_IDX 0 4796f33ac92fSHawking Zhang #define regGDS_VMID8_BASE 0x20b0 4797f33ac92fSHawking Zhang #define regGDS_VMID8_BASE_BASE_IDX 0 4798f33ac92fSHawking Zhang #define regGDS_VMID8_SIZE 0x20b1 4799f33ac92fSHawking Zhang #define regGDS_VMID8_SIZE_BASE_IDX 0 4800f33ac92fSHawking Zhang #define regGDS_VMID9_BASE 0x20b2 4801f33ac92fSHawking Zhang #define regGDS_VMID9_BASE_BASE_IDX 0 4802f33ac92fSHawking Zhang #define regGDS_VMID9_SIZE 0x20b3 4803f33ac92fSHawking Zhang #define regGDS_VMID9_SIZE_BASE_IDX 0 4804f33ac92fSHawking Zhang #define regGDS_VMID10_BASE 0x20b4 4805f33ac92fSHawking Zhang #define regGDS_VMID10_BASE_BASE_IDX 0 4806f33ac92fSHawking Zhang #define regGDS_VMID10_SIZE 0x20b5 4807f33ac92fSHawking Zhang #define regGDS_VMID10_SIZE_BASE_IDX 0 4808f33ac92fSHawking Zhang #define regGDS_VMID11_BASE 0x20b6 4809f33ac92fSHawking Zhang #define regGDS_VMID11_BASE_BASE_IDX 0 4810f33ac92fSHawking Zhang #define regGDS_VMID11_SIZE 0x20b7 4811f33ac92fSHawking Zhang #define regGDS_VMID11_SIZE_BASE_IDX 0 4812f33ac92fSHawking Zhang #define regGDS_VMID12_BASE 0x20b8 4813f33ac92fSHawking Zhang #define regGDS_VMID12_BASE_BASE_IDX 0 4814f33ac92fSHawking Zhang #define regGDS_VMID12_SIZE 0x20b9 4815f33ac92fSHawking Zhang #define regGDS_VMID12_SIZE_BASE_IDX 0 4816f33ac92fSHawking Zhang #define regGDS_VMID13_BASE 0x20ba 4817f33ac92fSHawking Zhang #define regGDS_VMID13_BASE_BASE_IDX 0 4818f33ac92fSHawking Zhang #define regGDS_VMID13_SIZE 0x20bb 4819f33ac92fSHawking Zhang #define regGDS_VMID13_SIZE_BASE_IDX 0 4820f33ac92fSHawking Zhang #define regGDS_VMID14_BASE 0x20bc 4821f33ac92fSHawking Zhang #define regGDS_VMID14_BASE_BASE_IDX 0 4822f33ac92fSHawking Zhang #define regGDS_VMID14_SIZE 0x20bd 4823f33ac92fSHawking Zhang #define regGDS_VMID14_SIZE_BASE_IDX 0 4824f33ac92fSHawking Zhang #define regGDS_VMID15_BASE 0x20be 4825f33ac92fSHawking Zhang #define regGDS_VMID15_BASE_BASE_IDX 0 4826f33ac92fSHawking Zhang #define regGDS_VMID15_SIZE 0x20bf 4827f33ac92fSHawking Zhang #define regGDS_VMID15_SIZE_BASE_IDX 0 4828f33ac92fSHawking Zhang #define regGDS_GWS_VMID0 0x20c0 4829f33ac92fSHawking Zhang #define regGDS_GWS_VMID0_BASE_IDX 0 4830f33ac92fSHawking Zhang #define regGDS_GWS_VMID1 0x20c1 4831f33ac92fSHawking Zhang #define regGDS_GWS_VMID1_BASE_IDX 0 4832f33ac92fSHawking Zhang #define regGDS_GWS_VMID2 0x20c2 4833f33ac92fSHawking Zhang #define regGDS_GWS_VMID2_BASE_IDX 0 4834f33ac92fSHawking Zhang #define regGDS_GWS_VMID3 0x20c3 4835f33ac92fSHawking Zhang #define regGDS_GWS_VMID3_BASE_IDX 0 4836f33ac92fSHawking Zhang #define regGDS_GWS_VMID4 0x20c4 4837f33ac92fSHawking Zhang #define regGDS_GWS_VMID4_BASE_IDX 0 4838f33ac92fSHawking Zhang #define regGDS_GWS_VMID5 0x20c5 4839f33ac92fSHawking Zhang #define regGDS_GWS_VMID5_BASE_IDX 0 4840f33ac92fSHawking Zhang #define regGDS_GWS_VMID6 0x20c6 4841f33ac92fSHawking Zhang #define regGDS_GWS_VMID6_BASE_IDX 0 4842f33ac92fSHawking Zhang #define regGDS_GWS_VMID7 0x20c7 4843f33ac92fSHawking Zhang #define regGDS_GWS_VMID7_BASE_IDX 0 4844f33ac92fSHawking Zhang #define regGDS_GWS_VMID8 0x20c8 4845f33ac92fSHawking Zhang #define regGDS_GWS_VMID8_BASE_IDX 0 4846f33ac92fSHawking Zhang #define regGDS_GWS_VMID9 0x20c9 4847f33ac92fSHawking Zhang #define regGDS_GWS_VMID9_BASE_IDX 0 4848f33ac92fSHawking Zhang #define regGDS_GWS_VMID10 0x20ca 4849f33ac92fSHawking Zhang #define regGDS_GWS_VMID10_BASE_IDX 0 4850f33ac92fSHawking Zhang #define regGDS_GWS_VMID11 0x20cb 4851f33ac92fSHawking Zhang #define regGDS_GWS_VMID11_BASE_IDX 0 4852f33ac92fSHawking Zhang #define regGDS_GWS_VMID12 0x20cc 4853f33ac92fSHawking Zhang #define regGDS_GWS_VMID12_BASE_IDX 0 4854f33ac92fSHawking Zhang #define regGDS_GWS_VMID13 0x20cd 4855f33ac92fSHawking Zhang #define regGDS_GWS_VMID13_BASE_IDX 0 4856f33ac92fSHawking Zhang #define regGDS_GWS_VMID14 0x20ce 4857f33ac92fSHawking Zhang #define regGDS_GWS_VMID14_BASE_IDX 0 4858f33ac92fSHawking Zhang #define regGDS_GWS_VMID15 0x20cf 4859f33ac92fSHawking Zhang #define regGDS_GWS_VMID15_BASE_IDX 0 4860f33ac92fSHawking Zhang #define regGDS_OA_VMID0 0x20d0 4861f33ac92fSHawking Zhang #define regGDS_OA_VMID0_BASE_IDX 0 4862f33ac92fSHawking Zhang #define regGDS_OA_VMID1 0x20d1 4863f33ac92fSHawking Zhang #define regGDS_OA_VMID1_BASE_IDX 0 4864f33ac92fSHawking Zhang #define regGDS_OA_VMID2 0x20d2 4865f33ac92fSHawking Zhang #define regGDS_OA_VMID2_BASE_IDX 0 4866f33ac92fSHawking Zhang #define regGDS_OA_VMID3 0x20d3 4867f33ac92fSHawking Zhang #define regGDS_OA_VMID3_BASE_IDX 0 4868f33ac92fSHawking Zhang #define regGDS_OA_VMID4 0x20d4 4869f33ac92fSHawking Zhang #define regGDS_OA_VMID4_BASE_IDX 0 4870f33ac92fSHawking Zhang #define regGDS_OA_VMID5 0x20d5 4871f33ac92fSHawking Zhang #define regGDS_OA_VMID5_BASE_IDX 0 4872f33ac92fSHawking Zhang #define regGDS_OA_VMID6 0x20d6 4873f33ac92fSHawking Zhang #define regGDS_OA_VMID6_BASE_IDX 0 4874f33ac92fSHawking Zhang #define regGDS_OA_VMID7 0x20d7 4875f33ac92fSHawking Zhang #define regGDS_OA_VMID7_BASE_IDX 0 4876f33ac92fSHawking Zhang #define regGDS_OA_VMID8 0x20d8 4877f33ac92fSHawking Zhang #define regGDS_OA_VMID8_BASE_IDX 0 4878f33ac92fSHawking Zhang #define regGDS_OA_VMID9 0x20d9 4879f33ac92fSHawking Zhang #define regGDS_OA_VMID9_BASE_IDX 0 4880f33ac92fSHawking Zhang #define regGDS_OA_VMID10 0x20da 4881f33ac92fSHawking Zhang #define regGDS_OA_VMID10_BASE_IDX 0 4882f33ac92fSHawking Zhang #define regGDS_OA_VMID11 0x20db 4883f33ac92fSHawking Zhang #define regGDS_OA_VMID11_BASE_IDX 0 4884f33ac92fSHawking Zhang #define regGDS_OA_VMID12 0x20dc 4885f33ac92fSHawking Zhang #define regGDS_OA_VMID12_BASE_IDX 0 4886f33ac92fSHawking Zhang #define regGDS_OA_VMID13 0x20dd 4887f33ac92fSHawking Zhang #define regGDS_OA_VMID13_BASE_IDX 0 4888f33ac92fSHawking Zhang #define regGDS_OA_VMID14 0x20de 4889f33ac92fSHawking Zhang #define regGDS_OA_VMID14_BASE_IDX 0 4890f33ac92fSHawking Zhang #define regGDS_OA_VMID15 0x20df 4891f33ac92fSHawking Zhang #define regGDS_OA_VMID15_BASE_IDX 0 4892f33ac92fSHawking Zhang #define regGDS_GWS_RESET0 0x20e4 4893f33ac92fSHawking Zhang #define regGDS_GWS_RESET0_BASE_IDX 0 4894f33ac92fSHawking Zhang #define regGDS_GWS_RESET1 0x20e5 4895f33ac92fSHawking Zhang #define regGDS_GWS_RESET1_BASE_IDX 0 4896f33ac92fSHawking Zhang #define regGDS_GWS_RESOURCE_RESET 0x20e6 4897f33ac92fSHawking Zhang #define regGDS_GWS_RESOURCE_RESET_BASE_IDX 0 4898f33ac92fSHawking Zhang #define regGDS_COMPUTE_MAX_WAVE_ID 0x20e8 4899f33ac92fSHawking Zhang #define regGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX 0 4900f33ac92fSHawking Zhang #define regGDS_OA_RESET_MASK 0x20e9 4901f33ac92fSHawking Zhang #define regGDS_OA_RESET_MASK_BASE_IDX 0 4902f33ac92fSHawking Zhang #define regGDS_OA_RESET 0x20ea 4903f33ac92fSHawking Zhang #define regGDS_OA_RESET_BASE_IDX 0 4904f33ac92fSHawking Zhang #define regGDS_CS_CTXSW_STATUS 0x20ed 4905f33ac92fSHawking Zhang #define regGDS_CS_CTXSW_STATUS_BASE_IDX 0 4906f33ac92fSHawking Zhang #define regGDS_CS_CTXSW_CNT0 0x20ee 4907f33ac92fSHawking Zhang #define regGDS_CS_CTXSW_CNT0_BASE_IDX 0 4908f33ac92fSHawking Zhang #define regGDS_CS_CTXSW_CNT1 0x20ef 4909f33ac92fSHawking Zhang #define regGDS_CS_CTXSW_CNT1_BASE_IDX 0 4910f33ac92fSHawking Zhang #define regGDS_CS_CTXSW_CNT2 0x20f0 4911f33ac92fSHawking Zhang #define regGDS_CS_CTXSW_CNT2_BASE_IDX 0 4912f33ac92fSHawking Zhang #define regGDS_CS_CTXSW_CNT3 0x20f1 4913f33ac92fSHawking Zhang #define regGDS_CS_CTXSW_CNT3_BASE_IDX 0 4914f33ac92fSHawking Zhang #define regGDS_GFX_CTXSW_STATUS 0x20f2 4915f33ac92fSHawking Zhang #define regGDS_GFX_CTXSW_STATUS_BASE_IDX 0 4916f33ac92fSHawking Zhang #define regGDS_PS_CTXSW_CNT0 0x20f7 4917f33ac92fSHawking Zhang #define regGDS_PS_CTXSW_CNT0_BASE_IDX 0 4918f33ac92fSHawking Zhang #define regGDS_PS_CTXSW_CNT1 0x20f8 4919f33ac92fSHawking Zhang #define regGDS_PS_CTXSW_CNT1_BASE_IDX 0 4920f33ac92fSHawking Zhang #define regGDS_PS_CTXSW_CNT2 0x20f9 4921f33ac92fSHawking Zhang #define regGDS_PS_CTXSW_CNT2_BASE_IDX 0 4922f33ac92fSHawking Zhang #define regGDS_PS_CTXSW_CNT3 0x20fa 4923f33ac92fSHawking Zhang #define regGDS_PS_CTXSW_CNT3_BASE_IDX 0 4924f33ac92fSHawking Zhang #define regGDS_PS_CTXSW_IDX 0x20fb 4925f33ac92fSHawking Zhang #define regGDS_PS_CTXSW_IDX_BASE_IDX 0 4926f33ac92fSHawking Zhang #define regGDS_GS_CTXSW_CNT0 0x2117 4927f33ac92fSHawking Zhang #define regGDS_GS_CTXSW_CNT0_BASE_IDX 0 4928f33ac92fSHawking Zhang #define regGDS_GS_CTXSW_CNT1 0x2118 4929f33ac92fSHawking Zhang #define regGDS_GS_CTXSW_CNT1_BASE_IDX 0 4930f33ac92fSHawking Zhang #define regGDS_GS_CTXSW_CNT2 0x2119 4931f33ac92fSHawking Zhang #define regGDS_GS_CTXSW_CNT2_BASE_IDX 0 4932f33ac92fSHawking Zhang #define regGDS_GS_CTXSW_CNT3 0x211a 4933f33ac92fSHawking Zhang #define regGDS_GS_CTXSW_CNT3_BASE_IDX 0 4934f33ac92fSHawking Zhang #define regGDS_MEMORY_CLEAN 0x211f 4935f33ac92fSHawking Zhang #define regGDS_MEMORY_CLEAN_BASE_IDX 0 4936f33ac92fSHawking Zhang 4937f33ac92fSHawking Zhang 4938f33ac92fSHawking Zhang // addressBlock: gc_gusdec 4939f33ac92fSHawking Zhang // base address: 0x33000 4940f33ac92fSHawking Zhang #define regGUS_IO_RD_COMBINE_FLUSH 0x2c00 4941f33ac92fSHawking Zhang #define regGUS_IO_RD_COMBINE_FLUSH_BASE_IDX 1 4942f33ac92fSHawking Zhang #define regGUS_IO_WR_COMBINE_FLUSH 0x2c01 4943f33ac92fSHawking Zhang #define regGUS_IO_WR_COMBINE_FLUSH_BASE_IDX 1 4944f33ac92fSHawking Zhang #define regGUS_IO_RD_PRI_AGE_RATE 0x2c02 4945f33ac92fSHawking Zhang #define regGUS_IO_RD_PRI_AGE_RATE_BASE_IDX 1 4946f33ac92fSHawking Zhang #define regGUS_IO_WR_PRI_AGE_RATE 0x2c03 4947f33ac92fSHawking Zhang #define regGUS_IO_WR_PRI_AGE_RATE_BASE_IDX 1 4948f33ac92fSHawking Zhang #define regGUS_IO_RD_PRI_AGE_COEFF 0x2c04 4949f33ac92fSHawking Zhang #define regGUS_IO_RD_PRI_AGE_COEFF_BASE_IDX 1 4950f33ac92fSHawking Zhang #define regGUS_IO_WR_PRI_AGE_COEFF 0x2c05 4951f33ac92fSHawking Zhang #define regGUS_IO_WR_PRI_AGE_COEFF_BASE_IDX 1 4952f33ac92fSHawking Zhang #define regGUS_IO_RD_PRI_QUEUING 0x2c06 4953f33ac92fSHawking Zhang #define regGUS_IO_RD_PRI_QUEUING_BASE_IDX 1 4954f33ac92fSHawking Zhang #define regGUS_IO_WR_PRI_QUEUING 0x2c07 4955f33ac92fSHawking Zhang #define regGUS_IO_WR_PRI_QUEUING_BASE_IDX 1 4956f33ac92fSHawking Zhang #define regGUS_IO_RD_PRI_FIXED 0x2c08 4957f33ac92fSHawking Zhang #define regGUS_IO_RD_PRI_FIXED_BASE_IDX 1 4958f33ac92fSHawking Zhang #define regGUS_IO_WR_PRI_FIXED 0x2c09 4959f33ac92fSHawking Zhang #define regGUS_IO_WR_PRI_FIXED_BASE_IDX 1 4960f33ac92fSHawking Zhang #define regGUS_IO_RD_PRI_URGENCY_COEFF 0x2c0a 4961f33ac92fSHawking Zhang #define regGUS_IO_RD_PRI_URGENCY_COEFF_BASE_IDX 1 4962f33ac92fSHawking Zhang #define regGUS_IO_WR_PRI_URGENCY_COEFF 0x2c0b 4963f33ac92fSHawking Zhang #define regGUS_IO_WR_PRI_URGENCY_COEFF_BASE_IDX 1 4964f33ac92fSHawking Zhang #define regGUS_IO_RD_PRI_URGENCY_MODE 0x2c0c 4965f33ac92fSHawking Zhang #define regGUS_IO_RD_PRI_URGENCY_MODE_BASE_IDX 1 4966f33ac92fSHawking Zhang #define regGUS_IO_WR_PRI_URGENCY_MODE 0x2c0d 4967f33ac92fSHawking Zhang #define regGUS_IO_WR_PRI_URGENCY_MODE_BASE_IDX 1 4968f33ac92fSHawking Zhang #define regGUS_IO_RD_PRI_QUANT_PRI1 0x2c0e 4969f33ac92fSHawking Zhang #define regGUS_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 4970f33ac92fSHawking Zhang #define regGUS_IO_RD_PRI_QUANT_PRI2 0x2c0f 4971f33ac92fSHawking Zhang #define regGUS_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 4972f33ac92fSHawking Zhang #define regGUS_IO_RD_PRI_QUANT_PRI3 0x2c10 4973f33ac92fSHawking Zhang #define regGUS_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 4974f33ac92fSHawking Zhang #define regGUS_IO_RD_PRI_QUANT_PRI4 0x2c11 4975f33ac92fSHawking Zhang #define regGUS_IO_RD_PRI_QUANT_PRI4_BASE_IDX 1 4976f33ac92fSHawking Zhang #define regGUS_IO_WR_PRI_QUANT_PRI1 0x2c12 4977f33ac92fSHawking Zhang #define regGUS_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 4978f33ac92fSHawking Zhang #define regGUS_IO_WR_PRI_QUANT_PRI2 0x2c13 4979f33ac92fSHawking Zhang #define regGUS_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 4980f33ac92fSHawking Zhang #define regGUS_IO_WR_PRI_QUANT_PRI3 0x2c14 4981f33ac92fSHawking Zhang #define regGUS_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 4982f33ac92fSHawking Zhang #define regGUS_IO_WR_PRI_QUANT_PRI4 0x2c15 4983f33ac92fSHawking Zhang #define regGUS_IO_WR_PRI_QUANT_PRI4_BASE_IDX 1 4984f33ac92fSHawking Zhang #define regGUS_IO_RD_PRI_QUANT1_PRI1 0x2c16 4985f33ac92fSHawking Zhang #define regGUS_IO_RD_PRI_QUANT1_PRI1_BASE_IDX 1 4986f33ac92fSHawking Zhang #define regGUS_IO_RD_PRI_QUANT1_PRI2 0x2c17 4987f33ac92fSHawking Zhang #define regGUS_IO_RD_PRI_QUANT1_PRI2_BASE_IDX 1 4988f33ac92fSHawking Zhang #define regGUS_IO_RD_PRI_QUANT1_PRI3 0x2c18 4989f33ac92fSHawking Zhang #define regGUS_IO_RD_PRI_QUANT1_PRI3_BASE_IDX 1 4990f33ac92fSHawking Zhang #define regGUS_IO_RD_PRI_QUANT1_PRI4 0x2c19 4991f33ac92fSHawking Zhang #define regGUS_IO_RD_PRI_QUANT1_PRI4_BASE_IDX 1 4992f33ac92fSHawking Zhang #define regGUS_IO_WR_PRI_QUANT1_PRI1 0x2c1a 4993f33ac92fSHawking Zhang #define regGUS_IO_WR_PRI_QUANT1_PRI1_BASE_IDX 1 4994f33ac92fSHawking Zhang #define regGUS_IO_WR_PRI_QUANT1_PRI2 0x2c1b 4995f33ac92fSHawking Zhang #define regGUS_IO_WR_PRI_QUANT1_PRI2_BASE_IDX 1 4996f33ac92fSHawking Zhang #define regGUS_IO_WR_PRI_QUANT1_PRI3 0x2c1c 4997f33ac92fSHawking Zhang #define regGUS_IO_WR_PRI_QUANT1_PRI3_BASE_IDX 1 4998f33ac92fSHawking Zhang #define regGUS_IO_WR_PRI_QUANT1_PRI4 0x2c1d 4999f33ac92fSHawking Zhang #define regGUS_IO_WR_PRI_QUANT1_PRI4_BASE_IDX 1 5000f33ac92fSHawking Zhang #define regGUS_DRAM_COMBINE_FLUSH 0x2c1e 5001f33ac92fSHawking Zhang #define regGUS_DRAM_COMBINE_FLUSH_BASE_IDX 1 5002f33ac92fSHawking Zhang #define regGUS_DRAM_COMBINE_RD_WR_EN 0x2c1f 5003f33ac92fSHawking Zhang #define regGUS_DRAM_COMBINE_RD_WR_EN_BASE_IDX 1 5004f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_AGE_RATE 0x2c20 5005f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_AGE_RATE_BASE_IDX 1 5006f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_AGE_COEFF 0x2c21 5007f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_AGE_COEFF_BASE_IDX 1 5008f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_QUEUING 0x2c22 5009f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_QUEUING_BASE_IDX 1 5010f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_FIXED 0x2c23 5011f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_FIXED_BASE_IDX 1 5012f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_URGENCY_COEFF 0x2c24 5013f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_URGENCY_COEFF_BASE_IDX 1 5014f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_URGENCY_MODE 0x2c25 5015f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_URGENCY_MODE_BASE_IDX 1 5016f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_QUANT_PRI1 0x2c26 5017f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_QUANT_PRI1_BASE_IDX 1 5018f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_QUANT_PRI2 0x2c27 5019f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_QUANT_PRI2_BASE_IDX 1 5020f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_QUANT_PRI3 0x2c28 5021f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_QUANT_PRI3_BASE_IDX 1 5022f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_QUANT_PRI4 0x2c29 5023f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_QUANT_PRI4_BASE_IDX 1 5024f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_QUANT_PRI5 0x2c2a 5025f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_QUANT_PRI5_BASE_IDX 1 5026f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_QUANT1_PRI1 0x2c2b 5027f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_QUANT1_PRI1_BASE_IDX 1 5028f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_QUANT1_PRI2 0x2c2c 5029f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_QUANT1_PRI2_BASE_IDX 1 5030f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_QUANT1_PRI3 0x2c2d 5031f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_QUANT1_PRI3_BASE_IDX 1 5032f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_QUANT1_PRI4 0x2c2e 5033f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_QUANT1_PRI4_BASE_IDX 1 5034f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_QUANT1_PRI5 0x2c2f 5035f33ac92fSHawking Zhang #define regGUS_DRAM_PRI_QUANT1_PRI5_BASE_IDX 1 5036f33ac92fSHawking Zhang #define regGUS_IO_GROUP_BURST 0x2c30 5037f33ac92fSHawking Zhang #define regGUS_IO_GROUP_BURST_BASE_IDX 1 5038f33ac92fSHawking Zhang #define regGUS_DRAM_GROUP_BURST 0x2c31 5039f33ac92fSHawking Zhang #define regGUS_DRAM_GROUP_BURST_BASE_IDX 1 5040f33ac92fSHawking Zhang #define regGUS_SDP_ARB_FINAL 0x2c32 5041f33ac92fSHawking Zhang #define regGUS_SDP_ARB_FINAL_BASE_IDX 1 5042f33ac92fSHawking Zhang #define regGUS_SDP_QOS_VC_PRIORITY 0x2c33 5043f33ac92fSHawking Zhang #define regGUS_SDP_QOS_VC_PRIORITY_BASE_IDX 1 5044f33ac92fSHawking Zhang #define regGUS_SDP_CREDITS 0x2c34 5045f33ac92fSHawking Zhang #define regGUS_SDP_CREDITS_BASE_IDX 1 5046f33ac92fSHawking Zhang #define regGUS_SDP_TAG_RESERVE0 0x2c35 5047f33ac92fSHawking Zhang #define regGUS_SDP_TAG_RESERVE0_BASE_IDX 1 5048f33ac92fSHawking Zhang #define regGUS_SDP_TAG_RESERVE1 0x2c36 5049f33ac92fSHawking Zhang #define regGUS_SDP_TAG_RESERVE1_BASE_IDX 1 5050f33ac92fSHawking Zhang #define regGUS_SDP_VCC_RESERVE0 0x2c37 5051f33ac92fSHawking Zhang #define regGUS_SDP_VCC_RESERVE0_BASE_IDX 1 5052f33ac92fSHawking Zhang #define regGUS_SDP_VCC_RESERVE1 0x2c38 5053f33ac92fSHawking Zhang #define regGUS_SDP_VCC_RESERVE1_BASE_IDX 1 5054f33ac92fSHawking Zhang #define regGUS_SDP_VCD_RESERVE0 0x2c39 5055f33ac92fSHawking Zhang #define regGUS_SDP_VCD_RESERVE0_BASE_IDX 1 5056f33ac92fSHawking Zhang #define regGUS_SDP_VCD_RESERVE1 0x2c3a 5057f33ac92fSHawking Zhang #define regGUS_SDP_VCD_RESERVE1_BASE_IDX 1 5058f33ac92fSHawking Zhang #define regGUS_SDP_REQ_CNTL 0x2c3b 5059f33ac92fSHawking Zhang #define regGUS_SDP_REQ_CNTL_BASE_IDX 1 5060f33ac92fSHawking Zhang #define regGUS_MISC 0x2c3c 5061f33ac92fSHawking Zhang #define regGUS_MISC_BASE_IDX 1 5062f33ac92fSHawking Zhang #define regGUS_LATENCY_SAMPLING 0x2c3d 5063f33ac92fSHawking Zhang #define regGUS_LATENCY_SAMPLING_BASE_IDX 1 5064f33ac92fSHawking Zhang #define regGUS_ERR_STATUS 0x2c3e 5065f33ac92fSHawking Zhang #define regGUS_ERR_STATUS_BASE_IDX 1 5066f33ac92fSHawking Zhang #define regGUS_MISC2 0x2c3f 5067f33ac92fSHawking Zhang #define regGUS_MISC2_BASE_IDX 1 5068f33ac92fSHawking Zhang #define regGUS_SDP_ENABLE 0x2c45 5069f33ac92fSHawking Zhang #define regGUS_SDP_ENABLE_BASE_IDX 1 5070f33ac92fSHawking Zhang #define regGUS_L1_CH0_CMD_IN 0x2c46 5071f33ac92fSHawking Zhang #define regGUS_L1_CH0_CMD_IN_BASE_IDX 1 5072f33ac92fSHawking Zhang #define regGUS_L1_CH0_CMD_OUT 0x2c47 5073f33ac92fSHawking Zhang #define regGUS_L1_CH0_CMD_OUT_BASE_IDX 1 5074f33ac92fSHawking Zhang #define regGUS_L1_CH0_DATA_IN 0x2c48 5075f33ac92fSHawking Zhang #define regGUS_L1_CH0_DATA_IN_BASE_IDX 1 5076f33ac92fSHawking Zhang #define regGUS_L1_CH0_DATA_OUT 0x2c49 5077f33ac92fSHawking Zhang #define regGUS_L1_CH0_DATA_OUT_BASE_IDX 1 5078f33ac92fSHawking Zhang #define regGUS_L1_CH0_DATA_U_IN 0x2c4a 5079f33ac92fSHawking Zhang #define regGUS_L1_CH0_DATA_U_IN_BASE_IDX 1 5080f33ac92fSHawking Zhang #define regGUS_L1_CH0_DATA_U_OUT 0x2c4b 5081f33ac92fSHawking Zhang #define regGUS_L1_CH0_DATA_U_OUT_BASE_IDX 1 5082f33ac92fSHawking Zhang #define regGUS_L1_CH1_CMD_IN 0x2c4c 5083f33ac92fSHawking Zhang #define regGUS_L1_CH1_CMD_IN_BASE_IDX 1 5084f33ac92fSHawking Zhang #define regGUS_L1_CH1_CMD_OUT 0x2c4d 5085f33ac92fSHawking Zhang #define regGUS_L1_CH1_CMD_OUT_BASE_IDX 1 5086f33ac92fSHawking Zhang #define regGUS_L1_CH1_DATA_IN 0x2c4e 5087f33ac92fSHawking Zhang #define regGUS_L1_CH1_DATA_IN_BASE_IDX 1 5088f33ac92fSHawking Zhang #define regGUS_L1_CH1_DATA_OUT 0x2c4f 5089f33ac92fSHawking Zhang #define regGUS_L1_CH1_DATA_OUT_BASE_IDX 1 5090f33ac92fSHawking Zhang #define regGUS_L1_CH1_DATA_U_IN 0x2c50 5091f33ac92fSHawking Zhang #define regGUS_L1_CH1_DATA_U_IN_BASE_IDX 1 5092f33ac92fSHawking Zhang #define regGUS_L1_CH1_DATA_U_OUT 0x2c51 5093f33ac92fSHawking Zhang #define regGUS_L1_CH1_DATA_U_OUT_BASE_IDX 1 5094f33ac92fSHawking Zhang #define regGUS_L1_SA0_CMD_IN 0x2c52 5095f33ac92fSHawking Zhang #define regGUS_L1_SA0_CMD_IN_BASE_IDX 1 5096f33ac92fSHawking Zhang #define regGUS_L1_SA0_CMD_OUT 0x2c53 5097f33ac92fSHawking Zhang #define regGUS_L1_SA0_CMD_OUT_BASE_IDX 1 5098f33ac92fSHawking Zhang #define regGUS_L1_SA0_DATA_IN 0x2c54 5099f33ac92fSHawking Zhang #define regGUS_L1_SA0_DATA_IN_BASE_IDX 1 5100f33ac92fSHawking Zhang #define regGUS_L1_SA0_DATA_OUT 0x2c55 5101f33ac92fSHawking Zhang #define regGUS_L1_SA0_DATA_OUT_BASE_IDX 1 5102f33ac92fSHawking Zhang #define regGUS_L1_SA0_DATA_U_IN 0x2c56 5103f33ac92fSHawking Zhang #define regGUS_L1_SA0_DATA_U_IN_BASE_IDX 1 5104f33ac92fSHawking Zhang #define regGUS_L1_SA0_DATA_U_OUT 0x2c57 5105f33ac92fSHawking Zhang #define regGUS_L1_SA0_DATA_U_OUT_BASE_IDX 1 5106f33ac92fSHawking Zhang #define regGUS_L1_SA1_CMD_IN 0x2c58 5107f33ac92fSHawking Zhang #define regGUS_L1_SA1_CMD_IN_BASE_IDX 1 5108f33ac92fSHawking Zhang #define regGUS_L1_SA1_CMD_OUT 0x2c59 5109f33ac92fSHawking Zhang #define regGUS_L1_SA1_CMD_OUT_BASE_IDX 1 5110f33ac92fSHawking Zhang #define regGUS_L1_SA1_DATA_IN 0x2c5a 5111f33ac92fSHawking Zhang #define regGUS_L1_SA1_DATA_IN_BASE_IDX 1 5112f33ac92fSHawking Zhang #define regGUS_L1_SA1_DATA_OUT 0x2c5b 5113f33ac92fSHawking Zhang #define regGUS_L1_SA1_DATA_OUT_BASE_IDX 1 5114f33ac92fSHawking Zhang #define regGUS_L1_SA1_DATA_U_IN 0x2c5c 5115f33ac92fSHawking Zhang #define regGUS_L1_SA1_DATA_U_IN_BASE_IDX 1 5116f33ac92fSHawking Zhang #define regGUS_L1_SA1_DATA_U_OUT 0x2c5d 5117f33ac92fSHawking Zhang #define regGUS_L1_SA1_DATA_U_OUT_BASE_IDX 1 5118f33ac92fSHawking Zhang #define regGUS_L1_SA2_CMD_IN 0x2c5e 5119f33ac92fSHawking Zhang #define regGUS_L1_SA2_CMD_IN_BASE_IDX 1 5120f33ac92fSHawking Zhang #define regGUS_L1_SA2_CMD_OUT 0x2c5f 5121f33ac92fSHawking Zhang #define regGUS_L1_SA2_CMD_OUT_BASE_IDX 1 5122f33ac92fSHawking Zhang #define regGUS_L1_SA2_DATA_IN 0x2c60 5123f33ac92fSHawking Zhang #define regGUS_L1_SA2_DATA_IN_BASE_IDX 1 5124f33ac92fSHawking Zhang #define regGUS_L1_SA2_DATA_OUT 0x2c61 5125f33ac92fSHawking Zhang #define regGUS_L1_SA2_DATA_OUT_BASE_IDX 1 5126f33ac92fSHawking Zhang #define regGUS_L1_SA2_DATA_U_IN 0x2c62 5127f33ac92fSHawking Zhang #define regGUS_L1_SA2_DATA_U_IN_BASE_IDX 1 5128f33ac92fSHawking Zhang #define regGUS_L1_SA2_DATA_U_OUT 0x2c63 5129f33ac92fSHawking Zhang #define regGUS_L1_SA2_DATA_U_OUT_BASE_IDX 1 5130f33ac92fSHawking Zhang #define regGUS_L1_SA3_CMD_IN 0x2c64 5131f33ac92fSHawking Zhang #define regGUS_L1_SA3_CMD_IN_BASE_IDX 1 5132f33ac92fSHawking Zhang #define regGUS_L1_SA3_CMD_OUT 0x2c65 5133f33ac92fSHawking Zhang #define regGUS_L1_SA3_CMD_OUT_BASE_IDX 1 5134f33ac92fSHawking Zhang #define regGUS_L1_SA3_DATA_IN 0x2c66 5135f33ac92fSHawking Zhang #define regGUS_L1_SA3_DATA_IN_BASE_IDX 1 5136f33ac92fSHawking Zhang #define regGUS_L1_SA3_DATA_OUT 0x2c67 5137f33ac92fSHawking Zhang #define regGUS_L1_SA3_DATA_OUT_BASE_IDX 1 5138f33ac92fSHawking Zhang #define regGUS_L1_SA3_DATA_U_IN 0x2c68 5139f33ac92fSHawking Zhang #define regGUS_L1_SA3_DATA_U_IN_BASE_IDX 1 5140f33ac92fSHawking Zhang #define regGUS_L1_SA3_DATA_U_OUT 0x2c69 5141f33ac92fSHawking Zhang #define regGUS_L1_SA3_DATA_U_OUT_BASE_IDX 1 5142f33ac92fSHawking Zhang #define regGUS_MISC3 0x2c6a 5143f33ac92fSHawking Zhang #define regGUS_MISC3_BASE_IDX 1 5144f33ac92fSHawking Zhang #define regGUS_WRRSP_FIFO_CNTL 0x2c6b 5145f33ac92fSHawking Zhang #define regGUS_WRRSP_FIFO_CNTL_BASE_IDX 1 5146f33ac92fSHawking Zhang 5147f33ac92fSHawking Zhang 5148f33ac92fSHawking Zhang // addressBlock: gc_gfxdec0 5149f33ac92fSHawking Zhang // base address: 0x28000 5150f33ac92fSHawking Zhang #define regDB_RENDER_CONTROL 0x0000 5151f33ac92fSHawking Zhang #define regDB_RENDER_CONTROL_BASE_IDX 1 5152f33ac92fSHawking Zhang #define regDB_COUNT_CONTROL 0x0001 5153f33ac92fSHawking Zhang #define regDB_COUNT_CONTROL_BASE_IDX 1 5154f33ac92fSHawking Zhang #define regDB_DEPTH_VIEW 0x0002 5155f33ac92fSHawking Zhang #define regDB_DEPTH_VIEW_BASE_IDX 1 5156f33ac92fSHawking Zhang #define regDB_RENDER_OVERRIDE 0x0003 5157f33ac92fSHawking Zhang #define regDB_RENDER_OVERRIDE_BASE_IDX 1 5158f33ac92fSHawking Zhang #define regDB_RENDER_OVERRIDE2 0x0004 5159f33ac92fSHawking Zhang #define regDB_RENDER_OVERRIDE2_BASE_IDX 1 5160f33ac92fSHawking Zhang #define regDB_HTILE_DATA_BASE 0x0005 5161f33ac92fSHawking Zhang #define regDB_HTILE_DATA_BASE_BASE_IDX 1 5162f33ac92fSHawking Zhang #define regDB_DEPTH_SIZE_XY 0x0007 5163f33ac92fSHawking Zhang #define regDB_DEPTH_SIZE_XY_BASE_IDX 1 5164f33ac92fSHawking Zhang #define regDB_DEPTH_BOUNDS_MIN 0x0008 5165f33ac92fSHawking Zhang #define regDB_DEPTH_BOUNDS_MIN_BASE_IDX 1 5166f33ac92fSHawking Zhang #define regDB_DEPTH_BOUNDS_MAX 0x0009 5167f33ac92fSHawking Zhang #define regDB_DEPTH_BOUNDS_MAX_BASE_IDX 1 5168f33ac92fSHawking Zhang #define regDB_STENCIL_CLEAR 0x000a 5169f33ac92fSHawking Zhang #define regDB_STENCIL_CLEAR_BASE_IDX 1 5170f33ac92fSHawking Zhang #define regDB_DEPTH_CLEAR 0x000b 5171f33ac92fSHawking Zhang #define regDB_DEPTH_CLEAR_BASE_IDX 1 5172f33ac92fSHawking Zhang #define regPA_SC_SCREEN_SCISSOR_TL 0x000c 5173f33ac92fSHawking Zhang #define regPA_SC_SCREEN_SCISSOR_TL_BASE_IDX 1 5174f33ac92fSHawking Zhang #define regPA_SC_SCREEN_SCISSOR_BR 0x000d 5175f33ac92fSHawking Zhang #define regPA_SC_SCREEN_SCISSOR_BR_BASE_IDX 1 5176f33ac92fSHawking Zhang #define regDB_RESERVED_REG_2 0x000f 5177f33ac92fSHawking Zhang #define regDB_RESERVED_REG_2_BASE_IDX 1 5178f33ac92fSHawking Zhang #define regDB_Z_INFO 0x0010 5179f33ac92fSHawking Zhang #define regDB_Z_INFO_BASE_IDX 1 5180f33ac92fSHawking Zhang #define regDB_STENCIL_INFO 0x0011 5181f33ac92fSHawking Zhang #define regDB_STENCIL_INFO_BASE_IDX 1 5182f33ac92fSHawking Zhang #define regDB_Z_READ_BASE 0x0012 5183f33ac92fSHawking Zhang #define regDB_Z_READ_BASE_BASE_IDX 1 5184f33ac92fSHawking Zhang #define regDB_STENCIL_READ_BASE 0x0013 5185f33ac92fSHawking Zhang #define regDB_STENCIL_READ_BASE_BASE_IDX 1 5186f33ac92fSHawking Zhang #define regDB_Z_WRITE_BASE 0x0014 5187f33ac92fSHawking Zhang #define regDB_Z_WRITE_BASE_BASE_IDX 1 5188f33ac92fSHawking Zhang #define regDB_STENCIL_WRITE_BASE 0x0015 5189f33ac92fSHawking Zhang #define regDB_STENCIL_WRITE_BASE_BASE_IDX 1 5190f33ac92fSHawking Zhang #define regDB_RESERVED_REG_1 0x0016 5191f33ac92fSHawking Zhang #define regDB_RESERVED_REG_1_BASE_IDX 1 5192f33ac92fSHawking Zhang #define regDB_RESERVED_REG_3 0x0017 5193f33ac92fSHawking Zhang #define regDB_RESERVED_REG_3_BASE_IDX 1 5194f33ac92fSHawking Zhang #define regDB_Z_READ_BASE_HI 0x001a 5195f33ac92fSHawking Zhang #define regDB_Z_READ_BASE_HI_BASE_IDX 1 5196f33ac92fSHawking Zhang #define regDB_STENCIL_READ_BASE_HI 0x001b 5197f33ac92fSHawking Zhang #define regDB_STENCIL_READ_BASE_HI_BASE_IDX 1 5198f33ac92fSHawking Zhang #define regDB_Z_WRITE_BASE_HI 0x001c 5199f33ac92fSHawking Zhang #define regDB_Z_WRITE_BASE_HI_BASE_IDX 1 5200f33ac92fSHawking Zhang #define regDB_STENCIL_WRITE_BASE_HI 0x001d 5201f33ac92fSHawking Zhang #define regDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1 5202f33ac92fSHawking Zhang #define regDB_HTILE_DATA_BASE_HI 0x001e 5203f33ac92fSHawking Zhang #define regDB_HTILE_DATA_BASE_HI_BASE_IDX 1 5204f33ac92fSHawking Zhang #define regDB_RMI_L2_CACHE_CONTROL 0x001f 5205f33ac92fSHawking Zhang #define regDB_RMI_L2_CACHE_CONTROL_BASE_IDX 1 5206f33ac92fSHawking Zhang #define regTA_BC_BASE_ADDR 0x0020 5207f33ac92fSHawking Zhang #define regTA_BC_BASE_ADDR_BASE_IDX 1 5208f33ac92fSHawking Zhang #define regTA_BC_BASE_ADDR_HI 0x0021 5209f33ac92fSHawking Zhang #define regTA_BC_BASE_ADDR_HI_BASE_IDX 1 5210f33ac92fSHawking Zhang #define regCOHER_DEST_BASE_HI_0 0x007a 5211f33ac92fSHawking Zhang #define regCOHER_DEST_BASE_HI_0_BASE_IDX 1 5212f33ac92fSHawking Zhang #define regCOHER_DEST_BASE_HI_1 0x007b 5213f33ac92fSHawking Zhang #define regCOHER_DEST_BASE_HI_1_BASE_IDX 1 5214f33ac92fSHawking Zhang #define regCOHER_DEST_BASE_HI_2 0x007c 5215f33ac92fSHawking Zhang #define regCOHER_DEST_BASE_HI_2_BASE_IDX 1 5216f33ac92fSHawking Zhang #define regCOHER_DEST_BASE_HI_3 0x007d 5217f33ac92fSHawking Zhang #define regCOHER_DEST_BASE_HI_3_BASE_IDX 1 5218f33ac92fSHawking Zhang #define regCOHER_DEST_BASE_2 0x007e 5219f33ac92fSHawking Zhang #define regCOHER_DEST_BASE_2_BASE_IDX 1 5220f33ac92fSHawking Zhang #define regCOHER_DEST_BASE_3 0x007f 5221f33ac92fSHawking Zhang #define regCOHER_DEST_BASE_3_BASE_IDX 1 5222f33ac92fSHawking Zhang #define regPA_SC_WINDOW_OFFSET 0x0080 5223f33ac92fSHawking Zhang #define regPA_SC_WINDOW_OFFSET_BASE_IDX 1 5224f33ac92fSHawking Zhang #define regPA_SC_WINDOW_SCISSOR_TL 0x0081 5225f33ac92fSHawking Zhang #define regPA_SC_WINDOW_SCISSOR_TL_BASE_IDX 1 5226f33ac92fSHawking Zhang #define regPA_SC_WINDOW_SCISSOR_BR 0x0082 5227f33ac92fSHawking Zhang #define regPA_SC_WINDOW_SCISSOR_BR_BASE_IDX 1 5228f33ac92fSHawking Zhang #define regPA_SC_CLIPRECT_RULE 0x0083 5229f33ac92fSHawking Zhang #define regPA_SC_CLIPRECT_RULE_BASE_IDX 1 5230f33ac92fSHawking Zhang #define regPA_SC_CLIPRECT_0_TL 0x0084 5231f33ac92fSHawking Zhang #define regPA_SC_CLIPRECT_0_TL_BASE_IDX 1 5232f33ac92fSHawking Zhang #define regPA_SC_CLIPRECT_0_BR 0x0085 5233f33ac92fSHawking Zhang #define regPA_SC_CLIPRECT_0_BR_BASE_IDX 1 5234f33ac92fSHawking Zhang #define regPA_SC_CLIPRECT_1_TL 0x0086 5235f33ac92fSHawking Zhang #define regPA_SC_CLIPRECT_1_TL_BASE_IDX 1 5236f33ac92fSHawking Zhang #define regPA_SC_CLIPRECT_1_BR 0x0087 5237f33ac92fSHawking Zhang #define regPA_SC_CLIPRECT_1_BR_BASE_IDX 1 5238f33ac92fSHawking Zhang #define regPA_SC_CLIPRECT_2_TL 0x0088 5239f33ac92fSHawking Zhang #define regPA_SC_CLIPRECT_2_TL_BASE_IDX 1 5240f33ac92fSHawking Zhang #define regPA_SC_CLIPRECT_2_BR 0x0089 5241f33ac92fSHawking Zhang #define regPA_SC_CLIPRECT_2_BR_BASE_IDX 1 5242f33ac92fSHawking Zhang #define regPA_SC_CLIPRECT_3_TL 0x008a 5243f33ac92fSHawking Zhang #define regPA_SC_CLIPRECT_3_TL_BASE_IDX 1 5244f33ac92fSHawking Zhang #define regPA_SC_CLIPRECT_3_BR 0x008b 5245f33ac92fSHawking Zhang #define regPA_SC_CLIPRECT_3_BR_BASE_IDX 1 5246f33ac92fSHawking Zhang #define regPA_SC_EDGERULE 0x008c 5247f33ac92fSHawking Zhang #define regPA_SC_EDGERULE_BASE_IDX 1 5248f33ac92fSHawking Zhang #define regPA_SU_HARDWARE_SCREEN_OFFSET 0x008d 5249f33ac92fSHawking Zhang #define regPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX 1 5250f33ac92fSHawking Zhang #define regCB_TARGET_MASK 0x008e 5251f33ac92fSHawking Zhang #define regCB_TARGET_MASK_BASE_IDX 1 5252f33ac92fSHawking Zhang #define regCB_SHADER_MASK 0x008f 5253f33ac92fSHawking Zhang #define regCB_SHADER_MASK_BASE_IDX 1 5254f33ac92fSHawking Zhang #define regPA_SC_GENERIC_SCISSOR_TL 0x0090 5255f33ac92fSHawking Zhang #define regPA_SC_GENERIC_SCISSOR_TL_BASE_IDX 1 5256f33ac92fSHawking Zhang #define regPA_SC_GENERIC_SCISSOR_BR 0x0091 5257f33ac92fSHawking Zhang #define regPA_SC_GENERIC_SCISSOR_BR_BASE_IDX 1 5258f33ac92fSHawking Zhang #define regCOHER_DEST_BASE_0 0x0092 5259f33ac92fSHawking Zhang #define regCOHER_DEST_BASE_0_BASE_IDX 1 5260f33ac92fSHawking Zhang #define regCOHER_DEST_BASE_1 0x0093 5261f33ac92fSHawking Zhang #define regCOHER_DEST_BASE_1_BASE_IDX 1 5262f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_0_TL 0x0094 5263f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX 1 5264f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_0_BR 0x0095 5265f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX 1 5266f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_1_TL 0x0096 5267f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX 1 5268f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_1_BR 0x0097 5269f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX 1 5270f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_2_TL 0x0098 5271f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX 1 5272f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_2_BR 0x0099 5273f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX 1 5274f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_3_TL 0x009a 5275f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX 1 5276f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_3_BR 0x009b 5277f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX 1 5278f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_4_TL 0x009c 5279f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX 1 5280f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_4_BR 0x009d 5281f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX 1 5282f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_5_TL 0x009e 5283f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX 1 5284f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_5_BR 0x009f 5285f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX 1 5286f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_6_TL 0x00a0 5287f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX 1 5288f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_6_BR 0x00a1 5289f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX 1 5290f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_7_TL 0x00a2 5291f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX 1 5292f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_7_BR 0x00a3 5293f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX 1 5294f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_8_TL 0x00a4 5295f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX 1 5296f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_8_BR 0x00a5 5297f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX 1 5298f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_9_TL 0x00a6 5299f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX 1 5300f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_9_BR 0x00a7 5301f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX 1 5302f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_10_TL 0x00a8 5303f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX 1 5304f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_10_BR 0x00a9 5305f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX 1 5306f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_11_TL 0x00aa 5307f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX 1 5308f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_11_BR 0x00ab 5309f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX 1 5310f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_12_TL 0x00ac 5311f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX 1 5312f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_12_BR 0x00ad 5313f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX 1 5314f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_13_TL 0x00ae 5315f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX 1 5316f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_13_BR 0x00af 5317f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX 1 5318f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_14_TL 0x00b0 5319f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX 1 5320f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_14_BR 0x00b1 5321f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX 1 5322f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_15_TL 0x00b2 5323f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX 1 5324f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_15_BR 0x00b3 5325f33ac92fSHawking Zhang #define regPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX 1 5326f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_0 0x00b4 5327f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_0_BASE_IDX 1 5328f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_0 0x00b5 5329f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_0_BASE_IDX 1 5330f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_1 0x00b6 5331f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_1_BASE_IDX 1 5332f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_1 0x00b7 5333f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_1_BASE_IDX 1 5334f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_2 0x00b8 5335f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_2_BASE_IDX 1 5336f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_2 0x00b9 5337f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_2_BASE_IDX 1 5338f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_3 0x00ba 5339f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_3_BASE_IDX 1 5340f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_3 0x00bb 5341f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_3_BASE_IDX 1 5342f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_4 0x00bc 5343f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_4_BASE_IDX 1 5344f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_4 0x00bd 5345f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_4_BASE_IDX 1 5346f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_5 0x00be 5347f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_5_BASE_IDX 1 5348f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_5 0x00bf 5349f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_5_BASE_IDX 1 5350f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_6 0x00c0 5351f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_6_BASE_IDX 1 5352f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_6 0x00c1 5353f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_6_BASE_IDX 1 5354f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_7 0x00c2 5355f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_7_BASE_IDX 1 5356f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_7 0x00c3 5357f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_7_BASE_IDX 1 5358f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_8 0x00c4 5359f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_8_BASE_IDX 1 5360f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_8 0x00c5 5361f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_8_BASE_IDX 1 5362f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_9 0x00c6 5363f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_9_BASE_IDX 1 5364f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_9 0x00c7 5365f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_9_BASE_IDX 1 5366f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_10 0x00c8 5367f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_10_BASE_IDX 1 5368f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_10 0x00c9 5369f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_10_BASE_IDX 1 5370f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_11 0x00ca 5371f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_11_BASE_IDX 1 5372f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_11 0x00cb 5373f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_11_BASE_IDX 1 5374f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_12 0x00cc 5375f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_12_BASE_IDX 1 5376f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_12 0x00cd 5377f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_12_BASE_IDX 1 5378f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_13 0x00ce 5379f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_13_BASE_IDX 1 5380f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_13 0x00cf 5381f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_13_BASE_IDX 1 5382f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_14 0x00d0 5383f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_14_BASE_IDX 1 5384f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_14 0x00d1 5385f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_14_BASE_IDX 1 5386f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_15 0x00d2 5387f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMIN_15_BASE_IDX 1 5388f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_15 0x00d3 5389f33ac92fSHawking Zhang #define regPA_SC_VPORT_ZMAX_15_BASE_IDX 1 5390f33ac92fSHawking Zhang #define regPA_SC_RASTER_CONFIG 0x00d4 5391f33ac92fSHawking Zhang #define regPA_SC_RASTER_CONFIG_BASE_IDX 1 5392f33ac92fSHawking Zhang #define regPA_SC_RASTER_CONFIG_1 0x00d5 5393f33ac92fSHawking Zhang #define regPA_SC_RASTER_CONFIG_1_BASE_IDX 1 5394f33ac92fSHawking Zhang #define regPA_SC_SCREEN_EXTENT_CONTROL 0x00d6 5395f33ac92fSHawking Zhang #define regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX 1 5396f33ac92fSHawking Zhang #define regPA_SC_TILE_STEERING_OVERRIDE 0x00d7 5397f33ac92fSHawking Zhang #define regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX 1 5398f33ac92fSHawking Zhang #define regCP_PERFMON_CNTX_CNTL 0x00d8 5399f33ac92fSHawking Zhang #define regCP_PERFMON_CNTX_CNTL_BASE_IDX 1 5400f33ac92fSHawking Zhang #define regCP_PIPEID 0x00d9 5401f33ac92fSHawking Zhang #define regCP_PIPEID_BASE_IDX 1 5402f33ac92fSHawking Zhang #define regCP_RINGID 0x00d9 5403f33ac92fSHawking Zhang #define regCP_RINGID_BASE_IDX 1 5404f33ac92fSHawking Zhang #define regCP_VMID 0x00da 5405f33ac92fSHawking Zhang #define regCP_VMID_BASE_IDX 1 5406f33ac92fSHawking Zhang #define regCONTEXT_RESERVED_REG0 0x00db 5407f33ac92fSHawking Zhang #define regCONTEXT_RESERVED_REG0_BASE_IDX 1 5408f33ac92fSHawking Zhang #define regCONTEXT_RESERVED_REG1 0x00dc 5409f33ac92fSHawking Zhang #define regCONTEXT_RESERVED_REG1_BASE_IDX 1 5410f33ac92fSHawking Zhang #define regPA_SC_VRS_OVERRIDE_CNTL 0x00f4 5411f33ac92fSHawking Zhang #define regPA_SC_VRS_OVERRIDE_CNTL_BASE_IDX 1 5412f33ac92fSHawking Zhang #define regPA_SC_VRS_RATE_FEEDBACK_BASE 0x00f5 5413f33ac92fSHawking Zhang #define regPA_SC_VRS_RATE_FEEDBACK_BASE_BASE_IDX 1 5414f33ac92fSHawking Zhang #define regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT 0x00f6 5415f33ac92fSHawking Zhang #define regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT_BASE_IDX 1 5416f33ac92fSHawking Zhang #define regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY 0x00f7 5417f33ac92fSHawking Zhang #define regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY_BASE_IDX 1 5418f33ac92fSHawking Zhang #define regPA_SC_VRS_RATE_CACHE_CNTL 0x00f9 5419f33ac92fSHawking Zhang #define regPA_SC_VRS_RATE_CACHE_CNTL_BASE_IDX 1 5420f33ac92fSHawking Zhang #define regPA_SC_VRS_RATE_BASE 0x00fc 5421f33ac92fSHawking Zhang #define regPA_SC_VRS_RATE_BASE_BASE_IDX 1 5422f33ac92fSHawking Zhang #define regPA_SC_VRS_RATE_BASE_EXT 0x00fd 5423f33ac92fSHawking Zhang #define regPA_SC_VRS_RATE_BASE_EXT_BASE_IDX 1 5424f33ac92fSHawking Zhang #define regPA_SC_VRS_RATE_SIZE_XY 0x00fe 5425f33ac92fSHawking Zhang #define regPA_SC_VRS_RATE_SIZE_XY_BASE_IDX 1 5426f33ac92fSHawking Zhang #define regVGT_MULTI_PRIM_IB_RESET_INDX 0x0103 5427f33ac92fSHawking Zhang #define regVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1 5428f33ac92fSHawking Zhang #define regCB_RMI_GL2_CACHE_CONTROL 0x0104 5429f33ac92fSHawking Zhang #define regCB_RMI_GL2_CACHE_CONTROL_BASE_IDX 1 5430f33ac92fSHawking Zhang #define regCB_BLEND_RED 0x0105 5431f33ac92fSHawking Zhang #define regCB_BLEND_RED_BASE_IDX 1 5432f33ac92fSHawking Zhang #define regCB_BLEND_GREEN 0x0106 5433f33ac92fSHawking Zhang #define regCB_BLEND_GREEN_BASE_IDX 1 5434f33ac92fSHawking Zhang #define regCB_BLEND_BLUE 0x0107 5435f33ac92fSHawking Zhang #define regCB_BLEND_BLUE_BASE_IDX 1 5436f33ac92fSHawking Zhang #define regCB_BLEND_ALPHA 0x0108 5437f33ac92fSHawking Zhang #define regCB_BLEND_ALPHA_BASE_IDX 1 5438f33ac92fSHawking Zhang #define regCB_FDCC_CONTROL 0x0109 5439f33ac92fSHawking Zhang #define regCB_FDCC_CONTROL_BASE_IDX 1 5440f33ac92fSHawking Zhang #define regCB_COVERAGE_OUT_CONTROL 0x010a 5441f33ac92fSHawking Zhang #define regCB_COVERAGE_OUT_CONTROL_BASE_IDX 1 5442f33ac92fSHawking Zhang #define regDB_STENCIL_CONTROL 0x010b 5443f33ac92fSHawking Zhang #define regDB_STENCIL_CONTROL_BASE_IDX 1 5444f33ac92fSHawking Zhang #define regDB_STENCILREFMASK 0x010c 5445f33ac92fSHawking Zhang #define regDB_STENCILREFMASK_BASE_IDX 1 5446f33ac92fSHawking Zhang #define regDB_STENCILREFMASK_BF 0x010d 5447f33ac92fSHawking Zhang #define regDB_STENCILREFMASK_BF_BASE_IDX 1 5448f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE 0x010f 5449f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_BASE_IDX 1 5450f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET 0x0110 5451f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_BASE_IDX 1 5452f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE 0x0111 5453f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_BASE_IDX 1 5454f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET 0x0112 5455f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_BASE_IDX 1 5456f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE 0x0113 5457f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_BASE_IDX 1 5458f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET 0x0114 5459f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_BASE_IDX 1 5460f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_1 0x0115 5461f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_1_BASE_IDX 1 5462f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_1 0x0116 5463f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_1_BASE_IDX 1 5464f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_1 0x0117 5465f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_1_BASE_IDX 1 5466f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_1 0x0118 5467f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_1_BASE_IDX 1 5468f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_1 0x0119 5469f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_1_BASE_IDX 1 5470f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_1 0x011a 5471f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_1_BASE_IDX 1 5472f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_2 0x011b 5473f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_2_BASE_IDX 1 5474f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_2 0x011c 5475f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_2_BASE_IDX 1 5476f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_2 0x011d 5477f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_2_BASE_IDX 1 5478f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_2 0x011e 5479f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_2_BASE_IDX 1 5480f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_2 0x011f 5481f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_2_BASE_IDX 1 5482f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_2 0x0120 5483f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_2_BASE_IDX 1 5484f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_3 0x0121 5485f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_3_BASE_IDX 1 5486f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_3 0x0122 5487f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_3_BASE_IDX 1 5488f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_3 0x0123 5489f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_3_BASE_IDX 1 5490f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_3 0x0124 5491f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_3_BASE_IDX 1 5492f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_3 0x0125 5493f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_3_BASE_IDX 1 5494f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_3 0x0126 5495f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_3_BASE_IDX 1 5496f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_4 0x0127 5497f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_4_BASE_IDX 1 5498f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_4 0x0128 5499f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_4_BASE_IDX 1 5500f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_4 0x0129 5501f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_4_BASE_IDX 1 5502f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_4 0x012a 5503f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_4_BASE_IDX 1 5504f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_4 0x012b 5505f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_4_BASE_IDX 1 5506f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_4 0x012c 5507f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_4_BASE_IDX 1 5508f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_5 0x012d 5509f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_5_BASE_IDX 1 5510f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_5 0x012e 5511f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_5_BASE_IDX 1 5512f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_5 0x012f 5513f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_5_BASE_IDX 1 5514f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_5 0x0130 5515f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_5_BASE_IDX 1 5516f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_5 0x0131 5517f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_5_BASE_IDX 1 5518f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_5 0x0132 5519f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_5_BASE_IDX 1 5520f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_6 0x0133 5521f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_6_BASE_IDX 1 5522f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_6 0x0134 5523f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_6_BASE_IDX 1 5524f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_6 0x0135 5525f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_6_BASE_IDX 1 5526f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_6 0x0136 5527f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_6_BASE_IDX 1 5528f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_6 0x0137 5529f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_6_BASE_IDX 1 5530f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_6 0x0138 5531f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_6_BASE_IDX 1 5532f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_7 0x0139 5533f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_7_BASE_IDX 1 5534f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_7 0x013a 5535f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_7_BASE_IDX 1 5536f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_7 0x013b 5537f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_7_BASE_IDX 1 5538f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_7 0x013c 5539f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_7_BASE_IDX 1 5540f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_7 0x013d 5541f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_7_BASE_IDX 1 5542f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_7 0x013e 5543f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_7_BASE_IDX 1 5544f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_8 0x013f 5545f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_8_BASE_IDX 1 5546f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_8 0x0140 5547f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_8_BASE_IDX 1 5548f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_8 0x0141 5549f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_8_BASE_IDX 1 5550f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_8 0x0142 5551f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_8_BASE_IDX 1 5552f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_8 0x0143 5553f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_8_BASE_IDX 1 5554f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_8 0x0144 5555f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_8_BASE_IDX 1 5556f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_9 0x0145 5557f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_9_BASE_IDX 1 5558f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_9 0x0146 5559f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_9_BASE_IDX 1 5560f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_9 0x0147 5561f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_9_BASE_IDX 1 5562f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_9 0x0148 5563f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_9_BASE_IDX 1 5564f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_9 0x0149 5565f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_9_BASE_IDX 1 5566f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_9 0x014a 5567f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_9_BASE_IDX 1 5568f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_10 0x014b 5569f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_10_BASE_IDX 1 5570f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_10 0x014c 5571f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_10_BASE_IDX 1 5572f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_10 0x014d 5573f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_10_BASE_IDX 1 5574f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_10 0x014e 5575f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_10_BASE_IDX 1 5576f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_10 0x014f 5577f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_10_BASE_IDX 1 5578f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_10 0x0150 5579f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_10_BASE_IDX 1 5580f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_11 0x0151 5581f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_11_BASE_IDX 1 5582f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_11 0x0152 5583f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_11_BASE_IDX 1 5584f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_11 0x0153 5585f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_11_BASE_IDX 1 5586f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_11 0x0154 5587f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_11_BASE_IDX 1 5588f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_11 0x0155 5589f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_11_BASE_IDX 1 5590f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_11 0x0156 5591f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_11_BASE_IDX 1 5592f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_12 0x0157 5593f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_12_BASE_IDX 1 5594f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_12 0x0158 5595f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_12_BASE_IDX 1 5596f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_12 0x0159 5597f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_12_BASE_IDX 1 5598f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_12 0x015a 5599f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_12_BASE_IDX 1 5600f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_12 0x015b 5601f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_12_BASE_IDX 1 5602f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_12 0x015c 5603f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_12_BASE_IDX 1 5604f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_13 0x015d 5605f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_13_BASE_IDX 1 5606f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_13 0x015e 5607f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_13_BASE_IDX 1 5608f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_13 0x015f 5609f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_13_BASE_IDX 1 5610f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_13 0x0160 5611f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_13_BASE_IDX 1 5612f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_13 0x0161 5613f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_13_BASE_IDX 1 5614f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_13 0x0162 5615f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_13_BASE_IDX 1 5616f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_14 0x0163 5617f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_14_BASE_IDX 1 5618f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_14 0x0164 5619f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_14_BASE_IDX 1 5620f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_14 0x0165 5621f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_14_BASE_IDX 1 5622f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_14 0x0166 5623f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_14_BASE_IDX 1 5624f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_14 0x0167 5625f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_14_BASE_IDX 1 5626f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_14 0x0168 5627f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_14_BASE_IDX 1 5628f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_15 0x0169 5629f33ac92fSHawking Zhang #define regPA_CL_VPORT_XSCALE_15_BASE_IDX 1 5630f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_15 0x016a 5631f33ac92fSHawking Zhang #define regPA_CL_VPORT_XOFFSET_15_BASE_IDX 1 5632f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_15 0x016b 5633f33ac92fSHawking Zhang #define regPA_CL_VPORT_YSCALE_15_BASE_IDX 1 5634f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_15 0x016c 5635f33ac92fSHawking Zhang #define regPA_CL_VPORT_YOFFSET_15_BASE_IDX 1 5636f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_15 0x016d 5637f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZSCALE_15_BASE_IDX 1 5638f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_15 0x016e 5639f33ac92fSHawking Zhang #define regPA_CL_VPORT_ZOFFSET_15_BASE_IDX 1 5640f33ac92fSHawking Zhang #define regPA_CL_UCP_0_X 0x016f 5641f33ac92fSHawking Zhang #define regPA_CL_UCP_0_X_BASE_IDX 1 5642f33ac92fSHawking Zhang #define regPA_CL_UCP_0_Y 0x0170 5643f33ac92fSHawking Zhang #define regPA_CL_UCP_0_Y_BASE_IDX 1 5644f33ac92fSHawking Zhang #define regPA_CL_UCP_0_Z 0x0171 5645f33ac92fSHawking Zhang #define regPA_CL_UCP_0_Z_BASE_IDX 1 5646f33ac92fSHawking Zhang #define regPA_CL_UCP_0_W 0x0172 5647f33ac92fSHawking Zhang #define regPA_CL_UCP_0_W_BASE_IDX 1 5648f33ac92fSHawking Zhang #define regPA_CL_UCP_1_X 0x0173 5649f33ac92fSHawking Zhang #define regPA_CL_UCP_1_X_BASE_IDX 1 5650f33ac92fSHawking Zhang #define regPA_CL_UCP_1_Y 0x0174 5651f33ac92fSHawking Zhang #define regPA_CL_UCP_1_Y_BASE_IDX 1 5652f33ac92fSHawking Zhang #define regPA_CL_UCP_1_Z 0x0175 5653f33ac92fSHawking Zhang #define regPA_CL_UCP_1_Z_BASE_IDX 1 5654f33ac92fSHawking Zhang #define regPA_CL_UCP_1_W 0x0176 5655f33ac92fSHawking Zhang #define regPA_CL_UCP_1_W_BASE_IDX 1 5656f33ac92fSHawking Zhang #define regPA_CL_UCP_2_X 0x0177 5657f33ac92fSHawking Zhang #define regPA_CL_UCP_2_X_BASE_IDX 1 5658f33ac92fSHawking Zhang #define regPA_CL_UCP_2_Y 0x0178 5659f33ac92fSHawking Zhang #define regPA_CL_UCP_2_Y_BASE_IDX 1 5660f33ac92fSHawking Zhang #define regPA_CL_UCP_2_Z 0x0179 5661f33ac92fSHawking Zhang #define regPA_CL_UCP_2_Z_BASE_IDX 1 5662f33ac92fSHawking Zhang #define regPA_CL_UCP_2_W 0x017a 5663f33ac92fSHawking Zhang #define regPA_CL_UCP_2_W_BASE_IDX 1 5664f33ac92fSHawking Zhang #define regPA_CL_UCP_3_X 0x017b 5665f33ac92fSHawking Zhang #define regPA_CL_UCP_3_X_BASE_IDX 1 5666f33ac92fSHawking Zhang #define regPA_CL_UCP_3_Y 0x017c 5667f33ac92fSHawking Zhang #define regPA_CL_UCP_3_Y_BASE_IDX 1 5668f33ac92fSHawking Zhang #define regPA_CL_UCP_3_Z 0x017d 5669f33ac92fSHawking Zhang #define regPA_CL_UCP_3_Z_BASE_IDX 1 5670f33ac92fSHawking Zhang #define regPA_CL_UCP_3_W 0x017e 5671f33ac92fSHawking Zhang #define regPA_CL_UCP_3_W_BASE_IDX 1 5672f33ac92fSHawking Zhang #define regPA_CL_UCP_4_X 0x017f 5673f33ac92fSHawking Zhang #define regPA_CL_UCP_4_X_BASE_IDX 1 5674f33ac92fSHawking Zhang #define regPA_CL_UCP_4_Y 0x0180 5675f33ac92fSHawking Zhang #define regPA_CL_UCP_4_Y_BASE_IDX 1 5676f33ac92fSHawking Zhang #define regPA_CL_UCP_4_Z 0x0181 5677f33ac92fSHawking Zhang #define regPA_CL_UCP_4_Z_BASE_IDX 1 5678f33ac92fSHawking Zhang #define regPA_CL_UCP_4_W 0x0182 5679f33ac92fSHawking Zhang #define regPA_CL_UCP_4_W_BASE_IDX 1 5680f33ac92fSHawking Zhang #define regPA_CL_UCP_5_X 0x0183 5681f33ac92fSHawking Zhang #define regPA_CL_UCP_5_X_BASE_IDX 1 5682f33ac92fSHawking Zhang #define regPA_CL_UCP_5_Y 0x0184 5683f33ac92fSHawking Zhang #define regPA_CL_UCP_5_Y_BASE_IDX 1 5684f33ac92fSHawking Zhang #define regPA_CL_UCP_5_Z 0x0185 5685f33ac92fSHawking Zhang #define regPA_CL_UCP_5_Z_BASE_IDX 1 5686f33ac92fSHawking Zhang #define regPA_CL_UCP_5_W 0x0186 5687f33ac92fSHawking Zhang #define regPA_CL_UCP_5_W_BASE_IDX 1 5688f33ac92fSHawking Zhang #define regPA_CL_PROG_NEAR_CLIP_Z 0x0187 5689f33ac92fSHawking Zhang #define regPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX 1 5690f33ac92fSHawking Zhang #define regPA_RATE_CNTL 0x0188 5691f33ac92fSHawking Zhang #define regPA_RATE_CNTL_BASE_IDX 1 5692f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_0 0x0191 5693f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_0_BASE_IDX 1 5694f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_1 0x0192 5695f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_1_BASE_IDX 1 5696f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_2 0x0193 5697f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_2_BASE_IDX 1 5698f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_3 0x0194 5699f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_3_BASE_IDX 1 5700f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_4 0x0195 5701f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_4_BASE_IDX 1 5702f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_5 0x0196 5703f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_5_BASE_IDX 1 5704f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_6 0x0197 5705f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_6_BASE_IDX 1 5706f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_7 0x0198 5707f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_7_BASE_IDX 1 5708f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_8 0x0199 5709f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_8_BASE_IDX 1 5710f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_9 0x019a 5711f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_9_BASE_IDX 1 5712f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_10 0x019b 5713f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_10_BASE_IDX 1 5714f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_11 0x019c 5715f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_11_BASE_IDX 1 5716f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_12 0x019d 5717f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_12_BASE_IDX 1 5718f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_13 0x019e 5719f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_13_BASE_IDX 1 5720f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_14 0x019f 5721f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_14_BASE_IDX 1 5722f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_15 0x01a0 5723f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_15_BASE_IDX 1 5724f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_16 0x01a1 5725f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_16_BASE_IDX 1 5726f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_17 0x01a2 5727f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_17_BASE_IDX 1 5728f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_18 0x01a3 5729f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_18_BASE_IDX 1 5730f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_19 0x01a4 5731f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_19_BASE_IDX 1 5732f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_20 0x01a5 5733f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_20_BASE_IDX 1 5734f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_21 0x01a6 5735f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_21_BASE_IDX 1 5736f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_22 0x01a7 5737f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_22_BASE_IDX 1 5738f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_23 0x01a8 5739f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_23_BASE_IDX 1 5740f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_24 0x01a9 5741f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_24_BASE_IDX 1 5742f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_25 0x01aa 5743f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_25_BASE_IDX 1 5744f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_26 0x01ab 5745f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_26_BASE_IDX 1 5746f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_27 0x01ac 5747f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_27_BASE_IDX 1 5748f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_28 0x01ad 5749f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_28_BASE_IDX 1 5750f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_29 0x01ae 5751f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_29_BASE_IDX 1 5752f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_30 0x01af 5753f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_30_BASE_IDX 1 5754f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_31 0x01b0 5755f33ac92fSHawking Zhang #define regSPI_PS_INPUT_CNTL_31_BASE_IDX 1 5756f33ac92fSHawking Zhang #define regSPI_VS_OUT_CONFIG 0x01b1 5757f33ac92fSHawking Zhang #define regSPI_VS_OUT_CONFIG_BASE_IDX 1 5758f33ac92fSHawking Zhang #define regSPI_PS_INPUT_ENA 0x01b3 5759f33ac92fSHawking Zhang #define regSPI_PS_INPUT_ENA_BASE_IDX 1 5760f33ac92fSHawking Zhang #define regSPI_PS_INPUT_ADDR 0x01b4 5761f33ac92fSHawking Zhang #define regSPI_PS_INPUT_ADDR_BASE_IDX 1 5762f33ac92fSHawking Zhang #define regSPI_INTERP_CONTROL_0 0x01b5 5763f33ac92fSHawking Zhang #define regSPI_INTERP_CONTROL_0_BASE_IDX 1 5764f33ac92fSHawking Zhang #define regSPI_PS_IN_CONTROL 0x01b6 5765f33ac92fSHawking Zhang #define regSPI_PS_IN_CONTROL_BASE_IDX 1 5766f33ac92fSHawking Zhang #define regSPI_BARYC_CNTL 0x01b8 5767f33ac92fSHawking Zhang #define regSPI_BARYC_CNTL_BASE_IDX 1 5768f33ac92fSHawking Zhang #define regSPI_TMPRING_SIZE 0x01ba 5769f33ac92fSHawking Zhang #define regSPI_TMPRING_SIZE_BASE_IDX 1 5770f33ac92fSHawking Zhang #define regSPI_GFX_SCRATCH_BASE_LO 0x01bb 5771f33ac92fSHawking Zhang #define regSPI_GFX_SCRATCH_BASE_LO_BASE_IDX 1 5772f33ac92fSHawking Zhang #define regSPI_GFX_SCRATCH_BASE_HI 0x01bc 5773f33ac92fSHawking Zhang #define regSPI_GFX_SCRATCH_BASE_HI_BASE_IDX 1 5774f33ac92fSHawking Zhang #define regSPI_SHADER_IDX_FORMAT 0x01c2 5775f33ac92fSHawking Zhang #define regSPI_SHADER_IDX_FORMAT_BASE_IDX 1 5776f33ac92fSHawking Zhang #define regSPI_SHADER_POS_FORMAT 0x01c3 5777f33ac92fSHawking Zhang #define regSPI_SHADER_POS_FORMAT_BASE_IDX 1 5778f33ac92fSHawking Zhang #define regSPI_SHADER_Z_FORMAT 0x01c4 5779f33ac92fSHawking Zhang #define regSPI_SHADER_Z_FORMAT_BASE_IDX 1 5780f33ac92fSHawking Zhang #define regSPI_SHADER_COL_FORMAT 0x01c5 5781f33ac92fSHawking Zhang #define regSPI_SHADER_COL_FORMAT_BASE_IDX 1 5782f33ac92fSHawking Zhang #define regSX_PS_DOWNCONVERT_CONTROL 0x01d4 5783f33ac92fSHawking Zhang #define regSX_PS_DOWNCONVERT_CONTROL_BASE_IDX 1 5784f33ac92fSHawking Zhang #define regSX_PS_DOWNCONVERT 0x01d5 5785f33ac92fSHawking Zhang #define regSX_PS_DOWNCONVERT_BASE_IDX 1 5786f33ac92fSHawking Zhang #define regSX_BLEND_OPT_EPSILON 0x01d6 5787f33ac92fSHawking Zhang #define regSX_BLEND_OPT_EPSILON_BASE_IDX 1 5788f33ac92fSHawking Zhang #define regSX_BLEND_OPT_CONTROL 0x01d7 5789f33ac92fSHawking Zhang #define regSX_BLEND_OPT_CONTROL_BASE_IDX 1 5790f33ac92fSHawking Zhang #define regSX_MRT0_BLEND_OPT 0x01d8 5791f33ac92fSHawking Zhang #define regSX_MRT0_BLEND_OPT_BASE_IDX 1 5792f33ac92fSHawking Zhang #define regSX_MRT1_BLEND_OPT 0x01d9 5793f33ac92fSHawking Zhang #define regSX_MRT1_BLEND_OPT_BASE_IDX 1 5794f33ac92fSHawking Zhang #define regSX_MRT2_BLEND_OPT 0x01da 5795f33ac92fSHawking Zhang #define regSX_MRT2_BLEND_OPT_BASE_IDX 1 5796f33ac92fSHawking Zhang #define regSX_MRT3_BLEND_OPT 0x01db 5797f33ac92fSHawking Zhang #define regSX_MRT3_BLEND_OPT_BASE_IDX 1 5798f33ac92fSHawking Zhang #define regSX_MRT4_BLEND_OPT 0x01dc 5799f33ac92fSHawking Zhang #define regSX_MRT4_BLEND_OPT_BASE_IDX 1 5800f33ac92fSHawking Zhang #define regSX_MRT5_BLEND_OPT 0x01dd 5801f33ac92fSHawking Zhang #define regSX_MRT5_BLEND_OPT_BASE_IDX 1 5802f33ac92fSHawking Zhang #define regSX_MRT6_BLEND_OPT 0x01de 5803f33ac92fSHawking Zhang #define regSX_MRT6_BLEND_OPT_BASE_IDX 1 5804f33ac92fSHawking Zhang #define regSX_MRT7_BLEND_OPT 0x01df 5805f33ac92fSHawking Zhang #define regSX_MRT7_BLEND_OPT_BASE_IDX 1 5806f33ac92fSHawking Zhang #define regCB_BLEND0_CONTROL 0x01e0 5807f33ac92fSHawking Zhang #define regCB_BLEND0_CONTROL_BASE_IDX 1 5808f33ac92fSHawking Zhang #define regCB_BLEND1_CONTROL 0x01e1 5809f33ac92fSHawking Zhang #define regCB_BLEND1_CONTROL_BASE_IDX 1 5810f33ac92fSHawking Zhang #define regCB_BLEND2_CONTROL 0x01e2 5811f33ac92fSHawking Zhang #define regCB_BLEND2_CONTROL_BASE_IDX 1 5812f33ac92fSHawking Zhang #define regCB_BLEND3_CONTROL 0x01e3 5813f33ac92fSHawking Zhang #define regCB_BLEND3_CONTROL_BASE_IDX 1 5814f33ac92fSHawking Zhang #define regCB_BLEND4_CONTROL 0x01e4 5815f33ac92fSHawking Zhang #define regCB_BLEND4_CONTROL_BASE_IDX 1 5816f33ac92fSHawking Zhang #define regCB_BLEND5_CONTROL 0x01e5 5817f33ac92fSHawking Zhang #define regCB_BLEND5_CONTROL_BASE_IDX 1 5818f33ac92fSHawking Zhang #define regCB_BLEND6_CONTROL 0x01e6 5819f33ac92fSHawking Zhang #define regCB_BLEND6_CONTROL_BASE_IDX 1 5820f33ac92fSHawking Zhang #define regCB_BLEND7_CONTROL 0x01e7 5821f33ac92fSHawking Zhang #define regCB_BLEND7_CONTROL_BASE_IDX 1 5822f33ac92fSHawking Zhang #define regGFX_COPY_STATE 0x01f4 5823f33ac92fSHawking Zhang #define regGFX_COPY_STATE_BASE_IDX 1 5824f33ac92fSHawking Zhang #define regPA_CL_POINT_X_RAD 0x01f5 5825f33ac92fSHawking Zhang #define regPA_CL_POINT_X_RAD_BASE_IDX 1 5826f33ac92fSHawking Zhang #define regPA_CL_POINT_Y_RAD 0x01f6 5827f33ac92fSHawking Zhang #define regPA_CL_POINT_Y_RAD_BASE_IDX 1 5828f33ac92fSHawking Zhang #define regPA_CL_POINT_SIZE 0x01f7 5829f33ac92fSHawking Zhang #define regPA_CL_POINT_SIZE_BASE_IDX 1 5830f33ac92fSHawking Zhang #define regPA_CL_POINT_CULL_RAD 0x01f8 5831f33ac92fSHawking Zhang #define regPA_CL_POINT_CULL_RAD_BASE_IDX 1 5832f33ac92fSHawking Zhang #define regVGT_DMA_BASE_HI 0x01f9 5833f33ac92fSHawking Zhang #define regVGT_DMA_BASE_HI_BASE_IDX 1 5834f33ac92fSHawking Zhang #define regVGT_DMA_BASE 0x01fa 5835f33ac92fSHawking Zhang #define regVGT_DMA_BASE_BASE_IDX 1 5836f33ac92fSHawking Zhang #define regVGT_DRAW_INITIATOR 0x01fc 5837f33ac92fSHawking Zhang #define regVGT_DRAW_INITIATOR_BASE_IDX 1 5838f33ac92fSHawking Zhang #define regVGT_EVENT_ADDRESS_REG 0x01fe 5839f33ac92fSHawking Zhang #define regVGT_EVENT_ADDRESS_REG_BASE_IDX 1 5840f33ac92fSHawking Zhang #define regGE_MAX_OUTPUT_PER_SUBGROUP 0x01ff 5841f33ac92fSHawking Zhang #define regGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX 1 5842f33ac92fSHawking Zhang #define regDB_DEPTH_CONTROL 0x0200 5843f33ac92fSHawking Zhang #define regDB_DEPTH_CONTROL_BASE_IDX 1 5844f33ac92fSHawking Zhang #define regDB_EQAA 0x0201 5845f33ac92fSHawking Zhang #define regDB_EQAA_BASE_IDX 1 5846f33ac92fSHawking Zhang #define regCB_COLOR_CONTROL 0x0202 5847f33ac92fSHawking Zhang #define regCB_COLOR_CONTROL_BASE_IDX 1 5848f33ac92fSHawking Zhang #define regDB_SHADER_CONTROL 0x0203 5849f33ac92fSHawking Zhang #define regDB_SHADER_CONTROL_BASE_IDX 1 5850f33ac92fSHawking Zhang #define regPA_CL_CLIP_CNTL 0x0204 5851f33ac92fSHawking Zhang #define regPA_CL_CLIP_CNTL_BASE_IDX 1 5852f33ac92fSHawking Zhang #define regPA_SU_SC_MODE_CNTL 0x0205 5853f33ac92fSHawking Zhang #define regPA_SU_SC_MODE_CNTL_BASE_IDX 1 5854f33ac92fSHawking Zhang #define regPA_CL_VTE_CNTL 0x0206 5855f33ac92fSHawking Zhang #define regPA_CL_VTE_CNTL_BASE_IDX 1 5856f33ac92fSHawking Zhang #define regPA_CL_VS_OUT_CNTL 0x0207 5857f33ac92fSHawking Zhang #define regPA_CL_VS_OUT_CNTL_BASE_IDX 1 5858f33ac92fSHawking Zhang #define regPA_CL_NANINF_CNTL 0x0208 5859f33ac92fSHawking Zhang #define regPA_CL_NANINF_CNTL_BASE_IDX 1 5860f33ac92fSHawking Zhang #define regPA_SU_LINE_STIPPLE_CNTL 0x0209 5861f33ac92fSHawking Zhang #define regPA_SU_LINE_STIPPLE_CNTL_BASE_IDX 1 5862f33ac92fSHawking Zhang #define regPA_SU_LINE_STIPPLE_SCALE 0x020a 5863f33ac92fSHawking Zhang #define regPA_SU_LINE_STIPPLE_SCALE_BASE_IDX 1 5864f33ac92fSHawking Zhang #define regPA_SU_PRIM_FILTER_CNTL 0x020b 5865f33ac92fSHawking Zhang #define regPA_SU_PRIM_FILTER_CNTL_BASE_IDX 1 5866f33ac92fSHawking Zhang #define regPA_SU_SMALL_PRIM_FILTER_CNTL 0x020c 5867f33ac92fSHawking Zhang #define regPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX 1 5868f33ac92fSHawking Zhang #define regPA_CL_NGG_CNTL 0x020e 5869f33ac92fSHawking Zhang #define regPA_CL_NGG_CNTL_BASE_IDX 1 5870f33ac92fSHawking Zhang #define regPA_SU_OVER_RASTERIZATION_CNTL 0x020f 5871f33ac92fSHawking Zhang #define regPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX 1 5872f33ac92fSHawking Zhang #define regPA_STEREO_CNTL 0x0210 5873f33ac92fSHawking Zhang #define regPA_STEREO_CNTL_BASE_IDX 1 5874f33ac92fSHawking Zhang #define regPA_STATE_STEREO_X 0x0211 5875f33ac92fSHawking Zhang #define regPA_STATE_STEREO_X_BASE_IDX 1 5876f33ac92fSHawking Zhang #define regPA_CL_VRS_CNTL 0x0212 5877f33ac92fSHawking Zhang #define regPA_CL_VRS_CNTL_BASE_IDX 1 5878f33ac92fSHawking Zhang #define regPA_SU_POINT_SIZE 0x0280 5879f33ac92fSHawking Zhang #define regPA_SU_POINT_SIZE_BASE_IDX 1 5880f33ac92fSHawking Zhang #define regPA_SU_POINT_MINMAX 0x0281 5881f33ac92fSHawking Zhang #define regPA_SU_POINT_MINMAX_BASE_IDX 1 5882f33ac92fSHawking Zhang #define regPA_SU_LINE_CNTL 0x0282 5883f33ac92fSHawking Zhang #define regPA_SU_LINE_CNTL_BASE_IDX 1 5884f33ac92fSHawking Zhang #define regPA_SC_LINE_STIPPLE 0x0283 5885f33ac92fSHawking Zhang #define regPA_SC_LINE_STIPPLE_BASE_IDX 1 5886f33ac92fSHawking Zhang #define regVGT_HOS_MAX_TESS_LEVEL 0x0286 5887f33ac92fSHawking Zhang #define regVGT_HOS_MAX_TESS_LEVEL_BASE_IDX 1 5888f33ac92fSHawking Zhang #define regVGT_HOS_MIN_TESS_LEVEL 0x0287 5889f33ac92fSHawking Zhang #define regVGT_HOS_MIN_TESS_LEVEL_BASE_IDX 1 5890f33ac92fSHawking Zhang #define regPA_SC_MODE_CNTL_0 0x0292 5891f33ac92fSHawking Zhang #define regPA_SC_MODE_CNTL_0_BASE_IDX 1 5892f33ac92fSHawking Zhang #define regPA_SC_MODE_CNTL_1 0x0293 5893f33ac92fSHawking Zhang #define regPA_SC_MODE_CNTL_1_BASE_IDX 1 5894f33ac92fSHawking Zhang #define regVGT_ENHANCE 0x0294 5895f33ac92fSHawking Zhang #define regVGT_ENHANCE_BASE_IDX 1 5896f33ac92fSHawking Zhang #define regIA_ENHANCE 0x029c 5897f33ac92fSHawking Zhang #define regIA_ENHANCE_BASE_IDX 1 5898f33ac92fSHawking Zhang #define regVGT_DMA_SIZE 0x029d 5899f33ac92fSHawking Zhang #define regVGT_DMA_SIZE_BASE_IDX 1 5900f33ac92fSHawking Zhang #define regVGT_DMA_MAX_SIZE 0x029e 5901f33ac92fSHawking Zhang #define regVGT_DMA_MAX_SIZE_BASE_IDX 1 5902f33ac92fSHawking Zhang #define regVGT_DMA_INDEX_TYPE 0x029f 5903f33ac92fSHawking Zhang #define regVGT_DMA_INDEX_TYPE_BASE_IDX 1 5904f33ac92fSHawking Zhang #define regWD_ENHANCE 0x02a0 5905f33ac92fSHawking Zhang #define regWD_ENHANCE_BASE_IDX 1 5906f33ac92fSHawking Zhang #define regVGT_PRIMITIVEID_EN 0x02a1 5907f33ac92fSHawking Zhang #define regVGT_PRIMITIVEID_EN_BASE_IDX 1 5908f33ac92fSHawking Zhang #define regVGT_DMA_NUM_INSTANCES 0x02a2 5909f33ac92fSHawking Zhang #define regVGT_DMA_NUM_INSTANCES_BASE_IDX 1 5910f33ac92fSHawking Zhang #define regVGT_PRIMITIVEID_RESET 0x02a3 5911f33ac92fSHawking Zhang #define regVGT_PRIMITIVEID_RESET_BASE_IDX 1 5912f33ac92fSHawking Zhang #define regVGT_EVENT_INITIATOR 0x02a4 5913f33ac92fSHawking Zhang #define regVGT_EVENT_INITIATOR_BASE_IDX 1 5914f33ac92fSHawking Zhang #define regVGT_DRAW_PAYLOAD_CNTL 0x02a6 5915f33ac92fSHawking Zhang #define regVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1 5916f33ac92fSHawking Zhang #define regVGT_ESGS_RING_ITEMSIZE 0x02ab 5917f33ac92fSHawking Zhang #define regVGT_ESGS_RING_ITEMSIZE_BASE_IDX 1 5918f33ac92fSHawking Zhang #define regVGT_REUSE_OFF 0x02ad 5919f33ac92fSHawking Zhang #define regVGT_REUSE_OFF_BASE_IDX 1 5920f33ac92fSHawking Zhang #define regDB_HTILE_SURFACE 0x02af 5921f33ac92fSHawking Zhang #define regDB_HTILE_SURFACE_BASE_IDX 1 5922f33ac92fSHawking Zhang #define regDB_SRESULTS_COMPARE_STATE0 0x02b0 5923f33ac92fSHawking Zhang #define regDB_SRESULTS_COMPARE_STATE0_BASE_IDX 1 5924f33ac92fSHawking Zhang #define regDB_SRESULTS_COMPARE_STATE1 0x02b1 5925f33ac92fSHawking Zhang #define regDB_SRESULTS_COMPARE_STATE1_BASE_IDX 1 5926f33ac92fSHawking Zhang #define regDB_PRELOAD_CONTROL 0x02b2 5927f33ac92fSHawking Zhang #define regDB_PRELOAD_CONTROL_BASE_IDX 1 5928f33ac92fSHawking Zhang #define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0x02ca 5929f33ac92fSHawking Zhang #define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX 1 5930f33ac92fSHawking Zhang #define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0x02cb 5931f33ac92fSHawking Zhang #define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX 1 5932f33ac92fSHawking Zhang #define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0x02cc 5933f33ac92fSHawking Zhang #define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX 1 5934f33ac92fSHawking Zhang #define regVGT_GS_MAX_VERT_OUT 0x02ce 5935f33ac92fSHawking Zhang #define regVGT_GS_MAX_VERT_OUT_BASE_IDX 1 5936f33ac92fSHawking Zhang #define regGE_NGG_SUBGRP_CNTL 0x02d3 5937f33ac92fSHawking Zhang #define regGE_NGG_SUBGRP_CNTL_BASE_IDX 1 5938f33ac92fSHawking Zhang #define regVGT_TESS_DISTRIBUTION 0x02d4 5939f33ac92fSHawking Zhang #define regVGT_TESS_DISTRIBUTION_BASE_IDX 1 5940f33ac92fSHawking Zhang #define regVGT_SHADER_STAGES_EN 0x02d5 5941f33ac92fSHawking Zhang #define regVGT_SHADER_STAGES_EN_BASE_IDX 1 5942f33ac92fSHawking Zhang #define regVGT_LS_HS_CONFIG 0x02d6 5943f33ac92fSHawking Zhang #define regVGT_LS_HS_CONFIG_BASE_IDX 1 5944f33ac92fSHawking Zhang #define regVGT_TF_PARAM 0x02db 5945f33ac92fSHawking Zhang #define regVGT_TF_PARAM_BASE_IDX 1 5946f33ac92fSHawking Zhang #define regDB_ALPHA_TO_MASK 0x02dc 5947f33ac92fSHawking Zhang #define regDB_ALPHA_TO_MASK_BASE_IDX 1 5948f33ac92fSHawking Zhang #define regPA_SU_POLY_OFFSET_DB_FMT_CNTL 0x02de 5949f33ac92fSHawking Zhang #define regPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX 1 5950f33ac92fSHawking Zhang #define regPA_SU_POLY_OFFSET_CLAMP 0x02df 5951f33ac92fSHawking Zhang #define regPA_SU_POLY_OFFSET_CLAMP_BASE_IDX 1 5952f33ac92fSHawking Zhang #define regPA_SU_POLY_OFFSET_FRONT_SCALE 0x02e0 5953f33ac92fSHawking Zhang #define regPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX 1 5954f33ac92fSHawking Zhang #define regPA_SU_POLY_OFFSET_FRONT_OFFSET 0x02e1 5955f33ac92fSHawking Zhang #define regPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX 1 5956f33ac92fSHawking Zhang #define regPA_SU_POLY_OFFSET_BACK_SCALE 0x02e2 5957f33ac92fSHawking Zhang #define regPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX 1 5958f33ac92fSHawking Zhang #define regPA_SU_POLY_OFFSET_BACK_OFFSET 0x02e3 5959f33ac92fSHawking Zhang #define regPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX 1 5960f33ac92fSHawking Zhang #define regVGT_GS_INSTANCE_CNT 0x02e4 5961f33ac92fSHawking Zhang #define regVGT_GS_INSTANCE_CNT_BASE_IDX 1 5962f33ac92fSHawking Zhang #define regPA_SC_CENTROID_PRIORITY_0 0x02f5 5963f33ac92fSHawking Zhang #define regPA_SC_CENTROID_PRIORITY_0_BASE_IDX 1 5964f33ac92fSHawking Zhang #define regPA_SC_CENTROID_PRIORITY_1 0x02f6 5965f33ac92fSHawking Zhang #define regPA_SC_CENTROID_PRIORITY_1_BASE_IDX 1 5966f33ac92fSHawking Zhang #define regPA_SC_LINE_CNTL 0x02f7 5967f33ac92fSHawking Zhang #define regPA_SC_LINE_CNTL_BASE_IDX 1 5968f33ac92fSHawking Zhang #define regPA_SC_AA_CONFIG 0x02f8 5969f33ac92fSHawking Zhang #define regPA_SC_AA_CONFIG_BASE_IDX 1 5970f33ac92fSHawking Zhang #define regPA_SU_VTX_CNTL 0x02f9 5971f33ac92fSHawking Zhang #define regPA_SU_VTX_CNTL_BASE_IDX 1 5972f33ac92fSHawking Zhang #define regPA_CL_GB_VERT_CLIP_ADJ 0x02fa 5973f33ac92fSHawking Zhang #define regPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX 1 5974f33ac92fSHawking Zhang #define regPA_CL_GB_VERT_DISC_ADJ 0x02fb 5975f33ac92fSHawking Zhang #define regPA_CL_GB_VERT_DISC_ADJ_BASE_IDX 1 5976f33ac92fSHawking Zhang #define regPA_CL_GB_HORZ_CLIP_ADJ 0x02fc 5977f33ac92fSHawking Zhang #define regPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX 1 5978f33ac92fSHawking Zhang #define regPA_CL_GB_HORZ_DISC_ADJ 0x02fd 5979f33ac92fSHawking Zhang #define regPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX 1 5980f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x02fe 5981f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX 1 5982f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0x02ff 5983f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX 1 5984f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0x0300 5985f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX 1 5986f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0x0301 5987f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX 1 5988f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x0302 5989f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX 1 5990f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0x0303 5991f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX 1 5992f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0x0304 5993f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX 1 5994f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0x0305 5995f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX 1 5996f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x0306 5997f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX 1 5998f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0x0307 5999f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX 1 6000f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0x0308 6001f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX 1 6002f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0x0309 6003f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX 1 6004f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x030a 6005f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX 1 6006f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0x030b 6007f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX 1 6008f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0x030c 6009f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX 1 6010f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0x030d 6011f33ac92fSHawking Zhang #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX 1 6012f33ac92fSHawking Zhang #define regPA_SC_AA_MASK_X0Y0_X1Y0 0x030e 6013f33ac92fSHawking Zhang #define regPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX 1 6014f33ac92fSHawking Zhang #define regPA_SC_AA_MASK_X0Y1_X1Y1 0x030f 6015f33ac92fSHawking Zhang #define regPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX 1 6016f33ac92fSHawking Zhang #define regPA_SC_SHADER_CONTROL 0x0310 6017f33ac92fSHawking Zhang #define regPA_SC_SHADER_CONTROL_BASE_IDX 1 6018f33ac92fSHawking Zhang #define regPA_SC_BINNER_CNTL_0 0x0311 6019f33ac92fSHawking Zhang #define regPA_SC_BINNER_CNTL_0_BASE_IDX 1 6020f33ac92fSHawking Zhang #define regPA_SC_BINNER_CNTL_1 0x0312 6021f33ac92fSHawking Zhang #define regPA_SC_BINNER_CNTL_1_BASE_IDX 1 6022f33ac92fSHawking Zhang #define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL 0x0313 6023f33ac92fSHawking Zhang #define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX 1 6024f33ac92fSHawking Zhang #define regPA_SC_NGG_MODE_CNTL 0x0314 6025f33ac92fSHawking Zhang #define regPA_SC_NGG_MODE_CNTL_BASE_IDX 1 6026f33ac92fSHawking Zhang #define regPA_SC_BINNER_CNTL_2 0x0315 6027f33ac92fSHawking Zhang #define regPA_SC_BINNER_CNTL_2_BASE_IDX 1 6028f33ac92fSHawking Zhang #define regCB_COLOR0_BASE 0x0318 6029f33ac92fSHawking Zhang #define regCB_COLOR0_BASE_BASE_IDX 1 6030f33ac92fSHawking Zhang #define regCB_COLOR0_VIEW 0x031b 6031f33ac92fSHawking Zhang #define regCB_COLOR0_VIEW_BASE_IDX 1 6032f33ac92fSHawking Zhang #define regCB_COLOR0_INFO 0x031c 6033f33ac92fSHawking Zhang #define regCB_COLOR0_INFO_BASE_IDX 1 6034f33ac92fSHawking Zhang #define regCB_COLOR0_ATTRIB 0x031d 6035f33ac92fSHawking Zhang #define regCB_COLOR0_ATTRIB_BASE_IDX 1 6036f33ac92fSHawking Zhang #define regCB_COLOR0_FDCC_CONTROL 0x031e 6037f33ac92fSHawking Zhang #define regCB_COLOR0_FDCC_CONTROL_BASE_IDX 1 6038f33ac92fSHawking Zhang #define regCB_COLOR0_DCC_BASE 0x0325 6039f33ac92fSHawking Zhang #define regCB_COLOR0_DCC_BASE_BASE_IDX 1 6040f33ac92fSHawking Zhang #define regCB_COLOR1_BASE 0x0327 6041f33ac92fSHawking Zhang #define regCB_COLOR1_BASE_BASE_IDX 1 6042f33ac92fSHawking Zhang #define regCB_COLOR1_VIEW 0x032a 6043f33ac92fSHawking Zhang #define regCB_COLOR1_VIEW_BASE_IDX 1 6044f33ac92fSHawking Zhang #define regCB_COLOR1_INFO 0x032b 6045f33ac92fSHawking Zhang #define regCB_COLOR1_INFO_BASE_IDX 1 6046f33ac92fSHawking Zhang #define regCB_COLOR1_ATTRIB 0x032c 6047f33ac92fSHawking Zhang #define regCB_COLOR1_ATTRIB_BASE_IDX 1 6048f33ac92fSHawking Zhang #define regCB_COLOR1_FDCC_CONTROL 0x032d 6049f33ac92fSHawking Zhang #define regCB_COLOR1_FDCC_CONTROL_BASE_IDX 1 6050f33ac92fSHawking Zhang #define regCB_COLOR1_DCC_BASE 0x0334 6051f33ac92fSHawking Zhang #define regCB_COLOR1_DCC_BASE_BASE_IDX 1 6052f33ac92fSHawking Zhang #define regCB_COLOR2_BASE 0x0336 6053f33ac92fSHawking Zhang #define regCB_COLOR2_BASE_BASE_IDX 1 6054f33ac92fSHawking Zhang #define regCB_COLOR2_VIEW 0x0339 6055f33ac92fSHawking Zhang #define regCB_COLOR2_VIEW_BASE_IDX 1 6056f33ac92fSHawking Zhang #define regCB_COLOR2_INFO 0x033a 6057f33ac92fSHawking Zhang #define regCB_COLOR2_INFO_BASE_IDX 1 6058f33ac92fSHawking Zhang #define regCB_COLOR2_ATTRIB 0x033b 6059f33ac92fSHawking Zhang #define regCB_COLOR2_ATTRIB_BASE_IDX 1 6060f33ac92fSHawking Zhang #define regCB_COLOR2_FDCC_CONTROL 0x033c 6061f33ac92fSHawking Zhang #define regCB_COLOR2_FDCC_CONTROL_BASE_IDX 1 6062f33ac92fSHawking Zhang #define regCB_COLOR2_DCC_BASE 0x0343 6063f33ac92fSHawking Zhang #define regCB_COLOR2_DCC_BASE_BASE_IDX 1 6064f33ac92fSHawking Zhang #define regCB_COLOR3_BASE 0x0345 6065f33ac92fSHawking Zhang #define regCB_COLOR3_BASE_BASE_IDX 1 6066f33ac92fSHawking Zhang #define regCB_COLOR3_VIEW 0x0348 6067f33ac92fSHawking Zhang #define regCB_COLOR3_VIEW_BASE_IDX 1 6068f33ac92fSHawking Zhang #define regCB_COLOR3_INFO 0x0349 6069f33ac92fSHawking Zhang #define regCB_COLOR3_INFO_BASE_IDX 1 6070f33ac92fSHawking Zhang #define regCB_COLOR3_ATTRIB 0x034a 6071f33ac92fSHawking Zhang #define regCB_COLOR3_ATTRIB_BASE_IDX 1 6072f33ac92fSHawking Zhang #define regCB_COLOR3_FDCC_CONTROL 0x034b 6073f33ac92fSHawking Zhang #define regCB_COLOR3_FDCC_CONTROL_BASE_IDX 1 6074f33ac92fSHawking Zhang #define regCB_COLOR3_DCC_BASE 0x0352 6075f33ac92fSHawking Zhang #define regCB_COLOR3_DCC_BASE_BASE_IDX 1 6076f33ac92fSHawking Zhang #define regCB_COLOR4_BASE 0x0354 6077f33ac92fSHawking Zhang #define regCB_COLOR4_BASE_BASE_IDX 1 6078f33ac92fSHawking Zhang #define regCB_COLOR4_VIEW 0x0357 6079f33ac92fSHawking Zhang #define regCB_COLOR4_VIEW_BASE_IDX 1 6080f33ac92fSHawking Zhang #define regCB_COLOR4_INFO 0x0358 6081f33ac92fSHawking Zhang #define regCB_COLOR4_INFO_BASE_IDX 1 6082f33ac92fSHawking Zhang #define regCB_COLOR4_ATTRIB 0x0359 6083f33ac92fSHawking Zhang #define regCB_COLOR4_ATTRIB_BASE_IDX 1 6084f33ac92fSHawking Zhang #define regCB_COLOR4_FDCC_CONTROL 0x035a 6085f33ac92fSHawking Zhang #define regCB_COLOR4_FDCC_CONTROL_BASE_IDX 1 6086f33ac92fSHawking Zhang #define regCB_COLOR4_DCC_BASE 0x0361 6087f33ac92fSHawking Zhang #define regCB_COLOR4_DCC_BASE_BASE_IDX 1 6088f33ac92fSHawking Zhang #define regCB_COLOR5_BASE 0x0363 6089f33ac92fSHawking Zhang #define regCB_COLOR5_BASE_BASE_IDX 1 6090f33ac92fSHawking Zhang #define regCB_COLOR5_VIEW 0x0366 6091f33ac92fSHawking Zhang #define regCB_COLOR5_VIEW_BASE_IDX 1 6092f33ac92fSHawking Zhang #define regCB_COLOR5_INFO 0x0367 6093f33ac92fSHawking Zhang #define regCB_COLOR5_INFO_BASE_IDX 1 6094f33ac92fSHawking Zhang #define regCB_COLOR5_ATTRIB 0x0368 6095f33ac92fSHawking Zhang #define regCB_COLOR5_ATTRIB_BASE_IDX 1 6096f33ac92fSHawking Zhang #define regCB_COLOR5_FDCC_CONTROL 0x0369 6097f33ac92fSHawking Zhang #define regCB_COLOR5_FDCC_CONTROL_BASE_IDX 1 6098f33ac92fSHawking Zhang #define regCB_COLOR5_DCC_BASE 0x0370 6099f33ac92fSHawking Zhang #define regCB_COLOR5_DCC_BASE_BASE_IDX 1 6100f33ac92fSHawking Zhang #define regCB_COLOR6_BASE 0x0372 6101f33ac92fSHawking Zhang #define regCB_COLOR6_BASE_BASE_IDX 1 6102f33ac92fSHawking Zhang #define regCB_COLOR6_VIEW 0x0375 6103f33ac92fSHawking Zhang #define regCB_COLOR6_VIEW_BASE_IDX 1 6104f33ac92fSHawking Zhang #define regCB_COLOR6_INFO 0x0376 6105f33ac92fSHawking Zhang #define regCB_COLOR6_INFO_BASE_IDX 1 6106f33ac92fSHawking Zhang #define regCB_COLOR6_ATTRIB 0x0377 6107f33ac92fSHawking Zhang #define regCB_COLOR6_ATTRIB_BASE_IDX 1 6108f33ac92fSHawking Zhang #define regCB_COLOR6_FDCC_CONTROL 0x0378 6109f33ac92fSHawking Zhang #define regCB_COLOR6_FDCC_CONTROL_BASE_IDX 1 6110f33ac92fSHawking Zhang #define regCB_COLOR6_DCC_BASE 0x037f 6111f33ac92fSHawking Zhang #define regCB_COLOR6_DCC_BASE_BASE_IDX 1 6112f33ac92fSHawking Zhang #define regCB_COLOR7_BASE 0x0381 6113f33ac92fSHawking Zhang #define regCB_COLOR7_BASE_BASE_IDX 1 6114f33ac92fSHawking Zhang #define regCB_COLOR7_VIEW 0x0384 6115f33ac92fSHawking Zhang #define regCB_COLOR7_VIEW_BASE_IDX 1 6116f33ac92fSHawking Zhang #define regCB_COLOR7_INFO 0x0385 6117f33ac92fSHawking Zhang #define regCB_COLOR7_INFO_BASE_IDX 1 6118f33ac92fSHawking Zhang #define regCB_COLOR7_ATTRIB 0x0386 6119f33ac92fSHawking Zhang #define regCB_COLOR7_ATTRIB_BASE_IDX 1 6120f33ac92fSHawking Zhang #define regCB_COLOR7_FDCC_CONTROL 0x0387 6121f33ac92fSHawking Zhang #define regCB_COLOR7_FDCC_CONTROL_BASE_IDX 1 6122f33ac92fSHawking Zhang #define regCB_COLOR7_DCC_BASE 0x038e 6123f33ac92fSHawking Zhang #define regCB_COLOR7_DCC_BASE_BASE_IDX 1 6124f33ac92fSHawking Zhang #define regCB_COLOR0_BASE_EXT 0x0390 6125f33ac92fSHawking Zhang #define regCB_COLOR0_BASE_EXT_BASE_IDX 1 6126f33ac92fSHawking Zhang #define regCB_COLOR1_BASE_EXT 0x0391 6127f33ac92fSHawking Zhang #define regCB_COLOR1_BASE_EXT_BASE_IDX 1 6128f33ac92fSHawking Zhang #define regCB_COLOR2_BASE_EXT 0x0392 6129f33ac92fSHawking Zhang #define regCB_COLOR2_BASE_EXT_BASE_IDX 1 6130f33ac92fSHawking Zhang #define regCB_COLOR3_BASE_EXT 0x0393 6131f33ac92fSHawking Zhang #define regCB_COLOR3_BASE_EXT_BASE_IDX 1 6132f33ac92fSHawking Zhang #define regCB_COLOR4_BASE_EXT 0x0394 6133f33ac92fSHawking Zhang #define regCB_COLOR4_BASE_EXT_BASE_IDX 1 6134f33ac92fSHawking Zhang #define regCB_COLOR5_BASE_EXT 0x0395 6135f33ac92fSHawking Zhang #define regCB_COLOR5_BASE_EXT_BASE_IDX 1 6136f33ac92fSHawking Zhang #define regCB_COLOR6_BASE_EXT 0x0396 6137f33ac92fSHawking Zhang #define regCB_COLOR6_BASE_EXT_BASE_IDX 1 6138f33ac92fSHawking Zhang #define regCB_COLOR7_BASE_EXT 0x0397 6139f33ac92fSHawking Zhang #define regCB_COLOR7_BASE_EXT_BASE_IDX 1 6140f33ac92fSHawking Zhang #define regCB_COLOR0_DCC_BASE_EXT 0x03a8 6141f33ac92fSHawking Zhang #define regCB_COLOR0_DCC_BASE_EXT_BASE_IDX 1 6142f33ac92fSHawking Zhang #define regCB_COLOR1_DCC_BASE_EXT 0x03a9 6143f33ac92fSHawking Zhang #define regCB_COLOR1_DCC_BASE_EXT_BASE_IDX 1 6144f33ac92fSHawking Zhang #define regCB_COLOR2_DCC_BASE_EXT 0x03aa 6145f33ac92fSHawking Zhang #define regCB_COLOR2_DCC_BASE_EXT_BASE_IDX 1 6146f33ac92fSHawking Zhang #define regCB_COLOR3_DCC_BASE_EXT 0x03ab 6147f33ac92fSHawking Zhang #define regCB_COLOR3_DCC_BASE_EXT_BASE_IDX 1 6148f33ac92fSHawking Zhang #define regCB_COLOR4_DCC_BASE_EXT 0x03ac 6149f33ac92fSHawking Zhang #define regCB_COLOR4_DCC_BASE_EXT_BASE_IDX 1 6150f33ac92fSHawking Zhang #define regCB_COLOR5_DCC_BASE_EXT 0x03ad 6151f33ac92fSHawking Zhang #define regCB_COLOR5_DCC_BASE_EXT_BASE_IDX 1 6152f33ac92fSHawking Zhang #define regCB_COLOR6_DCC_BASE_EXT 0x03ae 6153f33ac92fSHawking Zhang #define regCB_COLOR6_DCC_BASE_EXT_BASE_IDX 1 6154f33ac92fSHawking Zhang #define regCB_COLOR7_DCC_BASE_EXT 0x03af 6155f33ac92fSHawking Zhang #define regCB_COLOR7_DCC_BASE_EXT_BASE_IDX 1 6156f33ac92fSHawking Zhang #define regCB_COLOR0_ATTRIB2 0x03b0 6157f33ac92fSHawking Zhang #define regCB_COLOR0_ATTRIB2_BASE_IDX 1 6158f33ac92fSHawking Zhang #define regCB_COLOR1_ATTRIB2 0x03b1 6159f33ac92fSHawking Zhang #define regCB_COLOR1_ATTRIB2_BASE_IDX 1 6160f33ac92fSHawking Zhang #define regCB_COLOR2_ATTRIB2 0x03b2 6161f33ac92fSHawking Zhang #define regCB_COLOR2_ATTRIB2_BASE_IDX 1 6162f33ac92fSHawking Zhang #define regCB_COLOR3_ATTRIB2 0x03b3 6163f33ac92fSHawking Zhang #define regCB_COLOR3_ATTRIB2_BASE_IDX 1 6164f33ac92fSHawking Zhang #define regCB_COLOR4_ATTRIB2 0x03b4 6165f33ac92fSHawking Zhang #define regCB_COLOR4_ATTRIB2_BASE_IDX 1 6166f33ac92fSHawking Zhang #define regCB_COLOR5_ATTRIB2 0x03b5 6167f33ac92fSHawking Zhang #define regCB_COLOR5_ATTRIB2_BASE_IDX 1 6168f33ac92fSHawking Zhang #define regCB_COLOR6_ATTRIB2 0x03b6 6169f33ac92fSHawking Zhang #define regCB_COLOR6_ATTRIB2_BASE_IDX 1 6170f33ac92fSHawking Zhang #define regCB_COLOR7_ATTRIB2 0x03b7 6171f33ac92fSHawking Zhang #define regCB_COLOR7_ATTRIB2_BASE_IDX 1 6172f33ac92fSHawking Zhang #define regCB_COLOR0_ATTRIB3 0x03b8 6173f33ac92fSHawking Zhang #define regCB_COLOR0_ATTRIB3_BASE_IDX 1 6174f33ac92fSHawking Zhang #define regCB_COLOR1_ATTRIB3 0x03b9 6175f33ac92fSHawking Zhang #define regCB_COLOR1_ATTRIB3_BASE_IDX 1 6176f33ac92fSHawking Zhang #define regCB_COLOR2_ATTRIB3 0x03ba 6177f33ac92fSHawking Zhang #define regCB_COLOR2_ATTRIB3_BASE_IDX 1 6178f33ac92fSHawking Zhang #define regCB_COLOR3_ATTRIB3 0x03bb 6179f33ac92fSHawking Zhang #define regCB_COLOR3_ATTRIB3_BASE_IDX 1 6180f33ac92fSHawking Zhang #define regCB_COLOR4_ATTRIB3 0x03bc 6181f33ac92fSHawking Zhang #define regCB_COLOR4_ATTRIB3_BASE_IDX 1 6182f33ac92fSHawking Zhang #define regCB_COLOR5_ATTRIB3 0x03bd 6183f33ac92fSHawking Zhang #define regCB_COLOR5_ATTRIB3_BASE_IDX 1 6184f33ac92fSHawking Zhang #define regCB_COLOR6_ATTRIB3 0x03be 6185f33ac92fSHawking Zhang #define regCB_COLOR6_ATTRIB3_BASE_IDX 1 6186f33ac92fSHawking Zhang #define regCB_COLOR7_ATTRIB3 0x03bf 6187f33ac92fSHawking Zhang #define regCB_COLOR7_ATTRIB3_BASE_IDX 1 6188f33ac92fSHawking Zhang 6189f33ac92fSHawking Zhang 6190f33ac92fSHawking Zhang // addressBlock: gc_pfvf_cpdec 6191f33ac92fSHawking Zhang // base address: 0x2a000 6192f33ac92fSHawking Zhang #define regCONFIG_RESERVED_REG0 0x0800 6193f33ac92fSHawking Zhang #define regCONFIG_RESERVED_REG0_BASE_IDX 1 6194f33ac92fSHawking Zhang #define regCONFIG_RESERVED_REG1 0x0801 6195f33ac92fSHawking Zhang #define regCONFIG_RESERVED_REG1_BASE_IDX 1 6196f33ac92fSHawking Zhang #define regCP_MEC_CNTL 0x0802 6197f33ac92fSHawking Zhang #define regCP_MEC_CNTL_BASE_IDX 1 6198f33ac92fSHawking Zhang #define regCP_ME_CNTL 0x0803 6199f33ac92fSHawking Zhang #define regCP_ME_CNTL_BASE_IDX 1 6200f33ac92fSHawking Zhang 6201f33ac92fSHawking Zhang 6202f33ac92fSHawking Zhang // addressBlock: gc_pfvf_grbmdec 6203f33ac92fSHawking Zhang // base address: 0x2a400 6204f33ac92fSHawking Zhang #define regGRBM_GFX_CNTL 0x0900 6205f33ac92fSHawking Zhang #define regGRBM_GFX_CNTL_BASE_IDX 1 6206f33ac92fSHawking Zhang #define regGRBM_NOWHERE 0x0901 6207f33ac92fSHawking Zhang #define regGRBM_NOWHERE_BASE_IDX 1 6208f33ac92fSHawking Zhang 6209f33ac92fSHawking Zhang 6210f33ac92fSHawking Zhang // addressBlock: gc_pfvf_padec 6211f33ac92fSHawking Zhang // base address: 0x2a500 6212f33ac92fSHawking Zhang #define regPA_SC_VRS_SURFACE_CNTL 0x0940 6213f33ac92fSHawking Zhang #define regPA_SC_VRS_SURFACE_CNTL_BASE_IDX 1 6214f33ac92fSHawking Zhang #define regPA_SC_ENHANCE 0x0941 6215f33ac92fSHawking Zhang #define regPA_SC_ENHANCE_BASE_IDX 1 6216f33ac92fSHawking Zhang #define regPA_SC_ENHANCE_1 0x0942 6217f33ac92fSHawking Zhang #define regPA_SC_ENHANCE_1_BASE_IDX 1 6218f33ac92fSHawking Zhang #define regPA_SC_ENHANCE_2 0x0943 6219f33ac92fSHawking Zhang #define regPA_SC_ENHANCE_2_BASE_IDX 1 6220f33ac92fSHawking Zhang #define regPA_SC_ENHANCE_3 0x0944 6221f33ac92fSHawking Zhang #define regPA_SC_ENHANCE_3_BASE_IDX 1 6222f33ac92fSHawking Zhang #define regPA_SC_BINNER_CNTL_OVERRIDE 0x0946 6223f33ac92fSHawking Zhang #define regPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX 1 6224f33ac92fSHawking Zhang #define regPA_SC_PBB_OVERRIDE_FLAG 0x0947 6225f33ac92fSHawking Zhang #define regPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX 1 6226f33ac92fSHawking Zhang #define regPA_SC_DSM_CNTL 0x0948 6227f33ac92fSHawking Zhang #define regPA_SC_DSM_CNTL_BASE_IDX 1 6228f33ac92fSHawking Zhang #define regPA_SC_TILE_STEERING_CREST_OVERRIDE 0x0949 6229f33ac92fSHawking Zhang #define regPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX 1 6230f33ac92fSHawking Zhang #define regPA_SC_FIFO_SIZE 0x094a 6231f33ac92fSHawking Zhang #define regPA_SC_FIFO_SIZE_BASE_IDX 1 6232f33ac92fSHawking Zhang #define regPA_SC_IF_FIFO_SIZE 0x094b 6233f33ac92fSHawking Zhang #define regPA_SC_IF_FIFO_SIZE_BASE_IDX 1 6234f33ac92fSHawking Zhang #define regPA_SC_PACKER_WAVE_ID_CNTL 0x094c 6235f33ac92fSHawking Zhang #define regPA_SC_PACKER_WAVE_ID_CNTL_BASE_IDX 1 6236f33ac92fSHawking Zhang #define regPA_SC_ATM_CNTL 0x094d 6237f33ac92fSHawking Zhang #define regPA_SC_ATM_CNTL_BASE_IDX 1 6238f33ac92fSHawking Zhang #define regPA_SC_PKR_WAVE_TABLE_CNTL 0x094e 6239f33ac92fSHawking Zhang #define regPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX 1 6240f33ac92fSHawking Zhang #define regPA_SC_FORCE_EOV_MAX_CNTS 0x094f 6241f33ac92fSHawking Zhang #define regPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX 1 6242f33ac92fSHawking Zhang #define regPA_SC_BINNER_EVENT_CNTL_0 0x0950 6243f33ac92fSHawking Zhang #define regPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX 1 6244f33ac92fSHawking Zhang #define regPA_SC_BINNER_EVENT_CNTL_1 0x0951 6245f33ac92fSHawking Zhang #define regPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX 1 6246f33ac92fSHawking Zhang #define regPA_SC_BINNER_EVENT_CNTL_2 0x0952 6247f33ac92fSHawking Zhang #define regPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX 1 6248f33ac92fSHawking Zhang #define regPA_SC_BINNER_EVENT_CNTL_3 0x0953 6249f33ac92fSHawking Zhang #define regPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX 1 6250f33ac92fSHawking Zhang #define regPA_SC_BINNER_TIMEOUT_COUNTER 0x0954 6251f33ac92fSHawking Zhang #define regPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX 1 6252f33ac92fSHawking Zhang #define regPA_SC_BINNER_PERF_CNTL_0 0x0955 6253f33ac92fSHawking Zhang #define regPA_SC_BINNER_PERF_CNTL_0_BASE_IDX 1 6254f33ac92fSHawking Zhang #define regPA_SC_BINNER_PERF_CNTL_1 0x0956 6255f33ac92fSHawking Zhang #define regPA_SC_BINNER_PERF_CNTL_1_BASE_IDX 1 6256f33ac92fSHawking Zhang #define regPA_SC_BINNER_PERF_CNTL_2 0x0957 6257f33ac92fSHawking Zhang #define regPA_SC_BINNER_PERF_CNTL_2_BASE_IDX 1 6258f33ac92fSHawking Zhang #define regPA_SC_BINNER_PERF_CNTL_3 0x0958 6259f33ac92fSHawking Zhang #define regPA_SC_BINNER_PERF_CNTL_3_BASE_IDX 1 6260f33ac92fSHawking Zhang #define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x095b 6261f33ac92fSHawking Zhang #define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 1 6262f33ac92fSHawking Zhang #define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x095c 6263f33ac92fSHawking Zhang #define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 1 6264f33ac92fSHawking Zhang #define regPA_SC_TRAP_SCREEN_HV_LOCK 0x095d 6265f33ac92fSHawking Zhang #define regPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX 1 6266f33ac92fSHawking Zhang #define regPA_PH_INTERFACE_FIFO_SIZE 0x095e 6267f33ac92fSHawking Zhang #define regPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX 1 6268f33ac92fSHawking Zhang #define regPA_PH_ENHANCE 0x095f 6269f33ac92fSHawking Zhang #define regPA_PH_ENHANCE_BASE_IDX 1 6270f33ac92fSHawking Zhang #define regPA_SC_VRS_SURFACE_CNTL_1 0x0960 6271f33ac92fSHawking Zhang #define regPA_SC_VRS_SURFACE_CNTL_1_BASE_IDX 1 6272f33ac92fSHawking Zhang 6273f33ac92fSHawking Zhang 6274f33ac92fSHawking Zhang // addressBlock: gc_pfvf_sqdec 6275f33ac92fSHawking Zhang // base address: 0x2a780 6276f33ac92fSHawking Zhang #define regSQ_RUNTIME_CONFIG 0x09e0 6277f33ac92fSHawking Zhang #define regSQ_RUNTIME_CONFIG_BASE_IDX 1 6278f33ac92fSHawking Zhang #define regSQ_DEBUG_STS_GLOBAL 0x09e1 6279f33ac92fSHawking Zhang #define regSQ_DEBUG_STS_GLOBAL_BASE_IDX 1 6280f33ac92fSHawking Zhang #define regSQ_DEBUG_STS_GLOBAL2 0x09e2 6281f33ac92fSHawking Zhang #define regSQ_DEBUG_STS_GLOBAL2_BASE_IDX 1 6282f33ac92fSHawking Zhang #define regSH_MEM_BASES 0x09e3 6283f33ac92fSHawking Zhang #define regSH_MEM_BASES_BASE_IDX 1 6284f33ac92fSHawking Zhang #define regSH_MEM_CONFIG 0x09e4 6285f33ac92fSHawking Zhang #define regSH_MEM_CONFIG_BASE_IDX 1 6286f33ac92fSHawking Zhang #define regSQ_DEBUG 0x09e5 6287f33ac92fSHawking Zhang #define regSQ_DEBUG_BASE_IDX 1 6288f33ac92fSHawking Zhang #define regSQ_SHADER_TBA_LO 0x09e6 6289f33ac92fSHawking Zhang #define regSQ_SHADER_TBA_LO_BASE_IDX 1 6290f33ac92fSHawking Zhang #define regSQ_SHADER_TBA_HI 0x09e7 6291f33ac92fSHawking Zhang #define regSQ_SHADER_TBA_HI_BASE_IDX 1 6292f33ac92fSHawking Zhang #define regSQ_SHADER_TMA_LO 0x09e8 6293f33ac92fSHawking Zhang #define regSQ_SHADER_TMA_LO_BASE_IDX 1 6294f33ac92fSHawking Zhang #define regSQ_SHADER_TMA_HI 0x09e9 6295f33ac92fSHawking Zhang #define regSQ_SHADER_TMA_HI_BASE_IDX 1 6296f33ac92fSHawking Zhang 6297f33ac92fSHawking Zhang 6298f33ac92fSHawking Zhang // addressBlock: gc_pfonly_cpdec 6299f33ac92fSHawking Zhang // base address: 0x2e000 6300f33ac92fSHawking Zhang #define regCP_DEBUG_2 0x1800 6301f33ac92fSHawking Zhang #define regCP_DEBUG_2_BASE_IDX 1 6302f33ac92fSHawking Zhang #define regCP_FETCHER_SOURCE 0x1801 6303f33ac92fSHawking Zhang #define regCP_FETCHER_SOURCE_BASE_IDX 1 6304f33ac92fSHawking Zhang 6305f33ac92fSHawking Zhang 6306f33ac92fSHawking Zhang // addressBlock: gc_pfonly_cpphqddec 6307f33ac92fSHawking Zhang // base address: 0x2e080 6308f33ac92fSHawking Zhang #define regCP_HPD_MES_ROQ_OFFSETS 0x1821 6309f33ac92fSHawking Zhang #define regCP_HPD_MES_ROQ_OFFSETS_BASE_IDX 1 6310f33ac92fSHawking Zhang #define regCP_HPD_ROQ_OFFSETS 0x1821 6311f33ac92fSHawking Zhang #define regCP_HPD_ROQ_OFFSETS_BASE_IDX 1 6312f33ac92fSHawking Zhang #define regCP_HPD_STATUS0 0x1822 6313f33ac92fSHawking Zhang #define regCP_HPD_STATUS0_BASE_IDX 1 6314f33ac92fSHawking Zhang 6315f33ac92fSHawking Zhang 6316f33ac92fSHawking Zhang // addressBlock: gc_pfonly_didtdec 6317f33ac92fSHawking Zhang // base address: 0x2e400 6318f33ac92fSHawking Zhang #define regDIDT_INDEX_AUTO_INCR_EN 0x1900 6319f33ac92fSHawking Zhang #define regDIDT_INDEX_AUTO_INCR_EN_BASE_IDX 1 6320f33ac92fSHawking Zhang #define regDIDT_EDC_CTRL 0x1901 6321f33ac92fSHawking Zhang #define regDIDT_EDC_CTRL_BASE_IDX 1 6322f33ac92fSHawking Zhang #define regDIDT_EDC_THROTTLE_CTRL 0x1902 6323f33ac92fSHawking Zhang #define regDIDT_EDC_THROTTLE_CTRL_BASE_IDX 1 6324f33ac92fSHawking Zhang #define regDIDT_EDC_THRESHOLD 0x1903 6325f33ac92fSHawking Zhang #define regDIDT_EDC_THRESHOLD_BASE_IDX 1 6326f33ac92fSHawking Zhang #define regDIDT_EDC_STALL_PATTERN_1_2 0x1904 6327f33ac92fSHawking Zhang #define regDIDT_EDC_STALL_PATTERN_1_2_BASE_IDX 1 6328f33ac92fSHawking Zhang #define regDIDT_EDC_STALL_PATTERN_3_4 0x1905 6329f33ac92fSHawking Zhang #define regDIDT_EDC_STALL_PATTERN_3_4_BASE_IDX 1 6330f33ac92fSHawking Zhang #define regDIDT_EDC_STALL_PATTERN_5_6 0x1906 6331f33ac92fSHawking Zhang #define regDIDT_EDC_STALL_PATTERN_5_6_BASE_IDX 1 6332f33ac92fSHawking Zhang #define regDIDT_EDC_STALL_PATTERN_7 0x1907 6333f33ac92fSHawking Zhang #define regDIDT_EDC_STALL_PATTERN_7_BASE_IDX 1 6334f33ac92fSHawking Zhang #define regDIDT_EDC_STATUS 0x1908 6335f33ac92fSHawking Zhang #define regDIDT_EDC_STATUS_BASE_IDX 1 6336f33ac92fSHawking Zhang #define regDIDT_EDC_DYNAMIC_THRESHOLD_RO 0x1909 6337f33ac92fSHawking Zhang #define regDIDT_EDC_DYNAMIC_THRESHOLD_RO_BASE_IDX 1 6338f33ac92fSHawking Zhang #define regDIDT_EDC_OVERFLOW 0x190a 6339f33ac92fSHawking Zhang #define regDIDT_EDC_OVERFLOW_BASE_IDX 1 6340f33ac92fSHawking Zhang #define regDIDT_EDC_ROLLING_POWER_DELTA 0x190b 6341f33ac92fSHawking Zhang #define regDIDT_EDC_ROLLING_POWER_DELTA_BASE_IDX 1 6342f33ac92fSHawking Zhang #define regDIDT_IND_INDEX 0x190c 6343f33ac92fSHawking Zhang #define regDIDT_IND_INDEX_BASE_IDX 1 6344f33ac92fSHawking Zhang #define regDIDT_IND_DATA 0x190d 6345f33ac92fSHawking Zhang #define regDIDT_IND_DATA_BASE_IDX 1 6346f33ac92fSHawking Zhang 6347f33ac92fSHawking Zhang 6348f33ac92fSHawking Zhang // addressBlock: gc_pfonly_spidec 6349f33ac92fSHawking Zhang // base address: 0x2e500 6350f33ac92fSHawking Zhang #define regSPI_GDBG_WAVE_CNTL 0x1943 6351f33ac92fSHawking Zhang #define regSPI_GDBG_WAVE_CNTL_BASE_IDX 1 6352f33ac92fSHawking Zhang #define regSPI_GDBG_TRAP_CONFIG 0x1944 6353f33ac92fSHawking Zhang #define regSPI_GDBG_TRAP_CONFIG_BASE_IDX 1 6354f33ac92fSHawking Zhang #define regSPI_GDBG_WAVE_CNTL3 0x1945 6355f33ac92fSHawking Zhang #define regSPI_GDBG_WAVE_CNTL3_BASE_IDX 1 6356f33ac92fSHawking Zhang #define regSPI_ARB_CNTL_0 0x1949 6357f33ac92fSHawking Zhang #define regSPI_ARB_CNTL_0_BASE_IDX 1 6358f33ac92fSHawking Zhang #define regSPI_FEATURE_CTRL 0x194a 6359f33ac92fSHawking Zhang #define regSPI_FEATURE_CTRL_BASE_IDX 1 6360f33ac92fSHawking Zhang #define regSPI_SHADER_RSRC_LIMIT_CTRL 0x194b 6361f33ac92fSHawking Zhang #define regSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX 1 6362f33ac92fSHawking Zhang #define regSPI_COMPUTE_WF_CTX_SAVE_STATUS 0x194e 6363f33ac92fSHawking Zhang #define regSPI_COMPUTE_WF_CTX_SAVE_STATUS_BASE_IDX 1 6364f33ac92fSHawking Zhang 6365f33ac92fSHawking Zhang 6366f33ac92fSHawking Zhang // addressBlock: gc_pfonly_tcpdec 6367f33ac92fSHawking Zhang // base address: 0x2e680 6368f33ac92fSHawking Zhang #define regTCP_INVALIDATE 0x19a0 6369f33ac92fSHawking Zhang #define regTCP_INVALIDATE_BASE_IDX 1 6370f33ac92fSHawking Zhang #define regTCP_STATUS 0x19a1 6371f33ac92fSHawking Zhang #define regTCP_STATUS_BASE_IDX 1 6372*5ffd8c73SAlex Sierra #define regTCP_CNTL 0x19a2 6373*5ffd8c73SAlex Sierra #define regTCP_CNTL_BASE_IDX 1 6374f33ac92fSHawking Zhang #define regTCP_CNTL2 0x19a3 6375f33ac92fSHawking Zhang #define regTCP_CNTL2_BASE_IDX 1 6376f33ac92fSHawking Zhang #define regTCP_DEBUG_INDEX 0x19a5 6377f33ac92fSHawking Zhang #define regTCP_DEBUG_INDEX_BASE_IDX 1 6378f33ac92fSHawking Zhang #define regTCP_DEBUG_DATA 0x19a6 6379f33ac92fSHawking Zhang #define regTCP_DEBUG_DATA_BASE_IDX 1 6380f33ac92fSHawking Zhang 6381f33ac92fSHawking Zhang 6382f33ac92fSHawking Zhang // addressBlock: gc_pfonly_gdsdec 6383f33ac92fSHawking Zhang // base address: 0x2e6c0 6384f33ac92fSHawking Zhang #define regGDS_ENHANCE2 0x19b0 6385f33ac92fSHawking Zhang #define regGDS_ENHANCE2_BASE_IDX 1 6386f33ac92fSHawking Zhang #define regGDS_OA_CGPG_RESTORE 0x19b1 6387f33ac92fSHawking Zhang #define regGDS_OA_CGPG_RESTORE_BASE_IDX 1 6388f33ac92fSHawking Zhang 6389f33ac92fSHawking Zhang 6390f33ac92fSHawking Zhang // addressBlock: gc_pfonly_utcl1dec 6391f33ac92fSHawking Zhang // base address: 0x2e600 6392f33ac92fSHawking Zhang #define regUTCL1_CTRL_0 0x1980 6393f33ac92fSHawking Zhang #define regUTCL1_CTRL_0_BASE_IDX 1 6394f33ac92fSHawking Zhang #define regUTCL1_UTCL0_INVREQ_DISABLE 0x1984 6395f33ac92fSHawking Zhang #define regUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX 1 6396f33ac92fSHawking Zhang #define regUTCL1_CTRL_2 0x1985 6397f33ac92fSHawking Zhang #define regUTCL1_CTRL_2_BASE_IDX 1 6398f33ac92fSHawking Zhang #define regUTCL1_FIFO_SIZING 0x1986 6399f33ac92fSHawking Zhang #define regUTCL1_FIFO_SIZING_BASE_IDX 1 6400f33ac92fSHawking Zhang #define regGCRD_SA0_TARGETS_DISABLE 0x1987 6401f33ac92fSHawking Zhang #define regGCRD_SA0_TARGETS_DISABLE_BASE_IDX 1 6402f33ac92fSHawking Zhang #define regGCRD_SA1_TARGETS_DISABLE 0x1989 6403f33ac92fSHawking Zhang #define regGCRD_SA1_TARGETS_DISABLE_BASE_IDX 1 6404f33ac92fSHawking Zhang #define regGCRD_CREDIT_SAFE 0x198a 6405f33ac92fSHawking Zhang #define regGCRD_CREDIT_SAFE_BASE_IDX 1 6406f33ac92fSHawking Zhang 6407f33ac92fSHawking Zhang 6408f33ac92fSHawking Zhang // addressBlock: gc_pfonly_pmmdec 6409f33ac92fSHawking Zhang // base address: 0x2e640 6410f33ac92fSHawking Zhang #define regGCR_GENERAL_CNTL 0x1990 6411f33ac92fSHawking Zhang #define regGCR_GENERAL_CNTL_BASE_IDX 1 6412f33ac92fSHawking Zhang #define regGCR_CMD_STATUS 0x1992 6413f33ac92fSHawking Zhang #define regGCR_CMD_STATUS_BASE_IDX 1 6414f33ac92fSHawking Zhang #define regGCR_SPARE 0x1993 6415f33ac92fSHawking Zhang #define regGCR_SPARE_BASE_IDX 1 6416f33ac92fSHawking Zhang #define regPMM_CNTL2 0x1999 6417f33ac92fSHawking Zhang #define regPMM_CNTL2_BASE_IDX 1 6418f33ac92fSHawking Zhang 6419f33ac92fSHawking Zhang 6420f33ac92fSHawking Zhang // addressBlock: gc_sedcdec 6421f33ac92fSHawking Zhang // base address: 0x2eb00 6422f33ac92fSHawking Zhang #define regSEDC_GL1_GL2_OVERRIDES 0x1ac0 6423f33ac92fSHawking Zhang #define regSEDC_GL1_GL2_OVERRIDES_BASE_IDX 1 6424f33ac92fSHawking Zhang 6425f33ac92fSHawking Zhang 6426f33ac92fSHawking Zhang // addressBlock: gc_pfonly_gccacdec 6427f33ac92fSHawking Zhang // base address: 0x2eb40 6428f33ac92fSHawking Zhang #define regGC_CAC_CTRL_1 0x1ad0 6429f33ac92fSHawking Zhang #define regGC_CAC_CTRL_1_BASE_IDX 1 6430f33ac92fSHawking Zhang #define regGC_CAC_CTRL_2 0x1ad1 6431f33ac92fSHawking Zhang #define regGC_CAC_CTRL_2_BASE_IDX 1 6432f33ac92fSHawking Zhang #define regGC_CAC_AGGR_LOWER 0x1ad2 6433f33ac92fSHawking Zhang #define regGC_CAC_AGGR_LOWER_BASE_IDX 1 6434f33ac92fSHawking Zhang #define regGC_CAC_AGGR_UPPER 0x1ad3 6435f33ac92fSHawking Zhang #define regGC_CAC_AGGR_UPPER_BASE_IDX 1 6436f33ac92fSHawking Zhang #define regSE0_CAC_AGGR_LOWER 0x1ad4 6437f33ac92fSHawking Zhang #define regSE0_CAC_AGGR_LOWER_BASE_IDX 1 6438f33ac92fSHawking Zhang #define regSE0_CAC_AGGR_UPPER 0x1ad5 6439f33ac92fSHawking Zhang #define regSE0_CAC_AGGR_UPPER_BASE_IDX 1 6440f33ac92fSHawking Zhang #define regSE1_CAC_AGGR_LOWER 0x1ad6 6441f33ac92fSHawking Zhang #define regSE1_CAC_AGGR_LOWER_BASE_IDX 1 6442f33ac92fSHawking Zhang #define regSE1_CAC_AGGR_UPPER 0x1ad7 6443f33ac92fSHawking Zhang #define regSE1_CAC_AGGR_UPPER_BASE_IDX 1 6444f33ac92fSHawking Zhang #define regSE2_CAC_AGGR_LOWER 0x1ad8 6445f33ac92fSHawking Zhang #define regSE2_CAC_AGGR_LOWER_BASE_IDX 1 6446f33ac92fSHawking Zhang #define regSE2_CAC_AGGR_UPPER 0x1ad9 6447f33ac92fSHawking Zhang #define regSE2_CAC_AGGR_UPPER_BASE_IDX 1 6448f33ac92fSHawking Zhang #define regSE3_CAC_AGGR_LOWER 0x1ada 6449f33ac92fSHawking Zhang #define regSE3_CAC_AGGR_LOWER_BASE_IDX 1 6450f33ac92fSHawking Zhang #define regSE3_CAC_AGGR_UPPER 0x1adb 6451f33ac92fSHawking Zhang #define regSE3_CAC_AGGR_UPPER_BASE_IDX 1 6452f33ac92fSHawking Zhang #define regSE4_CAC_AGGR_LOWER 0x1adc 6453f33ac92fSHawking Zhang #define regSE4_CAC_AGGR_LOWER_BASE_IDX 1 6454f33ac92fSHawking Zhang #define regSE4_CAC_AGGR_UPPER 0x1add 6455f33ac92fSHawking Zhang #define regSE4_CAC_AGGR_UPPER_BASE_IDX 1 6456f33ac92fSHawking Zhang #define regSE5_CAC_AGGR_LOWER 0x1ade 6457f33ac92fSHawking Zhang #define regSE5_CAC_AGGR_LOWER_BASE_IDX 1 6458f33ac92fSHawking Zhang #define regSE5_CAC_AGGR_UPPER 0x1adf 6459f33ac92fSHawking Zhang #define regSE5_CAC_AGGR_UPPER_BASE_IDX 1 6460f33ac92fSHawking Zhang #define regGC_CAC_AGGR_GFXCLK_CYCLE 0x1ae4 6461f33ac92fSHawking Zhang #define regGC_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 6462f33ac92fSHawking Zhang #define regSE0_CAC_AGGR_GFXCLK_CYCLE 0x1ae5 6463f33ac92fSHawking Zhang #define regSE0_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 6464f33ac92fSHawking Zhang #define regSE1_CAC_AGGR_GFXCLK_CYCLE 0x1ae6 6465f33ac92fSHawking Zhang #define regSE1_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 6466f33ac92fSHawking Zhang #define regSE2_CAC_AGGR_GFXCLK_CYCLE 0x1ae7 6467f33ac92fSHawking Zhang #define regSE2_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 6468f33ac92fSHawking Zhang #define regSE3_CAC_AGGR_GFXCLK_CYCLE 0x1ae8 6469f33ac92fSHawking Zhang #define regSE3_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 6470f33ac92fSHawking Zhang #define regSE4_CAC_AGGR_GFXCLK_CYCLE 0x1ae9 6471f33ac92fSHawking Zhang #define regSE4_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 6472f33ac92fSHawking Zhang #define regSE5_CAC_AGGR_GFXCLK_CYCLE 0x1aea 6473f33ac92fSHawking Zhang #define regSE5_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 6474f33ac92fSHawking Zhang #define regGC_EDC_CTRL 0x1aed 6475f33ac92fSHawking Zhang #define regGC_EDC_CTRL_BASE_IDX 1 6476f33ac92fSHawking Zhang #define regGC_EDC_THRESHOLD 0x1aee 6477f33ac92fSHawking Zhang #define regGC_EDC_THRESHOLD_BASE_IDX 1 6478f33ac92fSHawking Zhang #define regGC_EDC_STRETCH_CTRL 0x1aef 6479f33ac92fSHawking Zhang #define regGC_EDC_STRETCH_CTRL_BASE_IDX 1 6480f33ac92fSHawking Zhang #define regGC_EDC_STRETCH_THRESHOLD 0x1af0 6481f33ac92fSHawking Zhang #define regGC_EDC_STRETCH_THRESHOLD_BASE_IDX 1 6482f33ac92fSHawking Zhang #define regEDC_HYSTERESIS_CNTL 0x1af1 6483f33ac92fSHawking Zhang #define regEDC_HYSTERESIS_CNTL_BASE_IDX 1 6484f33ac92fSHawking Zhang #define regGC_THROTTLE_CTRL 0x1af2 6485f33ac92fSHawking Zhang #define regGC_THROTTLE_CTRL_BASE_IDX 1 6486f33ac92fSHawking Zhang #define regGC_THROTTLE_CTRL1 0x1af3 6487f33ac92fSHawking Zhang #define regGC_THROTTLE_CTRL1_BASE_IDX 1 6488f33ac92fSHawking Zhang #define regPCC_STALL_PATTERN_CTRL 0x1af4 6489f33ac92fSHawking Zhang #define regPCC_STALL_PATTERN_CTRL_BASE_IDX 1 6490f33ac92fSHawking Zhang #define regPWRBRK_STALL_PATTERN_CTRL 0x1af5 6491f33ac92fSHawking Zhang #define regPWRBRK_STALL_PATTERN_CTRL_BASE_IDX 1 6492f33ac92fSHawking Zhang #define regPCC_STALL_PATTERN_1_2 0x1af6 6493f33ac92fSHawking Zhang #define regPCC_STALL_PATTERN_1_2_BASE_IDX 1 6494f33ac92fSHawking Zhang #define regPCC_STALL_PATTERN_3_4 0x1af7 6495f33ac92fSHawking Zhang #define regPCC_STALL_PATTERN_3_4_BASE_IDX 1 6496f33ac92fSHawking Zhang #define regPCC_STALL_PATTERN_5_6 0x1af8 6497f33ac92fSHawking Zhang #define regPCC_STALL_PATTERN_5_6_BASE_IDX 1 6498f33ac92fSHawking Zhang #define regPCC_STALL_PATTERN_7 0x1af9 6499f33ac92fSHawking Zhang #define regPCC_STALL_PATTERN_7_BASE_IDX 1 6500f33ac92fSHawking Zhang #define regPWRBRK_STALL_PATTERN_1_2 0x1afa 6501f33ac92fSHawking Zhang #define regPWRBRK_STALL_PATTERN_1_2_BASE_IDX 1 6502f33ac92fSHawking Zhang #define regPWRBRK_STALL_PATTERN_3_4 0x1afb 6503f33ac92fSHawking Zhang #define regPWRBRK_STALL_PATTERN_3_4_BASE_IDX 1 6504f33ac92fSHawking Zhang #define regPWRBRK_STALL_PATTERN_5_6 0x1afc 6505f33ac92fSHawking Zhang #define regPWRBRK_STALL_PATTERN_5_6_BASE_IDX 1 6506f33ac92fSHawking Zhang #define regPWRBRK_STALL_PATTERN_7 0x1afd 6507f33ac92fSHawking Zhang #define regPWRBRK_STALL_PATTERN_7_BASE_IDX 1 6508f33ac92fSHawking Zhang #define regDIDT_STALL_PATTERN_CTRL 0x1afe 6509f33ac92fSHawking Zhang #define regDIDT_STALL_PATTERN_CTRL_BASE_IDX 1 6510f33ac92fSHawking Zhang #define regDIDT_STALL_PATTERN_1_2 0x1aff 6511f33ac92fSHawking Zhang #define regDIDT_STALL_PATTERN_1_2_BASE_IDX 1 6512f33ac92fSHawking Zhang #define regDIDT_STALL_PATTERN_3_4 0x1b00 6513f33ac92fSHawking Zhang #define regDIDT_STALL_PATTERN_3_4_BASE_IDX 1 6514f33ac92fSHawking Zhang #define regDIDT_STALL_PATTERN_5_6 0x1b01 6515f33ac92fSHawking Zhang #define regDIDT_STALL_PATTERN_5_6_BASE_IDX 1 6516f33ac92fSHawking Zhang #define regDIDT_STALL_PATTERN_7 0x1b02 6517f33ac92fSHawking Zhang #define regDIDT_STALL_PATTERN_7_BASE_IDX 1 6518f33ac92fSHawking Zhang #define regPCC_PWRBRK_HYSTERESIS_CTRL 0x1b03 6519f33ac92fSHawking Zhang #define regPCC_PWRBRK_HYSTERESIS_CTRL_BASE_IDX 1 6520f33ac92fSHawking Zhang #define regEDC_STRETCH_PERF_COUNTER 0x1b04 6521f33ac92fSHawking Zhang #define regEDC_STRETCH_PERF_COUNTER_BASE_IDX 1 6522f33ac92fSHawking Zhang #define regEDC_UNSTRETCH_PERF_COUNTER 0x1b05 6523f33ac92fSHawking Zhang #define regEDC_UNSTRETCH_PERF_COUNTER_BASE_IDX 1 6524f33ac92fSHawking Zhang #define regEDC_STRETCH_NUM_PERF_COUNTER 0x1b06 6525f33ac92fSHawking Zhang #define regEDC_STRETCH_NUM_PERF_COUNTER_BASE_IDX 1 6526f33ac92fSHawking Zhang #define regGC_EDC_STATUS 0x1b07 6527f33ac92fSHawking Zhang #define regGC_EDC_STATUS_BASE_IDX 1 6528f33ac92fSHawking Zhang #define regGC_EDC_OVERFLOW 0x1b08 6529f33ac92fSHawking Zhang #define regGC_EDC_OVERFLOW_BASE_IDX 1 6530f33ac92fSHawking Zhang #define regGC_EDC_ROLLING_POWER_DELTA 0x1b09 6531f33ac92fSHawking Zhang #define regGC_EDC_ROLLING_POWER_DELTA_BASE_IDX 1 6532f33ac92fSHawking Zhang #define regGC_THROTTLE_STATUS 0x1b0a 6533f33ac92fSHawking Zhang #define regGC_THROTTLE_STATUS_BASE_IDX 1 6534f33ac92fSHawking Zhang #define regEDC_PERF_COUNTER 0x1b0b 6535f33ac92fSHawking Zhang #define regEDC_PERF_COUNTER_BASE_IDX 1 6536f33ac92fSHawking Zhang #define regPCC_PERF_COUNTER 0x1b0c 6537f33ac92fSHawking Zhang #define regPCC_PERF_COUNTER_BASE_IDX 1 6538f33ac92fSHawking Zhang #define regPWRBRK_PERF_COUNTER 0x1b0d 6539f33ac92fSHawking Zhang #define regPWRBRK_PERF_COUNTER_BASE_IDX 1 6540f33ac92fSHawking Zhang #define regEDC_HYSTERESIS_STAT 0x1b0e 6541f33ac92fSHawking Zhang #define regEDC_HYSTERESIS_STAT_BASE_IDX 1 6542f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_CP_0 0x1b10 6543f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_CP_0_BASE_IDX 1 6544f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_CP_1 0x1b11 6545f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_CP_1_BASE_IDX 1 6546f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_EA_0 0x1b12 6547f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_EA_0_BASE_IDX 1 6548f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_EA_1 0x1b13 6549f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_EA_1_BASE_IDX 1 6550f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_EA_2 0x1b14 6551f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_EA_2_BASE_IDX 1 6552f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_UTCL2_ROUTER_0 0x1b15 6553f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_UTCL2_ROUTER_0_BASE_IDX 1 6554f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_UTCL2_ROUTER_1 0x1b16 6555f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_UTCL2_ROUTER_1_BASE_IDX 1 6556f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_UTCL2_ROUTER_2 0x1b17 6557f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_UTCL2_ROUTER_2_BASE_IDX 1 6558f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_UTCL2_ROUTER_3 0x1b18 6559f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_UTCL2_ROUTER_3_BASE_IDX 1 6560f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_UTCL2_ROUTER_4 0x1b19 6561f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_UTCL2_ROUTER_4_BASE_IDX 1 6562f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_UTCL2_VML2_0 0x1b1a 6563f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_UTCL2_VML2_0_BASE_IDX 1 6564f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_UTCL2_VML2_1 0x1b1b 6565f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_UTCL2_VML2_1_BASE_IDX 1 6566f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_UTCL2_VML2_2 0x1b1c 6567f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_UTCL2_VML2_2_BASE_IDX 1 6568f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_UTCL2_WALKER_0 0x1b1d 6569f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_UTCL2_WALKER_0_BASE_IDX 1 6570f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_UTCL2_WALKER_1 0x1b1e 6571f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_UTCL2_WALKER_1_BASE_IDX 1 6572f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_UTCL2_WALKER_2 0x1b1f 6573f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_UTCL2_WALKER_2_BASE_IDX 1 6574f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GDS_0 0x1b20 6575f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GDS_0_BASE_IDX 1 6576f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GDS_1 0x1b21 6577f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GDS_1_BASE_IDX 1 6578f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GDS_2 0x1b22 6579f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GDS_2_BASE_IDX 1 6580f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GE_0 0x1b23 6581f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GE_0_BASE_IDX 1 6582f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GE_1 0x1b24 6583f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GE_1_BASE_IDX 1 6584f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GE_2 0x1b25 6585f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GE_2_BASE_IDX 1 6586f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GE_3 0x1b26 6587f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GE_3_BASE_IDX 1 6588f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GE_4 0x1b27 6589f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GE_4_BASE_IDX 1 6590f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GE_5 0x1b28 6591f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GE_5_BASE_IDX 1 6592f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GE_6 0x1b29 6593f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GE_6_BASE_IDX 1 6594f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_PMM_0 0x1b2e 6595f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_PMM_0_BASE_IDX 1 6596f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GL2C_0 0x1b2f 6597f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GL2C_0_BASE_IDX 1 6598f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GL2C_1 0x1b30 6599f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GL2C_1_BASE_IDX 1 6600f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GL2C_2 0x1b31 6601f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GL2C_2_BASE_IDX 1 6602f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_PH_0 0x1b32 6603f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_PH_0_BASE_IDX 1 6604f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_PH_1 0x1b33 6605f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_PH_1_BASE_IDX 1 6606f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_PH_2 0x1b34 6607f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_PH_2_BASE_IDX 1 6608f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_PH_3 0x1b35 6609f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_PH_3_BASE_IDX 1 6610f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_SDMA_0 0x1b36 6611f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_SDMA_0_BASE_IDX 1 6612f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_SDMA_1 0x1b37 6613f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_SDMA_1_BASE_IDX 1 6614f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_SDMA_2 0x1b38 6615f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_SDMA_2_BASE_IDX 1 6616f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_SDMA_3 0x1b39 6617f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_SDMA_3_BASE_IDX 1 6618f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_SDMA_4 0x1b3a 6619f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_SDMA_4_BASE_IDX 1 6620f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_SDMA_5 0x1b3b 6621f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_SDMA_5_BASE_IDX 1 6622f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_CHC_0 0x1b3c 6623f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_CHC_0_BASE_IDX 1 6624f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_CHC_1 0x1b3d 6625f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_CHC_1_BASE_IDX 1 6626f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GUS_0 0x1b3e 6627f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GUS_0_BASE_IDX 1 6628f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GUS_1 0x1b3f 6629f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GUS_1_BASE_IDX 1 6630f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_RLC_0 0x1b40 6631f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_RLC_0_BASE_IDX 1 6632f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GRBM_0 0x1b44 6633f33ac92fSHawking Zhang #define regGC_CAC_WEIGHT_GRBM_0_BASE_IDX 1 6634f33ac92fSHawking Zhang #define regGC_EDC_CLK_MONITOR_CTRL 0x1b56 6635f33ac92fSHawking Zhang #define regGC_EDC_CLK_MONITOR_CTRL_BASE_IDX 1 6636f33ac92fSHawking Zhang #define regGC_CAC_IND_INDEX 0x1b58 6637f33ac92fSHawking Zhang #define regGC_CAC_IND_INDEX_BASE_IDX 1 6638f33ac92fSHawking Zhang #define regGC_CAC_IND_DATA 0x1b59 6639f33ac92fSHawking Zhang #define regGC_CAC_IND_DATA_BASE_IDX 1 6640f33ac92fSHawking Zhang #define regSE_CAC_CTRL_1 0x1b70 6641f33ac92fSHawking Zhang #define regSE_CAC_CTRL_1_BASE_IDX 1 6642f33ac92fSHawking Zhang #define regSE_CAC_CTRL_2 0x1b71 6643f33ac92fSHawking Zhang #define regSE_CAC_CTRL_2_BASE_IDX 1 6644f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_TA_0 0x1b72 6645f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_TA_0_BASE_IDX 1 6646f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_TD_0 0x1b73 6647f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_TD_0_BASE_IDX 1 6648f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_TD_1 0x1b74 6649f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_TD_1_BASE_IDX 1 6650f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_TD_2 0x1b75 6651f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_TD_2_BASE_IDX 1 6652f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_TD_3 0x1b76 6653f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_TD_3_BASE_IDX 1 6654f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_TD_4 0x1b77 6655f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_TD_4_BASE_IDX 1 6656f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_TD_5 0x1b78 6657f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_TD_5_BASE_IDX 1 6658f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_TCP_0 0x1b79 6659f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_TCP_0_BASE_IDX 1 6660f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_TCP_1 0x1b7a 6661f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_TCP_1_BASE_IDX 1 6662f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_TCP_2 0x1b7b 6663f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_TCP_2_BASE_IDX 1 6664f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_TCP_3 0x1b7c 6665f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_TCP_3_BASE_IDX 1 6666f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SQ_0 0x1b7d 6667f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SQ_0_BASE_IDX 1 6668f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SQ_1 0x1b7e 6669f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SQ_1_BASE_IDX 1 6670f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SQ_2 0x1b7f 6671f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SQ_2_BASE_IDX 1 6672f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SP_0 0x1b80 6673f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SP_0_BASE_IDX 1 6674f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SP_1 0x1b81 6675f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SP_1_BASE_IDX 1 6676f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_LDS_0 0x1b82 6677f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_LDS_0_BASE_IDX 1 6678f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_LDS_1 0x1b83 6679f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_LDS_1_BASE_IDX 1 6680f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_LDS_2 0x1b84 6681f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_LDS_2_BASE_IDX 1 6682f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_LDS_3 0x1b85 6683f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_LDS_3_BASE_IDX 1 6684f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SQC_0 0x1b87 6685f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SQC_0_BASE_IDX 1 6686f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SQC_1 0x1b88 6687f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SQC_1_BASE_IDX 1 6688f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_CU_0 0x1b89 6689f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_CU_0_BASE_IDX 1 6690f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_BCI_0 0x1b8a 6691f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_BCI_0_BASE_IDX 1 6692f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_CB_0 0x1b8b 6693f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_CB_0_BASE_IDX 1 6694f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_CB_1 0x1b8c 6695f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_CB_1_BASE_IDX 1 6696f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_CB_2 0x1b8d 6697f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_CB_2_BASE_IDX 1 6698f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_CB_3 0x1b8e 6699f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_CB_3_BASE_IDX 1 6700f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_CB_4 0x1b8f 6701f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_CB_4_BASE_IDX 1 6702f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_CB_5 0x1b90 6703f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_CB_5_BASE_IDX 1 6704f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_CB_6 0x1b91 6705f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_CB_6_BASE_IDX 1 6706f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_CB_7 0x1b92 6707f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_CB_7_BASE_IDX 1 6708f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_CB_8 0x1b93 6709f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_CB_8_BASE_IDX 1 6710f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_CB_9 0x1b94 6711f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_CB_9_BASE_IDX 1 6712f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_CB_10 0x1b95 6713f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_CB_10_BASE_IDX 1 6714f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_CB_11 0x1b96 6715f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_CB_11_BASE_IDX 1 6716f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_DB_0 0x1b97 6717f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_DB_0_BASE_IDX 1 6718f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_DB_1 0x1b98 6719f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_DB_1_BASE_IDX 1 6720f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_DB_2 0x1b99 6721f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_DB_2_BASE_IDX 1 6722f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_DB_3 0x1b9a 6723f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_DB_3_BASE_IDX 1 6724f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_DB_4 0x1b9b 6725f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_DB_4_BASE_IDX 1 6726f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_RMI_0 0x1b9c 6727f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_RMI_0_BASE_IDX 1 6728f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_RMI_1 0x1b9d 6729f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_RMI_1_BASE_IDX 1 6730f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SX_0 0x1b9e 6731f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SX_0_BASE_IDX 1 6732f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SXRB_0 0x1b9f 6733f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SXRB_0_BASE_IDX 1 6734f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_UTCL1_0 0x1ba0 6735f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_UTCL1_0_BASE_IDX 1 6736f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_GL1C_0 0x1ba1 6737f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_GL1C_0_BASE_IDX 1 6738f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_GL1C_1 0x1ba2 6739f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_GL1C_1_BASE_IDX 1 6740f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_GL1C_2 0x1ba3 6741f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_GL1C_2_BASE_IDX 1 6742f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SPI_0 0x1ba4 6743f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SPI_0_BASE_IDX 1 6744f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SPI_1 0x1ba5 6745f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SPI_1_BASE_IDX 1 6746f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SPI_2 0x1ba6 6747f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SPI_2_BASE_IDX 1 6748f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_PC_0 0x1ba7 6749f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_PC_0_BASE_IDX 1 6750f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_PA_0 0x1ba8 6751f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_PA_0_BASE_IDX 1 6752f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_PA_1 0x1ba9 6753f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_PA_1_BASE_IDX 1 6754f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_PA_2 0x1baa 6755f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_PA_2_BASE_IDX 1 6756f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_PA_3 0x1bab 6757f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_PA_3_BASE_IDX 1 6758f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SC_0 0x1bac 6759f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SC_0_BASE_IDX 1 6760f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SC_1 0x1bad 6761f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SC_1_BASE_IDX 1 6762f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SC_2 0x1bae 6763f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SC_2_BASE_IDX 1 6764f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SC_3 0x1baf 6765f33ac92fSHawking Zhang #define regSE_CAC_WEIGHT_SC_3_BASE_IDX 1 6766f33ac92fSHawking Zhang #define regSE_CAC_WINDOW_AGGR_VALUE 0x1bb0 6767f33ac92fSHawking Zhang #define regSE_CAC_WINDOW_AGGR_VALUE_BASE_IDX 1 6768f33ac92fSHawking Zhang #define regSE_CAC_WINDOW_GFXCLK_CYCLE 0x1bb1 6769f33ac92fSHawking Zhang #define regSE_CAC_WINDOW_GFXCLK_CYCLE_BASE_IDX 1 6770f33ac92fSHawking Zhang #define regSE_CAC_IND_INDEX 0x1bce 6771f33ac92fSHawking Zhang #define regSE_CAC_IND_INDEX_BASE_IDX 1 6772f33ac92fSHawking Zhang #define regSE_CAC_IND_DATA 0x1bcf 6773f33ac92fSHawking Zhang #define regSE_CAC_IND_DATA_BASE_IDX 1 6774f33ac92fSHawking Zhang 6775f33ac92fSHawking Zhang 6776f33ac92fSHawking Zhang // addressBlock: gc_pfonly2_spidec 6777f33ac92fSHawking Zhang // base address: 0x2f000 6778f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_0 0x1c00 6779f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_0_BASE_IDX 1 6780f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_1 0x1c01 6781f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_1_BASE_IDX 1 6782f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_2 0x1c02 6783f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_2_BASE_IDX 1 6784f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_3 0x1c03 6785f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_3_BASE_IDX 1 6786f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_4 0x1c04 6787f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_4_BASE_IDX 1 6788f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_5 0x1c05 6789f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_5_BASE_IDX 1 6790f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_6 0x1c06 6791f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_6_BASE_IDX 1 6792f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_7 0x1c07 6793f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_7_BASE_IDX 1 6794f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_8 0x1c08 6795f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_8_BASE_IDX 1 6796f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_9 0x1c09 6797f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_9_BASE_IDX 1 6798f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_10 0x1c0a 6799f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_10_BASE_IDX 1 6800f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_11 0x1c0b 6801f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_11_BASE_IDX 1 6802f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_12 0x1c0c 6803f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_12_BASE_IDX 1 6804f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_13 0x1c0d 6805f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_13_BASE_IDX 1 6806f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_14 0x1c0e 6807f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_14_BASE_IDX 1 6808f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_15 0x1c0f 6809f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_CU_15_BASE_IDX 1 6810f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_0 0x1c10 6811f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX 1 6812f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_1 0x1c11 6813f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX 1 6814f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_2 0x1c12 6815f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX 1 6816f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_3 0x1c13 6817f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX 1 6818f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_4 0x1c14 6819f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX 1 6820f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_5 0x1c15 6821f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX 1 6822f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_6 0x1c16 6823f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX 1 6824f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_7 0x1c17 6825f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX 1 6826f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_8 0x1c18 6827f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX 1 6828f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_9 0x1c19 6829f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX 1 6830f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_10 0x1c1a 6831f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX 1 6832f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_11 0x1c1b 6833f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX 1 6834f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_12 0x1c1c 6835f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX 1 6836f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_13 0x1c1d 6837f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX 1 6838f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_14 0x1c1e 6839f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX 1 6840f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_15 0x1c1f 6841f33ac92fSHawking Zhang #define regSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX 1 6842f33ac92fSHawking Zhang 6843f33ac92fSHawking Zhang 6844f33ac92fSHawking Zhang // addressBlock: gc_gfxudec 6845f33ac92fSHawking Zhang // base address: 0x30000 6846f33ac92fSHawking Zhang #define regCP_EOP_DONE_ADDR_LO 0x2000 6847f33ac92fSHawking Zhang #define regCP_EOP_DONE_ADDR_LO_BASE_IDX 1 6848f33ac92fSHawking Zhang #define regCP_EOP_DONE_ADDR_HI 0x2001 6849f33ac92fSHawking Zhang #define regCP_EOP_DONE_ADDR_HI_BASE_IDX 1 6850f33ac92fSHawking Zhang #define regCP_EOP_DONE_DATA_LO 0x2002 6851f33ac92fSHawking Zhang #define regCP_EOP_DONE_DATA_LO_BASE_IDX 1 6852f33ac92fSHawking Zhang #define regCP_EOP_DONE_DATA_HI 0x2003 6853f33ac92fSHawking Zhang #define regCP_EOP_DONE_DATA_HI_BASE_IDX 1 6854f33ac92fSHawking Zhang #define regCP_EOP_LAST_FENCE_LO 0x2004 6855f33ac92fSHawking Zhang #define regCP_EOP_LAST_FENCE_LO_BASE_IDX 1 6856f33ac92fSHawking Zhang #define regCP_EOP_LAST_FENCE_HI 0x2005 6857f33ac92fSHawking Zhang #define regCP_EOP_LAST_FENCE_HI_BASE_IDX 1 6858f33ac92fSHawking Zhang #define regCP_PIPE_STATS_ADDR_LO 0x2018 6859f33ac92fSHawking Zhang #define regCP_PIPE_STATS_ADDR_LO_BASE_IDX 1 6860f33ac92fSHawking Zhang #define regCP_PIPE_STATS_ADDR_HI 0x2019 6861f33ac92fSHawking Zhang #define regCP_PIPE_STATS_ADDR_HI_BASE_IDX 1 6862f33ac92fSHawking Zhang #define regCP_VGT_IAVERT_COUNT_LO 0x201a 6863f33ac92fSHawking Zhang #define regCP_VGT_IAVERT_COUNT_LO_BASE_IDX 1 6864f33ac92fSHawking Zhang #define regCP_VGT_IAVERT_COUNT_HI 0x201b 6865f33ac92fSHawking Zhang #define regCP_VGT_IAVERT_COUNT_HI_BASE_IDX 1 6866f33ac92fSHawking Zhang #define regCP_VGT_IAPRIM_COUNT_LO 0x201c 6867f33ac92fSHawking Zhang #define regCP_VGT_IAPRIM_COUNT_LO_BASE_IDX 1 6868f33ac92fSHawking Zhang #define regCP_VGT_IAPRIM_COUNT_HI 0x201d 6869f33ac92fSHawking Zhang #define regCP_VGT_IAPRIM_COUNT_HI_BASE_IDX 1 6870f33ac92fSHawking Zhang #define regCP_VGT_GSPRIM_COUNT_LO 0x201e 6871f33ac92fSHawking Zhang #define regCP_VGT_GSPRIM_COUNT_LO_BASE_IDX 1 6872f33ac92fSHawking Zhang #define regCP_VGT_GSPRIM_COUNT_HI 0x201f 6873f33ac92fSHawking Zhang #define regCP_VGT_GSPRIM_COUNT_HI_BASE_IDX 1 6874f33ac92fSHawking Zhang #define regCP_VGT_VSINVOC_COUNT_LO 0x2020 6875f33ac92fSHawking Zhang #define regCP_VGT_VSINVOC_COUNT_LO_BASE_IDX 1 6876f33ac92fSHawking Zhang #define regCP_VGT_VSINVOC_COUNT_HI 0x2021 6877f33ac92fSHawking Zhang #define regCP_VGT_VSINVOC_COUNT_HI_BASE_IDX 1 6878f33ac92fSHawking Zhang #define regCP_VGT_GSINVOC_COUNT_LO 0x2022 6879f33ac92fSHawking Zhang #define regCP_VGT_GSINVOC_COUNT_LO_BASE_IDX 1 6880f33ac92fSHawking Zhang #define regCP_VGT_GSINVOC_COUNT_HI 0x2023 6881f33ac92fSHawking Zhang #define regCP_VGT_GSINVOC_COUNT_HI_BASE_IDX 1 6882f33ac92fSHawking Zhang #define regCP_VGT_HSINVOC_COUNT_LO 0x2024 6883f33ac92fSHawking Zhang #define regCP_VGT_HSINVOC_COUNT_LO_BASE_IDX 1 6884f33ac92fSHawking Zhang #define regCP_VGT_HSINVOC_COUNT_HI 0x2025 6885f33ac92fSHawking Zhang #define regCP_VGT_HSINVOC_COUNT_HI_BASE_IDX 1 6886f33ac92fSHawking Zhang #define regCP_VGT_DSINVOC_COUNT_LO 0x2026 6887f33ac92fSHawking Zhang #define regCP_VGT_DSINVOC_COUNT_LO_BASE_IDX 1 6888f33ac92fSHawking Zhang #define regCP_VGT_DSINVOC_COUNT_HI 0x2027 6889f33ac92fSHawking Zhang #define regCP_VGT_DSINVOC_COUNT_HI_BASE_IDX 1 6890f33ac92fSHawking Zhang #define regCP_PA_CINVOC_COUNT_LO 0x2028 6891f33ac92fSHawking Zhang #define regCP_PA_CINVOC_COUNT_LO_BASE_IDX 1 6892f33ac92fSHawking Zhang #define regCP_PA_CINVOC_COUNT_HI 0x2029 6893f33ac92fSHawking Zhang #define regCP_PA_CINVOC_COUNT_HI_BASE_IDX 1 6894f33ac92fSHawking Zhang #define regCP_PA_CPRIM_COUNT_LO 0x202a 6895f33ac92fSHawking Zhang #define regCP_PA_CPRIM_COUNT_LO_BASE_IDX 1 6896f33ac92fSHawking Zhang #define regCP_PA_CPRIM_COUNT_HI 0x202b 6897f33ac92fSHawking Zhang #define regCP_PA_CPRIM_COUNT_HI_BASE_IDX 1 6898f33ac92fSHawking Zhang #define regCP_SC_PSINVOC_COUNT0_LO 0x202c 6899f33ac92fSHawking Zhang #define regCP_SC_PSINVOC_COUNT0_LO_BASE_IDX 1 6900f33ac92fSHawking Zhang #define regCP_SC_PSINVOC_COUNT0_HI 0x202d 6901f33ac92fSHawking Zhang #define regCP_SC_PSINVOC_COUNT0_HI_BASE_IDX 1 6902f33ac92fSHawking Zhang #define regCP_SC_PSINVOC_COUNT1_LO 0x202e 6903f33ac92fSHawking Zhang #define regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX 1 6904f33ac92fSHawking Zhang #define regCP_SC_PSINVOC_COUNT1_HI 0x202f 6905f33ac92fSHawking Zhang #define regCP_SC_PSINVOC_COUNT1_HI_BASE_IDX 1 6906f33ac92fSHawking Zhang #define regCP_VGT_CSINVOC_COUNT_LO 0x2030 6907f33ac92fSHawking Zhang #define regCP_VGT_CSINVOC_COUNT_LO_BASE_IDX 1 6908f33ac92fSHawking Zhang #define regCP_VGT_CSINVOC_COUNT_HI 0x2031 6909f33ac92fSHawking Zhang #define regCP_VGT_CSINVOC_COUNT_HI_BASE_IDX 1 6910f33ac92fSHawking Zhang #define regCP_VGT_ASINVOC_COUNT_LO 0x2032 6911f33ac92fSHawking Zhang #define regCP_VGT_ASINVOC_COUNT_LO_BASE_IDX 1 6912f33ac92fSHawking Zhang #define regCP_VGT_ASINVOC_COUNT_HI 0x2033 6913f33ac92fSHawking Zhang #define regCP_VGT_ASINVOC_COUNT_HI_BASE_IDX 1 6914f33ac92fSHawking Zhang #define regCP_PIPE_STATS_CONTROL 0x203d 6915f33ac92fSHawking Zhang #define regCP_PIPE_STATS_CONTROL_BASE_IDX 1 6916f33ac92fSHawking Zhang #define regSCRATCH_REG0 0x2040 6917f33ac92fSHawking Zhang #define regSCRATCH_REG0_BASE_IDX 1 6918f33ac92fSHawking Zhang #define regSCRATCH_REG1 0x2041 6919f33ac92fSHawking Zhang #define regSCRATCH_REG1_BASE_IDX 1 6920f33ac92fSHawking Zhang #define regSCRATCH_REG2 0x2042 6921f33ac92fSHawking Zhang #define regSCRATCH_REG2_BASE_IDX 1 6922f33ac92fSHawking Zhang #define regSCRATCH_REG3 0x2043 6923f33ac92fSHawking Zhang #define regSCRATCH_REG3_BASE_IDX 1 6924f33ac92fSHawking Zhang #define regSCRATCH_REG4 0x2044 6925f33ac92fSHawking Zhang #define regSCRATCH_REG4_BASE_IDX 1 6926f33ac92fSHawking Zhang #define regSCRATCH_REG5 0x2045 6927f33ac92fSHawking Zhang #define regSCRATCH_REG5_BASE_IDX 1 6928f33ac92fSHawking Zhang #define regSCRATCH_REG6 0x2046 6929f33ac92fSHawking Zhang #define regSCRATCH_REG6_BASE_IDX 1 6930f33ac92fSHawking Zhang #define regSCRATCH_REG7 0x2047 6931f33ac92fSHawking Zhang #define regSCRATCH_REG7_BASE_IDX 1 6932f33ac92fSHawking Zhang #define regSCRATCH_REG_ATOMIC 0x2048 6933f33ac92fSHawking Zhang #define regSCRATCH_REG_ATOMIC_BASE_IDX 1 6934f33ac92fSHawking Zhang #define regSCRATCH_REG_CMPSWAP_ATOMIC 0x2048 6935f33ac92fSHawking Zhang #define regSCRATCH_REG_CMPSWAP_ATOMIC_BASE_IDX 1 6936f33ac92fSHawking Zhang #define regCP_APPEND_DDID_CNT 0x204b 6937f33ac92fSHawking Zhang #define regCP_APPEND_DDID_CNT_BASE_IDX 1 6938f33ac92fSHawking Zhang #define regCP_APPEND_DATA_HI 0x204c 6939f33ac92fSHawking Zhang #define regCP_APPEND_DATA_HI_BASE_IDX 1 6940f33ac92fSHawking Zhang #define regCP_APPEND_LAST_CS_FENCE_HI 0x204d 6941f33ac92fSHawking Zhang #define regCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX 1 6942f33ac92fSHawking Zhang #define regCP_APPEND_LAST_PS_FENCE_HI 0x204e 6943f33ac92fSHawking Zhang #define regCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX 1 6944f33ac92fSHawking Zhang #define regCP_PFP_ATOMIC_PREOP_LO 0x2052 6945f33ac92fSHawking Zhang #define regCP_PFP_ATOMIC_PREOP_LO_BASE_IDX 1 6946f33ac92fSHawking Zhang #define regCP_PFP_ATOMIC_PREOP_HI 0x2053 6947f33ac92fSHawking Zhang #define regCP_PFP_ATOMIC_PREOP_HI_BASE_IDX 1 6948f33ac92fSHawking Zhang #define regCP_PFP_GDS_ATOMIC0_PREOP_LO 0x2054 6949f33ac92fSHawking Zhang #define regCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 6950f33ac92fSHawking Zhang #define regCP_PFP_GDS_ATOMIC0_PREOP_HI 0x2055 6951f33ac92fSHawking Zhang #define regCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 6952f33ac92fSHawking Zhang #define regCP_PFP_GDS_ATOMIC1_PREOP_LO 0x2056 6953f33ac92fSHawking Zhang #define regCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 6954f33ac92fSHawking Zhang #define regCP_PFP_GDS_ATOMIC1_PREOP_HI 0x2057 6955f33ac92fSHawking Zhang #define regCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 6956f33ac92fSHawking Zhang #define regCP_APPEND_ADDR_LO 0x2058 6957f33ac92fSHawking Zhang #define regCP_APPEND_ADDR_LO_BASE_IDX 1 6958f33ac92fSHawking Zhang #define regCP_APPEND_ADDR_HI 0x2059 6959f33ac92fSHawking Zhang #define regCP_APPEND_ADDR_HI_BASE_IDX 1 6960f33ac92fSHawking Zhang #define regCP_APPEND_DATA 0x205a 6961f33ac92fSHawking Zhang #define regCP_APPEND_DATA_BASE_IDX 1 6962f33ac92fSHawking Zhang #define regCP_APPEND_DATA_LO 0x205a 6963f33ac92fSHawking Zhang #define regCP_APPEND_DATA_LO_BASE_IDX 1 6964f33ac92fSHawking Zhang #define regCP_APPEND_LAST_CS_FENCE 0x205b 6965f33ac92fSHawking Zhang #define regCP_APPEND_LAST_CS_FENCE_BASE_IDX 1 6966f33ac92fSHawking Zhang #define regCP_APPEND_LAST_CS_FENCE_LO 0x205b 6967f33ac92fSHawking Zhang #define regCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX 1 6968f33ac92fSHawking Zhang #define regCP_APPEND_LAST_PS_FENCE 0x205c 6969f33ac92fSHawking Zhang #define regCP_APPEND_LAST_PS_FENCE_BASE_IDX 1 6970f33ac92fSHawking Zhang #define regCP_APPEND_LAST_PS_FENCE_LO 0x205c 6971f33ac92fSHawking Zhang #define regCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX 1 6972f33ac92fSHawking Zhang #define regCP_ATOMIC_PREOP_LO 0x205d 6973f33ac92fSHawking Zhang #define regCP_ATOMIC_PREOP_LO_BASE_IDX 1 6974f33ac92fSHawking Zhang #define regCP_ME_ATOMIC_PREOP_LO 0x205d 6975f33ac92fSHawking Zhang #define regCP_ME_ATOMIC_PREOP_LO_BASE_IDX 1 6976f33ac92fSHawking Zhang #define regCP_ATOMIC_PREOP_HI 0x205e 6977f33ac92fSHawking Zhang #define regCP_ATOMIC_PREOP_HI_BASE_IDX 1 6978f33ac92fSHawking Zhang #define regCP_ME_ATOMIC_PREOP_HI 0x205e 6979f33ac92fSHawking Zhang #define regCP_ME_ATOMIC_PREOP_HI_BASE_IDX 1 6980f33ac92fSHawking Zhang #define regCP_GDS_ATOMIC0_PREOP_LO 0x205f 6981f33ac92fSHawking Zhang #define regCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 6982f33ac92fSHawking Zhang #define regCP_ME_GDS_ATOMIC0_PREOP_LO 0x205f 6983f33ac92fSHawking Zhang #define regCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 6984f33ac92fSHawking Zhang #define regCP_GDS_ATOMIC0_PREOP_HI 0x2060 6985f33ac92fSHawking Zhang #define regCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 6986f33ac92fSHawking Zhang #define regCP_ME_GDS_ATOMIC0_PREOP_HI 0x2060 6987f33ac92fSHawking Zhang #define regCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 6988f33ac92fSHawking Zhang #define regCP_GDS_ATOMIC1_PREOP_LO 0x2061 6989f33ac92fSHawking Zhang #define regCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 6990f33ac92fSHawking Zhang #define regCP_ME_GDS_ATOMIC1_PREOP_LO 0x2061 6991f33ac92fSHawking Zhang #define regCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 6992f33ac92fSHawking Zhang #define regCP_GDS_ATOMIC1_PREOP_HI 0x2062 6993f33ac92fSHawking Zhang #define regCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 6994f33ac92fSHawking Zhang #define regCP_ME_GDS_ATOMIC1_PREOP_HI 0x2062 6995f33ac92fSHawking Zhang #define regCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 6996f33ac92fSHawking Zhang #define regCP_ME_MC_WADDR_LO 0x2069 6997f33ac92fSHawking Zhang #define regCP_ME_MC_WADDR_LO_BASE_IDX 1 6998f33ac92fSHawking Zhang #define regCP_ME_MC_WADDR_HI 0x206a 6999f33ac92fSHawking Zhang #define regCP_ME_MC_WADDR_HI_BASE_IDX 1 7000f33ac92fSHawking Zhang #define regCP_ME_MC_WDATA_LO 0x206b 7001f33ac92fSHawking Zhang #define regCP_ME_MC_WDATA_LO_BASE_IDX 1 7002f33ac92fSHawking Zhang #define regCP_ME_MC_WDATA_HI 0x206c 7003f33ac92fSHawking Zhang #define regCP_ME_MC_WDATA_HI_BASE_IDX 1 7004f33ac92fSHawking Zhang #define regCP_ME_MC_RADDR_LO 0x206d 7005f33ac92fSHawking Zhang #define regCP_ME_MC_RADDR_LO_BASE_IDX 1 7006f33ac92fSHawking Zhang #define regCP_ME_MC_RADDR_HI 0x206e 7007f33ac92fSHawking Zhang #define regCP_ME_MC_RADDR_HI_BASE_IDX 1 7008f33ac92fSHawking Zhang #define regCP_SEM_WAIT_TIMER 0x206f 7009f33ac92fSHawking Zhang #define regCP_SEM_WAIT_TIMER_BASE_IDX 1 7010f33ac92fSHawking Zhang #define regCP_SIG_SEM_ADDR_LO 0x2070 7011f33ac92fSHawking Zhang #define regCP_SIG_SEM_ADDR_LO_BASE_IDX 1 7012f33ac92fSHawking Zhang #define regCP_SIG_SEM_ADDR_HI 0x2071 7013f33ac92fSHawking Zhang #define regCP_SIG_SEM_ADDR_HI_BASE_IDX 1 7014f33ac92fSHawking Zhang #define regCP_WAIT_REG_MEM_TIMEOUT 0x2074 7015f33ac92fSHawking Zhang #define regCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX 1 7016f33ac92fSHawking Zhang #define regCP_WAIT_SEM_ADDR_LO 0x2075 7017f33ac92fSHawking Zhang #define regCP_WAIT_SEM_ADDR_LO_BASE_IDX 1 7018f33ac92fSHawking Zhang #define regCP_WAIT_SEM_ADDR_HI 0x2076 7019f33ac92fSHawking Zhang #define regCP_WAIT_SEM_ADDR_HI_BASE_IDX 1 7020f33ac92fSHawking Zhang #define regCP_DMA_PFP_CONTROL 0x2077 7021f33ac92fSHawking Zhang #define regCP_DMA_PFP_CONTROL_BASE_IDX 1 7022f33ac92fSHawking Zhang #define regCP_DMA_ME_CONTROL 0x2078 7023f33ac92fSHawking Zhang #define regCP_DMA_ME_CONTROL_BASE_IDX 1 7024f33ac92fSHawking Zhang #define regCP_DMA_ME_SRC_ADDR 0x2080 7025f33ac92fSHawking Zhang #define regCP_DMA_ME_SRC_ADDR_BASE_IDX 1 7026f33ac92fSHawking Zhang #define regCP_DMA_ME_SRC_ADDR_HI 0x2081 7027f33ac92fSHawking Zhang #define regCP_DMA_ME_SRC_ADDR_HI_BASE_IDX 1 7028f33ac92fSHawking Zhang #define regCP_DMA_ME_DST_ADDR 0x2082 7029f33ac92fSHawking Zhang #define regCP_DMA_ME_DST_ADDR_BASE_IDX 1 7030f33ac92fSHawking Zhang #define regCP_DMA_ME_DST_ADDR_HI 0x2083 7031f33ac92fSHawking Zhang #define regCP_DMA_ME_DST_ADDR_HI_BASE_IDX 1 7032f33ac92fSHawking Zhang #define regCP_DMA_ME_COMMAND 0x2084 7033f33ac92fSHawking Zhang #define regCP_DMA_ME_COMMAND_BASE_IDX 1 7034f33ac92fSHawking Zhang #define regCP_DMA_PFP_SRC_ADDR 0x2085 7035f33ac92fSHawking Zhang #define regCP_DMA_PFP_SRC_ADDR_BASE_IDX 1 7036f33ac92fSHawking Zhang #define regCP_DMA_PFP_SRC_ADDR_HI 0x2086 7037f33ac92fSHawking Zhang #define regCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX 1 7038f33ac92fSHawking Zhang #define regCP_DMA_PFP_DST_ADDR 0x2087 7039f33ac92fSHawking Zhang #define regCP_DMA_PFP_DST_ADDR_BASE_IDX 1 7040f33ac92fSHawking Zhang #define regCP_DMA_PFP_DST_ADDR_HI 0x2088 7041f33ac92fSHawking Zhang #define regCP_DMA_PFP_DST_ADDR_HI_BASE_IDX 1 7042f33ac92fSHawking Zhang #define regCP_DMA_PFP_COMMAND 0x2089 7043f33ac92fSHawking Zhang #define regCP_DMA_PFP_COMMAND_BASE_IDX 1 7044f33ac92fSHawking Zhang #define regCP_DMA_CNTL 0x208a 7045f33ac92fSHawking Zhang #define regCP_DMA_CNTL_BASE_IDX 1 7046f33ac92fSHawking Zhang #define regCP_DMA_READ_TAGS 0x208b 7047f33ac92fSHawking Zhang #define regCP_DMA_READ_TAGS_BASE_IDX 1 7048f33ac92fSHawking Zhang #define regCP_PFP_IB_CONTROL 0x208d 7049f33ac92fSHawking Zhang #define regCP_PFP_IB_CONTROL_BASE_IDX 1 7050f33ac92fSHawking Zhang #define regCP_PFP_LOAD_CONTROL 0x208e 7051f33ac92fSHawking Zhang #define regCP_PFP_LOAD_CONTROL_BASE_IDX 1 7052f33ac92fSHawking Zhang #define regCP_SCRATCH_INDEX 0x208f 7053f33ac92fSHawking Zhang #define regCP_SCRATCH_INDEX_BASE_IDX 1 7054f33ac92fSHawking Zhang #define regCP_SCRATCH_DATA 0x2090 7055f33ac92fSHawking Zhang #define regCP_SCRATCH_DATA_BASE_IDX 1 7056f33ac92fSHawking Zhang #define regCP_RB_OFFSET 0x2091 7057f33ac92fSHawking Zhang #define regCP_RB_OFFSET_BASE_IDX 1 7058f33ac92fSHawking Zhang #define regCP_IB2_OFFSET 0x2093 7059f33ac92fSHawking Zhang #define regCP_IB2_OFFSET_BASE_IDX 1 7060f33ac92fSHawking Zhang #define regCP_IB2_PREAMBLE_BEGIN 0x2096 7061f33ac92fSHawking Zhang #define regCP_IB2_PREAMBLE_BEGIN_BASE_IDX 1 7062f33ac92fSHawking Zhang #define regCP_IB2_PREAMBLE_END 0x2097 7063f33ac92fSHawking Zhang #define regCP_IB2_PREAMBLE_END_BASE_IDX 1 7064f33ac92fSHawking Zhang #define regCP_DMA_ME_CMD_ADDR_LO 0x209c 7065f33ac92fSHawking Zhang #define regCP_DMA_ME_CMD_ADDR_LO_BASE_IDX 1 7066f33ac92fSHawking Zhang #define regCP_DMA_ME_CMD_ADDR_HI 0x209d 7067f33ac92fSHawking Zhang #define regCP_DMA_ME_CMD_ADDR_HI_BASE_IDX 1 7068f33ac92fSHawking Zhang #define regCP_DMA_PFP_CMD_ADDR_LO 0x209e 7069f33ac92fSHawking Zhang #define regCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX 1 7070f33ac92fSHawking Zhang #define regCP_DMA_PFP_CMD_ADDR_HI 0x209f 7071f33ac92fSHawking Zhang #define regCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX 1 7072f33ac92fSHawking Zhang #define regCP_APPEND_CMD_ADDR_LO 0x20a0 7073f33ac92fSHawking Zhang #define regCP_APPEND_CMD_ADDR_LO_BASE_IDX 1 7074f33ac92fSHawking Zhang #define regCP_APPEND_CMD_ADDR_HI 0x20a1 7075f33ac92fSHawking Zhang #define regCP_APPEND_CMD_ADDR_HI_BASE_IDX 1 7076f33ac92fSHawking Zhang #define regUCONFIG_RESERVED_REG0 0x20a2 7077f33ac92fSHawking Zhang #define regUCONFIG_RESERVED_REG0_BASE_IDX 1 7078f33ac92fSHawking Zhang #define regUCONFIG_RESERVED_REG1 0x20a3 7079f33ac92fSHawking Zhang #define regUCONFIG_RESERVED_REG1_BASE_IDX 1 7080f33ac92fSHawking Zhang #define regCP_PA_MSPRIM_COUNT_LO 0x20a4 7081f33ac92fSHawking Zhang #define regCP_PA_MSPRIM_COUNT_LO_BASE_IDX 1 7082f33ac92fSHawking Zhang #define regCP_PA_MSPRIM_COUNT_HI 0x20a5 7083f33ac92fSHawking Zhang #define regCP_PA_MSPRIM_COUNT_HI_BASE_IDX 1 7084f33ac92fSHawking Zhang #define regCP_GE_MSINVOC_COUNT_LO 0x20a6 7085f33ac92fSHawking Zhang #define regCP_GE_MSINVOC_COUNT_LO_BASE_IDX 1 7086f33ac92fSHawking Zhang #define regCP_GE_MSINVOC_COUNT_HI 0x20a7 7087f33ac92fSHawking Zhang #define regCP_GE_MSINVOC_COUNT_HI_BASE_IDX 1 7088f33ac92fSHawking Zhang #define regCP_IB2_CMD_BUFSZ 0x20c1 7089f33ac92fSHawking Zhang #define regCP_IB2_CMD_BUFSZ_BASE_IDX 1 7090f33ac92fSHawking Zhang #define regCP_ST_CMD_BUFSZ 0x20c2 7091f33ac92fSHawking Zhang #define regCP_ST_CMD_BUFSZ_BASE_IDX 1 7092f33ac92fSHawking Zhang #define regCP_IB2_BASE_LO 0x20cf 7093f33ac92fSHawking Zhang #define regCP_IB2_BASE_LO_BASE_IDX 1 7094f33ac92fSHawking Zhang #define regCP_IB2_BASE_HI 0x20d0 7095f33ac92fSHawking Zhang #define regCP_IB2_BASE_HI_BASE_IDX 1 7096f33ac92fSHawking Zhang #define regCP_IB2_BUFSZ 0x20d1 7097f33ac92fSHawking Zhang #define regCP_IB2_BUFSZ_BASE_IDX 1 7098f33ac92fSHawking Zhang #define regCP_ST_BASE_LO 0x20d2 7099f33ac92fSHawking Zhang #define regCP_ST_BASE_LO_BASE_IDX 1 7100f33ac92fSHawking Zhang #define regCP_ST_BASE_HI 0x20d3 7101f33ac92fSHawking Zhang #define regCP_ST_BASE_HI_BASE_IDX 1 7102f33ac92fSHawking Zhang #define regCP_ST_BUFSZ 0x20d4 7103f33ac92fSHawking Zhang #define regCP_ST_BUFSZ_BASE_IDX 1 7104f33ac92fSHawking Zhang #define regCP_EOP_DONE_EVENT_CNTL 0x20d5 7105f33ac92fSHawking Zhang #define regCP_EOP_DONE_EVENT_CNTL_BASE_IDX 1 7106f33ac92fSHawking Zhang #define regCP_EOP_DONE_DATA_CNTL 0x20d6 7107f33ac92fSHawking Zhang #define regCP_EOP_DONE_DATA_CNTL_BASE_IDX 1 7108f33ac92fSHawking Zhang #define regCP_EOP_DONE_CNTX_ID 0x20d7 7109f33ac92fSHawking Zhang #define regCP_EOP_DONE_CNTX_ID_BASE_IDX 1 7110f33ac92fSHawking Zhang #define regCP_DB_BASE_LO 0x20d8 7111f33ac92fSHawking Zhang #define regCP_DB_BASE_LO_BASE_IDX 1 7112f33ac92fSHawking Zhang #define regCP_DB_BASE_HI 0x20d9 7113f33ac92fSHawking Zhang #define regCP_DB_BASE_HI_BASE_IDX 1 7114f33ac92fSHawking Zhang #define regCP_DB_BUFSZ 0x20da 7115f33ac92fSHawking Zhang #define regCP_DB_BUFSZ_BASE_IDX 1 7116f33ac92fSHawking Zhang #define regCP_DB_CMD_BUFSZ 0x20db 7117f33ac92fSHawking Zhang #define regCP_DB_CMD_BUFSZ_BASE_IDX 1 7118f33ac92fSHawking Zhang #define regCP_PFP_COMPLETION_STATUS 0x20ec 7119f33ac92fSHawking Zhang #define regCP_PFP_COMPLETION_STATUS_BASE_IDX 1 7120f33ac92fSHawking Zhang #define regCP_PRED_NOT_VISIBLE 0x20ee 7121f33ac92fSHawking Zhang #define regCP_PRED_NOT_VISIBLE_BASE_IDX 1 7122f33ac92fSHawking Zhang #define regCP_PFP_METADATA_BASE_ADDR 0x20f0 7123f33ac92fSHawking Zhang #define regCP_PFP_METADATA_BASE_ADDR_BASE_IDX 1 7124f33ac92fSHawking Zhang #define regCP_PFP_METADATA_BASE_ADDR_HI 0x20f1 7125f33ac92fSHawking Zhang #define regCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX 1 7126f33ac92fSHawking Zhang #define regCP_DRAW_INDX_INDR_ADDR 0x20f4 7127f33ac92fSHawking Zhang #define regCP_DRAW_INDX_INDR_ADDR_BASE_IDX 1 7128f33ac92fSHawking Zhang #define regCP_DRAW_INDX_INDR_ADDR_HI 0x20f5 7129f33ac92fSHawking Zhang #define regCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX 1 7130f33ac92fSHawking Zhang #define regCP_DISPATCH_INDR_ADDR 0x20f6 7131f33ac92fSHawking Zhang #define regCP_DISPATCH_INDR_ADDR_BASE_IDX 1 7132f33ac92fSHawking Zhang #define regCP_DISPATCH_INDR_ADDR_HI 0x20f7 7133f33ac92fSHawking Zhang #define regCP_DISPATCH_INDR_ADDR_HI_BASE_IDX 1 7134f33ac92fSHawking Zhang #define regCP_INDEX_BASE_ADDR 0x20f8 7135f33ac92fSHawking Zhang #define regCP_INDEX_BASE_ADDR_BASE_IDX 1 7136f33ac92fSHawking Zhang #define regCP_INDEX_BASE_ADDR_HI 0x20f9 7137f33ac92fSHawking Zhang #define regCP_INDEX_BASE_ADDR_HI_BASE_IDX 1 7138f33ac92fSHawking Zhang #define regCP_INDEX_TYPE 0x20fa 7139f33ac92fSHawking Zhang #define regCP_INDEX_TYPE_BASE_IDX 1 7140f33ac92fSHawking Zhang #define regCP_GDS_BKUP_ADDR 0x20fb 7141f33ac92fSHawking Zhang #define regCP_GDS_BKUP_ADDR_BASE_IDX 1 7142f33ac92fSHawking Zhang #define regCP_GDS_BKUP_ADDR_HI 0x20fc 7143f33ac92fSHawking Zhang #define regCP_GDS_BKUP_ADDR_HI_BASE_IDX 1 7144f33ac92fSHawking Zhang #define regCP_SAMPLE_STATUS 0x20fd 7145f33ac92fSHawking Zhang #define regCP_SAMPLE_STATUS_BASE_IDX 1 7146f33ac92fSHawking Zhang #define regCP_ME_COHER_CNTL 0x20fe 7147f33ac92fSHawking Zhang #define regCP_ME_COHER_CNTL_BASE_IDX 1 7148f33ac92fSHawking Zhang #define regCP_ME_COHER_SIZE 0x20ff 7149f33ac92fSHawking Zhang #define regCP_ME_COHER_SIZE_BASE_IDX 1 7150f33ac92fSHawking Zhang #define regCP_ME_COHER_SIZE_HI 0x2100 7151f33ac92fSHawking Zhang #define regCP_ME_COHER_SIZE_HI_BASE_IDX 1 7152f33ac92fSHawking Zhang #define regCP_ME_COHER_BASE 0x2101 7153f33ac92fSHawking Zhang #define regCP_ME_COHER_BASE_BASE_IDX 1 7154f33ac92fSHawking Zhang #define regCP_ME_COHER_BASE_HI 0x2102 7155f33ac92fSHawking Zhang #define regCP_ME_COHER_BASE_HI_BASE_IDX 1 7156f33ac92fSHawking Zhang #define regCP_ME_COHER_STATUS 0x2103 7157f33ac92fSHawking Zhang #define regCP_ME_COHER_STATUS_BASE_IDX 1 7158f33ac92fSHawking Zhang #define regRLC_GPM_PERF_COUNT_0 0x2140 7159f33ac92fSHawking Zhang #define regRLC_GPM_PERF_COUNT_0_BASE_IDX 1 7160f33ac92fSHawking Zhang #define regRLC_GPM_PERF_COUNT_1 0x2141 7161f33ac92fSHawking Zhang #define regRLC_GPM_PERF_COUNT_1_BASE_IDX 1 7162f33ac92fSHawking Zhang #define regGRBM_GFX_INDEX 0x2200 7163f33ac92fSHawking Zhang #define regGRBM_GFX_INDEX_BASE_IDX 1 7164f33ac92fSHawking Zhang #define regVGT_PRIMITIVE_TYPE 0x2242 7165f33ac92fSHawking Zhang #define regVGT_PRIMITIVE_TYPE_BASE_IDX 1 7166f33ac92fSHawking Zhang #define regVGT_INDEX_TYPE 0x2243 7167f33ac92fSHawking Zhang #define regVGT_INDEX_TYPE_BASE_IDX 1 7168f33ac92fSHawking Zhang #define regGE_MIN_VTX_INDX 0x2249 7169f33ac92fSHawking Zhang #define regGE_MIN_VTX_INDX_BASE_IDX 1 7170f33ac92fSHawking Zhang #define regGE_INDX_OFFSET 0x224a 7171f33ac92fSHawking Zhang #define regGE_INDX_OFFSET_BASE_IDX 1 7172f33ac92fSHawking Zhang #define regGE_MULTI_PRIM_IB_RESET_EN 0x224b 7173f33ac92fSHawking Zhang #define regGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX 1 7174f33ac92fSHawking Zhang #define regVGT_NUM_INDICES 0x224c 7175f33ac92fSHawking Zhang #define regVGT_NUM_INDICES_BASE_IDX 1 7176f33ac92fSHawking Zhang #define regVGT_NUM_INSTANCES 0x224d 7177f33ac92fSHawking Zhang #define regVGT_NUM_INSTANCES_BASE_IDX 1 7178f33ac92fSHawking Zhang #define regVGT_TF_RING_SIZE 0x224e 7179f33ac92fSHawking Zhang #define regVGT_TF_RING_SIZE_BASE_IDX 1 7180f33ac92fSHawking Zhang #define regVGT_HS_OFFCHIP_PARAM 0x224f 7181f33ac92fSHawking Zhang #define regVGT_HS_OFFCHIP_PARAM_BASE_IDX 1 7182f33ac92fSHawking Zhang #define regVGT_TF_MEMORY_BASE 0x2250 7183f33ac92fSHawking Zhang #define regVGT_TF_MEMORY_BASE_BASE_IDX 1 7184f33ac92fSHawking Zhang #define regGE_MAX_VTX_INDX 0x2259 7185f33ac92fSHawking Zhang #define regGE_MAX_VTX_INDX_BASE_IDX 1 7186f33ac92fSHawking Zhang #define regVGT_INSTANCE_BASE_ID 0x225a 7187f33ac92fSHawking Zhang #define regVGT_INSTANCE_BASE_ID_BASE_IDX 1 7188f33ac92fSHawking Zhang #define regGE_CNTL 0x225b 7189f33ac92fSHawking Zhang #define regGE_CNTL_BASE_IDX 1 7190f33ac92fSHawking Zhang #define regGE_USER_VGPR1 0x225c 7191f33ac92fSHawking Zhang #define regGE_USER_VGPR1_BASE_IDX 1 7192f33ac92fSHawking Zhang #define regGE_USER_VGPR2 0x225d 7193f33ac92fSHawking Zhang #define regGE_USER_VGPR2_BASE_IDX 1 7194f33ac92fSHawking Zhang #define regGE_USER_VGPR3 0x225e 7195f33ac92fSHawking Zhang #define regGE_USER_VGPR3_BASE_IDX 1 7196f33ac92fSHawking Zhang #define regGE_STEREO_CNTL 0x225f 7197f33ac92fSHawking Zhang #define regGE_STEREO_CNTL_BASE_IDX 1 7198f33ac92fSHawking Zhang #define regGE_PC_ALLOC 0x2260 7199f33ac92fSHawking Zhang #define regGE_PC_ALLOC_BASE_IDX 1 7200f33ac92fSHawking Zhang #define regVGT_TF_MEMORY_BASE_HI 0x2261 7201f33ac92fSHawking Zhang #define regVGT_TF_MEMORY_BASE_HI_BASE_IDX 1 7202f33ac92fSHawking Zhang #define regGE_USER_VGPR_EN 0x2262 7203f33ac92fSHawking Zhang #define regGE_USER_VGPR_EN_BASE_IDX 1 7204f33ac92fSHawking Zhang #define regGE_GS_FAST_LAUNCH_WG_DIM 0x2264 7205f33ac92fSHawking Zhang #define regGE_GS_FAST_LAUNCH_WG_DIM_BASE_IDX 1 7206f33ac92fSHawking Zhang #define regGE_GS_FAST_LAUNCH_WG_DIM_1 0x2265 7207f33ac92fSHawking Zhang #define regGE_GS_FAST_LAUNCH_WG_DIM_1_BASE_IDX 1 7208f33ac92fSHawking Zhang #define regVGT_GS_OUT_PRIM_TYPE 0x2266 7209f33ac92fSHawking Zhang #define regVGT_GS_OUT_PRIM_TYPE_BASE_IDX 1 7210f33ac92fSHawking Zhang #define regPA_SU_LINE_STIPPLE_VALUE 0x2280 7211f33ac92fSHawking Zhang #define regPA_SU_LINE_STIPPLE_VALUE_BASE_IDX 1 7212f33ac92fSHawking Zhang #define regPA_SC_LINE_STIPPLE_STATE 0x2281 7213f33ac92fSHawking Zhang #define regPA_SC_LINE_STIPPLE_STATE_BASE_IDX 1 7214f33ac92fSHawking Zhang #define regPA_SC_SCREEN_EXTENT_MIN_0 0x2284 7215f33ac92fSHawking Zhang #define regPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX 1 7216f33ac92fSHawking Zhang #define regPA_SC_SCREEN_EXTENT_MAX_0 0x2285 7217f33ac92fSHawking Zhang #define regPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX 1 7218f33ac92fSHawking Zhang #define regPA_SC_SCREEN_EXTENT_MIN_1 0x2286 7219f33ac92fSHawking Zhang #define regPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX 1 7220f33ac92fSHawking Zhang #define regPA_SC_SCREEN_EXTENT_MAX_1 0x228b 7221f33ac92fSHawking Zhang #define regPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX 1 7222f33ac92fSHawking Zhang #define regPA_SC_P3D_TRAP_SCREEN_HV_EN 0x22a0 7223f33ac92fSHawking Zhang #define regPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 7224f33ac92fSHawking Zhang #define regPA_SC_P3D_TRAP_SCREEN_H 0x22a1 7225f33ac92fSHawking Zhang #define regPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX 1 7226f33ac92fSHawking Zhang #define regPA_SC_P3D_TRAP_SCREEN_V 0x22a2 7227f33ac92fSHawking Zhang #define regPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX 1 7228f33ac92fSHawking Zhang #define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0x22a3 7229f33ac92fSHawking Zhang #define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 7230f33ac92fSHawking Zhang #define regPA_SC_P3D_TRAP_SCREEN_COUNT 0x22a4 7231f33ac92fSHawking Zhang #define regPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX 1 7232f33ac92fSHawking Zhang #define regPA_SC_HP3D_TRAP_SCREEN_HV_EN 0x22a8 7233f33ac92fSHawking Zhang #define regPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 7234f33ac92fSHawking Zhang #define regPA_SC_HP3D_TRAP_SCREEN_H 0x22a9 7235f33ac92fSHawking Zhang #define regPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX 1 7236f33ac92fSHawking Zhang #define regPA_SC_HP3D_TRAP_SCREEN_V 0x22aa 7237f33ac92fSHawking Zhang #define regPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX 1 7238f33ac92fSHawking Zhang #define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0x22ab 7239f33ac92fSHawking Zhang #define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 7240f33ac92fSHawking Zhang #define regPA_SC_HP3D_TRAP_SCREEN_COUNT 0x22ac 7241f33ac92fSHawking Zhang #define regPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX 1 7242f33ac92fSHawking Zhang #define regPA_SC_TRAP_SCREEN_HV_EN 0x22b0 7243f33ac92fSHawking Zhang #define regPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX 1 7244f33ac92fSHawking Zhang #define regPA_SC_TRAP_SCREEN_H 0x22b1 7245f33ac92fSHawking Zhang #define regPA_SC_TRAP_SCREEN_H_BASE_IDX 1 7246f33ac92fSHawking Zhang #define regPA_SC_TRAP_SCREEN_V 0x22b2 7247f33ac92fSHawking Zhang #define regPA_SC_TRAP_SCREEN_V_BASE_IDX 1 7248f33ac92fSHawking Zhang #define regPA_SC_TRAP_SCREEN_OCCURRENCE 0x22b3 7249f33ac92fSHawking Zhang #define regPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 7250f33ac92fSHawking Zhang #define regPA_SC_TRAP_SCREEN_COUNT 0x22b4 7251f33ac92fSHawking Zhang #define regPA_SC_TRAP_SCREEN_COUNT_BASE_IDX 1 7252f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_USERDATA_0 0x2340 7253f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_USERDATA_0_BASE_IDX 1 7254f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_USERDATA_1 0x2341 7255f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_USERDATA_1_BASE_IDX 1 7256f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_USERDATA_2 0x2342 7257f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_USERDATA_2_BASE_IDX 1 7258f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_USERDATA_3 0x2343 7259f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_USERDATA_3_BASE_IDX 1 7260f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_USERDATA_4 0x2344 7261f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_USERDATA_4_BASE_IDX 1 7262f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_USERDATA_5 0x2345 7263f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_USERDATA_5_BASE_IDX 1 7264f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_USERDATA_6 0x2346 7265f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_USERDATA_6_BASE_IDX 1 7266f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_USERDATA_7 0x2347 7267f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_USERDATA_7_BASE_IDX 1 7268f33ac92fSHawking Zhang #define regSQC_CACHES 0x2348 7269f33ac92fSHawking Zhang #define regSQC_CACHES_BASE_IDX 1 7270f33ac92fSHawking Zhang #define regTA_CS_BC_BASE_ADDR 0x2380 7271f33ac92fSHawking Zhang #define regTA_CS_BC_BASE_ADDR_BASE_IDX 1 7272f33ac92fSHawking Zhang #define regTA_CS_BC_BASE_ADDR_HI 0x2381 7273f33ac92fSHawking Zhang #define regTA_CS_BC_BASE_ADDR_HI_BASE_IDX 1 7274f33ac92fSHawking Zhang #define regDB_OCCLUSION_COUNT0_LOW 0x23c0 7275f33ac92fSHawking Zhang #define regDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1 7276f33ac92fSHawking Zhang #define regDB_OCCLUSION_COUNT0_HI 0x23c1 7277f33ac92fSHawking Zhang #define regDB_OCCLUSION_COUNT0_HI_BASE_IDX 1 7278f33ac92fSHawking Zhang #define regDB_OCCLUSION_COUNT1_LOW 0x23c2 7279f33ac92fSHawking Zhang #define regDB_OCCLUSION_COUNT1_LOW_BASE_IDX 1 7280f33ac92fSHawking Zhang #define regDB_OCCLUSION_COUNT1_HI 0x23c3 7281f33ac92fSHawking Zhang #define regDB_OCCLUSION_COUNT1_HI_BASE_IDX 1 7282f33ac92fSHawking Zhang #define regDB_OCCLUSION_COUNT2_LOW 0x23c4 7283f33ac92fSHawking Zhang #define regDB_OCCLUSION_COUNT2_LOW_BASE_IDX 1 7284f33ac92fSHawking Zhang #define regDB_OCCLUSION_COUNT2_HI 0x23c5 7285f33ac92fSHawking Zhang #define regDB_OCCLUSION_COUNT2_HI_BASE_IDX 1 7286f33ac92fSHawking Zhang #define regDB_OCCLUSION_COUNT3_LOW 0x23c6 7287f33ac92fSHawking Zhang #define regDB_OCCLUSION_COUNT3_LOW_BASE_IDX 1 7288f33ac92fSHawking Zhang #define regDB_OCCLUSION_COUNT3_HI 0x23c7 7289f33ac92fSHawking Zhang #define regDB_OCCLUSION_COUNT3_HI_BASE_IDX 1 7290f33ac92fSHawking Zhang #define regGDS_RD_ADDR 0x2400 7291f33ac92fSHawking Zhang #define regGDS_RD_ADDR_BASE_IDX 1 7292f33ac92fSHawking Zhang #define regGDS_RD_DATA 0x2401 7293f33ac92fSHawking Zhang #define regGDS_RD_DATA_BASE_IDX 1 7294f33ac92fSHawking Zhang #define regGDS_RD_BURST_ADDR 0x2402 7295f33ac92fSHawking Zhang #define regGDS_RD_BURST_ADDR_BASE_IDX 1 7296f33ac92fSHawking Zhang #define regGDS_RD_BURST_COUNT 0x2403 7297f33ac92fSHawking Zhang #define regGDS_RD_BURST_COUNT_BASE_IDX 1 7298f33ac92fSHawking Zhang #define regGDS_RD_BURST_DATA 0x2404 7299f33ac92fSHawking Zhang #define regGDS_RD_BURST_DATA_BASE_IDX 1 7300f33ac92fSHawking Zhang #define regGDS_WR_ADDR 0x2405 7301f33ac92fSHawking Zhang #define regGDS_WR_ADDR_BASE_IDX 1 7302f33ac92fSHawking Zhang #define regGDS_WR_DATA 0x2406 7303f33ac92fSHawking Zhang #define regGDS_WR_DATA_BASE_IDX 1 7304f33ac92fSHawking Zhang #define regGDS_WR_BURST_ADDR 0x2407 7305f33ac92fSHawking Zhang #define regGDS_WR_BURST_ADDR_BASE_IDX 1 7306f33ac92fSHawking Zhang #define regGDS_WR_BURST_DATA 0x2408 7307f33ac92fSHawking Zhang #define regGDS_WR_BURST_DATA_BASE_IDX 1 7308f33ac92fSHawking Zhang #define regGDS_WRITE_COMPLETE 0x2409 7309f33ac92fSHawking Zhang #define regGDS_WRITE_COMPLETE_BASE_IDX 1 7310f33ac92fSHawking Zhang #define regGDS_ATOM_CNTL 0x240a 7311f33ac92fSHawking Zhang #define regGDS_ATOM_CNTL_BASE_IDX 1 7312f33ac92fSHawking Zhang #define regGDS_ATOM_COMPLETE 0x240b 7313f33ac92fSHawking Zhang #define regGDS_ATOM_COMPLETE_BASE_IDX 1 7314f33ac92fSHawking Zhang #define regGDS_ATOM_BASE 0x240c 7315f33ac92fSHawking Zhang #define regGDS_ATOM_BASE_BASE_IDX 1 7316f33ac92fSHawking Zhang #define regGDS_ATOM_SIZE 0x240d 7317f33ac92fSHawking Zhang #define regGDS_ATOM_SIZE_BASE_IDX 1 7318f33ac92fSHawking Zhang #define regGDS_ATOM_OFFSET0 0x240e 7319f33ac92fSHawking Zhang #define regGDS_ATOM_OFFSET0_BASE_IDX 1 7320f33ac92fSHawking Zhang #define regGDS_ATOM_OFFSET1 0x240f 7321f33ac92fSHawking Zhang #define regGDS_ATOM_OFFSET1_BASE_IDX 1 7322f33ac92fSHawking Zhang #define regGDS_ATOM_DST 0x2410 7323f33ac92fSHawking Zhang #define regGDS_ATOM_DST_BASE_IDX 1 7324f33ac92fSHawking Zhang #define regGDS_ATOM_OP 0x2411 7325f33ac92fSHawking Zhang #define regGDS_ATOM_OP_BASE_IDX 1 7326f33ac92fSHawking Zhang #define regGDS_ATOM_SRC0 0x2412 7327f33ac92fSHawking Zhang #define regGDS_ATOM_SRC0_BASE_IDX 1 7328f33ac92fSHawking Zhang #define regGDS_ATOM_SRC0_U 0x2413 7329f33ac92fSHawking Zhang #define regGDS_ATOM_SRC0_U_BASE_IDX 1 7330f33ac92fSHawking Zhang #define regGDS_ATOM_SRC1 0x2414 7331f33ac92fSHawking Zhang #define regGDS_ATOM_SRC1_BASE_IDX 1 7332f33ac92fSHawking Zhang #define regGDS_ATOM_SRC1_U 0x2415 7333f33ac92fSHawking Zhang #define regGDS_ATOM_SRC1_U_BASE_IDX 1 7334f33ac92fSHawking Zhang #define regGDS_ATOM_READ0 0x2416 7335f33ac92fSHawking Zhang #define regGDS_ATOM_READ0_BASE_IDX 1 7336f33ac92fSHawking Zhang #define regGDS_ATOM_READ0_U 0x2417 7337f33ac92fSHawking Zhang #define regGDS_ATOM_READ0_U_BASE_IDX 1 7338f33ac92fSHawking Zhang #define regGDS_ATOM_READ1 0x2418 7339f33ac92fSHawking Zhang #define regGDS_ATOM_READ1_BASE_IDX 1 7340f33ac92fSHawking Zhang #define regGDS_ATOM_READ1_U 0x2419 7341f33ac92fSHawking Zhang #define regGDS_ATOM_READ1_U_BASE_IDX 1 7342f33ac92fSHawking Zhang #define regGDS_GWS_RESOURCE_CNTL 0x241a 7343f33ac92fSHawking Zhang #define regGDS_GWS_RESOURCE_CNTL_BASE_IDX 1 7344f33ac92fSHawking Zhang #define regGDS_GWS_RESOURCE 0x241b 7345f33ac92fSHawking Zhang #define regGDS_GWS_RESOURCE_BASE_IDX 1 7346f33ac92fSHawking Zhang #define regGDS_GWS_RESOURCE_CNT 0x241c 7347f33ac92fSHawking Zhang #define regGDS_GWS_RESOURCE_CNT_BASE_IDX 1 7348f33ac92fSHawking Zhang #define regGDS_OA_CNTL 0x241d 7349f33ac92fSHawking Zhang #define regGDS_OA_CNTL_BASE_IDX 1 7350f33ac92fSHawking Zhang #define regGDS_OA_COUNTER 0x241e 7351f33ac92fSHawking Zhang #define regGDS_OA_COUNTER_BASE_IDX 1 7352f33ac92fSHawking Zhang #define regGDS_OA_ADDRESS 0x241f 7353f33ac92fSHawking Zhang #define regGDS_OA_ADDRESS_BASE_IDX 1 7354f33ac92fSHawking Zhang #define regGDS_OA_INCDEC 0x2420 7355f33ac92fSHawking Zhang #define regGDS_OA_INCDEC_BASE_IDX 1 7356f33ac92fSHawking Zhang #define regGDS_OA_RING_SIZE 0x2421 7357f33ac92fSHawking Zhang #define regGDS_OA_RING_SIZE_BASE_IDX 1 7358f33ac92fSHawking Zhang #define regGDS_STRMOUT_DWORDS_WRITTEN_0 0x2422 7359f33ac92fSHawking Zhang #define regGDS_STRMOUT_DWORDS_WRITTEN_0_BASE_IDX 1 7360f33ac92fSHawking Zhang #define regGDS_STRMOUT_DWORDS_WRITTEN_1 0x2423 7361f33ac92fSHawking Zhang #define regGDS_STRMOUT_DWORDS_WRITTEN_1_BASE_IDX 1 7362f33ac92fSHawking Zhang #define regGDS_STRMOUT_DWORDS_WRITTEN_2 0x2424 7363f33ac92fSHawking Zhang #define regGDS_STRMOUT_DWORDS_WRITTEN_2_BASE_IDX 1 7364f33ac92fSHawking Zhang #define regGDS_STRMOUT_DWORDS_WRITTEN_3 0x2425 7365f33ac92fSHawking Zhang #define regGDS_STRMOUT_DWORDS_WRITTEN_3_BASE_IDX 1 7366f33ac92fSHawking Zhang #define regGDS_GS_0 0x2426 7367f33ac92fSHawking Zhang #define regGDS_GS_0_BASE_IDX 1 7368f33ac92fSHawking Zhang #define regGDS_GS_1 0x2427 7369f33ac92fSHawking Zhang #define regGDS_GS_1_BASE_IDX 1 7370f33ac92fSHawking Zhang #define regGDS_GS_2 0x2428 7371f33ac92fSHawking Zhang #define regGDS_GS_2_BASE_IDX 1 7372f33ac92fSHawking Zhang #define regGDS_GS_3 0x2429 7373f33ac92fSHawking Zhang #define regGDS_GS_3_BASE_IDX 1 7374f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_NEEDED_0_LO 0x242a 7375f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_NEEDED_0_LO_BASE_IDX 1 7376f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_NEEDED_0_HI 0x242b 7377f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_NEEDED_0_HI_BASE_IDX 1 7378f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_WRITTEN_0_LO 0x242c 7379f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_WRITTEN_0_LO_BASE_IDX 1 7380f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_WRITTEN_0_HI 0x242d 7381f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_WRITTEN_0_HI_BASE_IDX 1 7382f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_NEEDED_1_LO 0x242e 7383f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_NEEDED_1_LO_BASE_IDX 1 7384f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_NEEDED_1_HI 0x242f 7385f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_NEEDED_1_HI_BASE_IDX 1 7386f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_WRITTEN_1_LO 0x2430 7387f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_WRITTEN_1_LO_BASE_IDX 1 7388f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_WRITTEN_1_HI 0x2431 7389f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_WRITTEN_1_HI_BASE_IDX 1 7390f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_NEEDED_2_LO 0x2432 7391f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_NEEDED_2_LO_BASE_IDX 1 7392f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_NEEDED_2_HI 0x2433 7393f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_NEEDED_2_HI_BASE_IDX 1 7394f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_WRITTEN_2_LO 0x2434 7395f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_WRITTEN_2_LO_BASE_IDX 1 7396f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_WRITTEN_2_HI 0x2435 7397f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_WRITTEN_2_HI_BASE_IDX 1 7398f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_NEEDED_3_LO 0x2436 7399f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_NEEDED_3_LO_BASE_IDX 1 7400f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_NEEDED_3_HI 0x2437 7401f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_NEEDED_3_HI_BASE_IDX 1 7402f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_WRITTEN_3_LO 0x2438 7403f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_WRITTEN_3_LO_BASE_IDX 1 7404f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_WRITTEN_3_HI 0x2439 7405f33ac92fSHawking Zhang #define regGDS_STRMOUT_PRIMS_WRITTEN_3_HI_BASE_IDX 1 7406f33ac92fSHawking Zhang #define regSPI_CONFIG_CNTL 0x2440 7407f33ac92fSHawking Zhang #define regSPI_CONFIG_CNTL_BASE_IDX 1 7408f33ac92fSHawking Zhang #define regSPI_CONFIG_CNTL_1 0x2441 7409f33ac92fSHawking Zhang #define regSPI_CONFIG_CNTL_1_BASE_IDX 1 7410f33ac92fSHawking Zhang #define regSPI_CONFIG_CNTL_2 0x2442 7411f33ac92fSHawking Zhang #define regSPI_CONFIG_CNTL_2_BASE_IDX 1 7412f33ac92fSHawking Zhang #define regSPI_WAVE_LIMIT_CNTL 0x2443 7413f33ac92fSHawking Zhang #define regSPI_WAVE_LIMIT_CNTL_BASE_IDX 1 7414f33ac92fSHawking Zhang #define regSPI_GS_THROTTLE_CNTL1 0x2444 7415f33ac92fSHawking Zhang #define regSPI_GS_THROTTLE_CNTL1_BASE_IDX 1 7416f33ac92fSHawking Zhang #define regSPI_GS_THROTTLE_CNTL2 0x2445 7417f33ac92fSHawking Zhang #define regSPI_GS_THROTTLE_CNTL2_BASE_IDX 1 7418f33ac92fSHawking Zhang #define regSPI_ATTRIBUTE_RING_BASE 0x2446 7419f33ac92fSHawking Zhang #define regSPI_ATTRIBUTE_RING_BASE_BASE_IDX 1 7420f33ac92fSHawking Zhang #define regSPI_ATTRIBUTE_RING_SIZE 0x2447 7421f33ac92fSHawking Zhang #define regSPI_ATTRIBUTE_RING_SIZE_BASE_IDX 1 7422f33ac92fSHawking Zhang 7423f33ac92fSHawking Zhang 7424f33ac92fSHawking Zhang // addressBlock: gc_cprs64dec 7425f33ac92fSHawking Zhang // base address: 0x32000 7426f33ac92fSHawking Zhang #define regCP_MES_PRGRM_CNTR_START 0x2800 7427f33ac92fSHawking Zhang #define regCP_MES_PRGRM_CNTR_START_BASE_IDX 1 7428f33ac92fSHawking Zhang #define regCP_MES_INTR_ROUTINE_START 0x2801 7429f33ac92fSHawking Zhang #define regCP_MES_INTR_ROUTINE_START_BASE_IDX 1 7430f33ac92fSHawking Zhang #define regCP_MES_MTVEC_LO 0x2801 7431f33ac92fSHawking Zhang #define regCP_MES_MTVEC_LO_BASE_IDX 1 7432f33ac92fSHawking Zhang #define regCP_MES_INTR_ROUTINE_START_HI 0x2802 7433f33ac92fSHawking Zhang #define regCP_MES_INTR_ROUTINE_START_HI_BASE_IDX 1 7434f33ac92fSHawking Zhang #define regCP_MES_MTVEC_HI 0x2802 7435f33ac92fSHawking Zhang #define regCP_MES_MTVEC_HI_BASE_IDX 1 7436f33ac92fSHawking Zhang #define regCP_MES_CNTL 0x2807 7437f33ac92fSHawking Zhang #define regCP_MES_CNTL_BASE_IDX 1 7438f33ac92fSHawking Zhang #define regCP_MES_PIPE_PRIORITY_CNTS 0x2808 7439f33ac92fSHawking Zhang #define regCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX 1 7440f33ac92fSHawking Zhang #define regCP_MES_PIPE0_PRIORITY 0x2809 7441f33ac92fSHawking Zhang #define regCP_MES_PIPE0_PRIORITY_BASE_IDX 1 7442f33ac92fSHawking Zhang #define regCP_MES_PIPE1_PRIORITY 0x280a 7443f33ac92fSHawking Zhang #define regCP_MES_PIPE1_PRIORITY_BASE_IDX 1 7444f33ac92fSHawking Zhang #define regCP_MES_PIPE2_PRIORITY 0x280b 7445f33ac92fSHawking Zhang #define regCP_MES_PIPE2_PRIORITY_BASE_IDX 1 7446f33ac92fSHawking Zhang #define regCP_MES_PIPE3_PRIORITY 0x280c 7447f33ac92fSHawking Zhang #define regCP_MES_PIPE3_PRIORITY_BASE_IDX 1 7448f33ac92fSHawking Zhang #define regCP_MES_HEADER_DUMP 0x280d 7449f33ac92fSHawking Zhang #define regCP_MES_HEADER_DUMP_BASE_IDX 1 7450f33ac92fSHawking Zhang #define regCP_MES_MIE_LO 0x280e 7451f33ac92fSHawking Zhang #define regCP_MES_MIE_LO_BASE_IDX 1 7452f33ac92fSHawking Zhang #define regCP_MES_MIE_HI 0x280f 7453f33ac92fSHawking Zhang #define regCP_MES_MIE_HI_BASE_IDX 1 7454f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT 0x2810 7455f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_BASE_IDX 1 7456f33ac92fSHawking Zhang #define regCP_MES_SCRATCH_INDEX 0x2811 7457f33ac92fSHawking Zhang #define regCP_MES_SCRATCH_INDEX_BASE_IDX 1 7458f33ac92fSHawking Zhang #define regCP_MES_SCRATCH_DATA 0x2812 7459f33ac92fSHawking Zhang #define regCP_MES_SCRATCH_DATA_BASE_IDX 1 7460f33ac92fSHawking Zhang #define regCP_MES_INSTR_PNTR 0x2813 7461f33ac92fSHawking Zhang #define regCP_MES_INSTR_PNTR_BASE_IDX 1 7462f33ac92fSHawking Zhang #define regCP_MES_MSCRATCH_HI 0x2814 7463f33ac92fSHawking Zhang #define regCP_MES_MSCRATCH_HI_BASE_IDX 1 7464f33ac92fSHawking Zhang #define regCP_MES_MSCRATCH_LO 0x2815 7465f33ac92fSHawking Zhang #define regCP_MES_MSCRATCH_LO_BASE_IDX 1 7466f33ac92fSHawking Zhang #define regCP_MES_MSTATUS_LO 0x2816 7467f33ac92fSHawking Zhang #define regCP_MES_MSTATUS_LO_BASE_IDX 1 7468f33ac92fSHawking Zhang #define regCP_MES_MSTATUS_HI 0x2817 7469f33ac92fSHawking Zhang #define regCP_MES_MSTATUS_HI_BASE_IDX 1 7470f33ac92fSHawking Zhang #define regCP_MES_MEPC_LO 0x2818 7471f33ac92fSHawking Zhang #define regCP_MES_MEPC_LO_BASE_IDX 1 7472f33ac92fSHawking Zhang #define regCP_MES_MEPC_HI 0x2819 7473f33ac92fSHawking Zhang #define regCP_MES_MEPC_HI_BASE_IDX 1 7474f33ac92fSHawking Zhang #define regCP_MES_MCAUSE_LO 0x281a 7475f33ac92fSHawking Zhang #define regCP_MES_MCAUSE_LO_BASE_IDX 1 7476f33ac92fSHawking Zhang #define regCP_MES_MCAUSE_HI 0x281b 7477f33ac92fSHawking Zhang #define regCP_MES_MCAUSE_HI_BASE_IDX 1 7478f33ac92fSHawking Zhang #define regCP_MES_MBADADDR_LO 0x281c 7479f33ac92fSHawking Zhang #define regCP_MES_MBADADDR_LO_BASE_IDX 1 7480f33ac92fSHawking Zhang #define regCP_MES_MBADADDR_HI 0x281d 7481f33ac92fSHawking Zhang #define regCP_MES_MBADADDR_HI_BASE_IDX 1 7482f33ac92fSHawking Zhang #define regCP_MES_MIP_LO 0x281e 7483f33ac92fSHawking Zhang #define regCP_MES_MIP_LO_BASE_IDX 1 7484f33ac92fSHawking Zhang #define regCP_MES_MIP_HI 0x281f 7485f33ac92fSHawking Zhang #define regCP_MES_MIP_HI_BASE_IDX 1 7486f33ac92fSHawking Zhang #define regCP_MES_IC_OP_CNTL 0x2820 7487f33ac92fSHawking Zhang #define regCP_MES_IC_OP_CNTL_BASE_IDX 1 7488f33ac92fSHawking Zhang #define regCP_MES_MCYCLE_LO 0x2826 7489f33ac92fSHawking Zhang #define regCP_MES_MCYCLE_LO_BASE_IDX 1 7490f33ac92fSHawking Zhang #define regCP_MES_MCYCLE_HI 0x2827 7491f33ac92fSHawking Zhang #define regCP_MES_MCYCLE_HI_BASE_IDX 1 7492f33ac92fSHawking Zhang #define regCP_MES_MTIME_LO 0x2828 7493f33ac92fSHawking Zhang #define regCP_MES_MTIME_LO_BASE_IDX 1 7494f33ac92fSHawking Zhang #define regCP_MES_MTIME_HI 0x2829 7495f33ac92fSHawking Zhang #define regCP_MES_MTIME_HI_BASE_IDX 1 7496f33ac92fSHawking Zhang #define regCP_MES_MINSTRET_LO 0x282a 7497f33ac92fSHawking Zhang #define regCP_MES_MINSTRET_LO_BASE_IDX 1 7498f33ac92fSHawking Zhang #define regCP_MES_MINSTRET_HI 0x282b 7499f33ac92fSHawking Zhang #define regCP_MES_MINSTRET_HI_BASE_IDX 1 7500f33ac92fSHawking Zhang #define regCP_MES_MISA_LO 0x282c 7501f33ac92fSHawking Zhang #define regCP_MES_MISA_LO_BASE_IDX 1 7502f33ac92fSHawking Zhang #define regCP_MES_MISA_HI 0x282d 7503f33ac92fSHawking Zhang #define regCP_MES_MISA_HI_BASE_IDX 1 7504f33ac92fSHawking Zhang #define regCP_MES_MVENDORID_LO 0x282e 7505f33ac92fSHawking Zhang #define regCP_MES_MVENDORID_LO_BASE_IDX 1 7506f33ac92fSHawking Zhang #define regCP_MES_MVENDORID_HI 0x282f 7507f33ac92fSHawking Zhang #define regCP_MES_MVENDORID_HI_BASE_IDX 1 7508f33ac92fSHawking Zhang #define regCP_MES_MARCHID_LO 0x2830 7509f33ac92fSHawking Zhang #define regCP_MES_MARCHID_LO_BASE_IDX 1 7510f33ac92fSHawking Zhang #define regCP_MES_MARCHID_HI 0x2831 7511f33ac92fSHawking Zhang #define regCP_MES_MARCHID_HI_BASE_IDX 1 7512f33ac92fSHawking Zhang #define regCP_MES_MIMPID_LO 0x2832 7513f33ac92fSHawking Zhang #define regCP_MES_MIMPID_LO_BASE_IDX 1 7514f33ac92fSHawking Zhang #define regCP_MES_MIMPID_HI 0x2833 7515f33ac92fSHawking Zhang #define regCP_MES_MIMPID_HI_BASE_IDX 1 7516f33ac92fSHawking Zhang #define regCP_MES_MHARTID_LO 0x2834 7517f33ac92fSHawking Zhang #define regCP_MES_MHARTID_LO_BASE_IDX 1 7518f33ac92fSHawking Zhang #define regCP_MES_MHARTID_HI 0x2835 7519f33ac92fSHawking Zhang #define regCP_MES_MHARTID_HI_BASE_IDX 1 7520f33ac92fSHawking Zhang #define regCP_MES_DC_BASE_CNTL 0x2836 7521f33ac92fSHawking Zhang #define regCP_MES_DC_BASE_CNTL_BASE_IDX 1 7522f33ac92fSHawking Zhang #define regCP_MES_DC_OP_CNTL 0x2837 7523f33ac92fSHawking Zhang #define regCP_MES_DC_OP_CNTL_BASE_IDX 1 7524f33ac92fSHawking Zhang #define regCP_MES_MTIMECMP_LO 0x2838 7525f33ac92fSHawking Zhang #define regCP_MES_MTIMECMP_LO_BASE_IDX 1 7526f33ac92fSHawking Zhang #define regCP_MES_MTIMECMP_HI 0x2839 7527f33ac92fSHawking Zhang #define regCP_MES_MTIMECMP_HI_BASE_IDX 1 7528f33ac92fSHawking Zhang #define regCP_MES_PROCESS_QUANTUM_PIPE0 0x283a 7529f33ac92fSHawking Zhang #define regCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX 1 7530f33ac92fSHawking Zhang #define regCP_MES_PROCESS_QUANTUM_PIPE1 0x283b 7531f33ac92fSHawking Zhang #define regCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX 1 7532f33ac92fSHawking Zhang #define regCP_MES_DOORBELL_CONTROL1 0x283c 7533f33ac92fSHawking Zhang #define regCP_MES_DOORBELL_CONTROL1_BASE_IDX 1 7534f33ac92fSHawking Zhang #define regCP_MES_DOORBELL_CONTROL2 0x283d 7535f33ac92fSHawking Zhang #define regCP_MES_DOORBELL_CONTROL2_BASE_IDX 1 7536f33ac92fSHawking Zhang #define regCP_MES_DOORBELL_CONTROL3 0x283e 7537f33ac92fSHawking Zhang #define regCP_MES_DOORBELL_CONTROL3_BASE_IDX 1 7538f33ac92fSHawking Zhang #define regCP_MES_DOORBELL_CONTROL4 0x283f 7539f33ac92fSHawking Zhang #define regCP_MES_DOORBELL_CONTROL4_BASE_IDX 1 7540f33ac92fSHawking Zhang #define regCP_MES_DOORBELL_CONTROL5 0x2840 7541f33ac92fSHawking Zhang #define regCP_MES_DOORBELL_CONTROL5_BASE_IDX 1 7542f33ac92fSHawking Zhang #define regCP_MES_DOORBELL_CONTROL6 0x2841 7543f33ac92fSHawking Zhang #define regCP_MES_DOORBELL_CONTROL6_BASE_IDX 1 7544f33ac92fSHawking Zhang #define regCP_MES_GP0_LO 0x2843 7545f33ac92fSHawking Zhang #define regCP_MES_GP0_LO_BASE_IDX 1 7546f33ac92fSHawking Zhang #define regCP_MES_GP0_HI 0x2844 7547f33ac92fSHawking Zhang #define regCP_MES_GP0_HI_BASE_IDX 1 7548f33ac92fSHawking Zhang #define regCP_MES_GP1_LO 0x2845 7549f33ac92fSHawking Zhang #define regCP_MES_GP1_LO_BASE_IDX 1 7550f33ac92fSHawking Zhang #define regCP_MES_GP1_HI 0x2846 7551f33ac92fSHawking Zhang #define regCP_MES_GP1_HI_BASE_IDX 1 7552f33ac92fSHawking Zhang #define regCP_MES_GP2_LO 0x2847 7553f33ac92fSHawking Zhang #define regCP_MES_GP2_LO_BASE_IDX 1 7554f33ac92fSHawking Zhang #define regCP_MES_GP2_HI 0x2848 7555f33ac92fSHawking Zhang #define regCP_MES_GP2_HI_BASE_IDX 1 7556f33ac92fSHawking Zhang #define regCP_MES_GP3_LO 0x2849 7557f33ac92fSHawking Zhang #define regCP_MES_GP3_LO_BASE_IDX 1 7558f33ac92fSHawking Zhang #define regCP_MES_GP3_HI 0x284a 7559f33ac92fSHawking Zhang #define regCP_MES_GP3_HI_BASE_IDX 1 7560f33ac92fSHawking Zhang #define regCP_MES_GP4_LO 0x284b 7561f33ac92fSHawking Zhang #define regCP_MES_GP4_LO_BASE_IDX 1 7562f33ac92fSHawking Zhang #define regCP_MES_GP4_HI 0x284c 7563f33ac92fSHawking Zhang #define regCP_MES_GP4_HI_BASE_IDX 1 7564f33ac92fSHawking Zhang #define regCP_MES_GP5_LO 0x284d 7565f33ac92fSHawking Zhang #define regCP_MES_GP5_LO_BASE_IDX 1 7566f33ac92fSHawking Zhang #define regCP_MES_GP5_HI 0x284e 7567f33ac92fSHawking Zhang #define regCP_MES_GP5_HI_BASE_IDX 1 7568f33ac92fSHawking Zhang #define regCP_MES_GP6_LO 0x284f 7569f33ac92fSHawking Zhang #define regCP_MES_GP6_LO_BASE_IDX 1 7570f33ac92fSHawking Zhang #define regCP_MES_GP6_HI 0x2850 7571f33ac92fSHawking Zhang #define regCP_MES_GP6_HI_BASE_IDX 1 7572f33ac92fSHawking Zhang #define regCP_MES_GP7_LO 0x2851 7573f33ac92fSHawking Zhang #define regCP_MES_GP7_LO_BASE_IDX 1 7574f33ac92fSHawking Zhang #define regCP_MES_GP7_HI 0x2852 7575f33ac92fSHawking Zhang #define regCP_MES_GP7_HI_BASE_IDX 1 7576f33ac92fSHawking Zhang #define regCP_MES_GP8_LO 0x2853 7577f33ac92fSHawking Zhang #define regCP_MES_GP8_LO_BASE_IDX 1 7578f33ac92fSHawking Zhang #define regCP_MES_GP8_HI 0x2854 7579f33ac92fSHawking Zhang #define regCP_MES_GP8_HI_BASE_IDX 1 7580f33ac92fSHawking Zhang #define regCP_MES_GP9_LO 0x2855 7581f33ac92fSHawking Zhang #define regCP_MES_GP9_LO_BASE_IDX 1 7582f33ac92fSHawking Zhang #define regCP_MES_GP9_HI 0x2856 7583f33ac92fSHawking Zhang #define regCP_MES_GP9_HI_BASE_IDX 1 7584f33ac92fSHawking Zhang #define regCP_MES_LOCAL_BASE0_LO 0x2883 7585f33ac92fSHawking Zhang #define regCP_MES_LOCAL_BASE0_LO_BASE_IDX 1 7586f33ac92fSHawking Zhang #define regCP_MES_LOCAL_BASE0_HI 0x2884 7587f33ac92fSHawking Zhang #define regCP_MES_LOCAL_BASE0_HI_BASE_IDX 1 7588f33ac92fSHawking Zhang #define regCP_MES_LOCAL_MASK0_LO 0x2885 7589f33ac92fSHawking Zhang #define regCP_MES_LOCAL_MASK0_LO_BASE_IDX 1 7590f33ac92fSHawking Zhang #define regCP_MES_LOCAL_MASK0_HI 0x2886 7591f33ac92fSHawking Zhang #define regCP_MES_LOCAL_MASK0_HI_BASE_IDX 1 7592f33ac92fSHawking Zhang #define regCP_MES_LOCAL_APERTURE 0x2887 7593f33ac92fSHawking Zhang #define regCP_MES_LOCAL_APERTURE_BASE_IDX 1 7594f33ac92fSHawking Zhang #define regCP_MES_LOCAL_INSTR_BASE_LO 0x2888 7595f33ac92fSHawking Zhang #define regCP_MES_LOCAL_INSTR_BASE_LO_BASE_IDX 1 7596f33ac92fSHawking Zhang #define regCP_MES_LOCAL_INSTR_BASE_HI 0x2889 7597f33ac92fSHawking Zhang #define regCP_MES_LOCAL_INSTR_BASE_HI_BASE_IDX 1 7598f33ac92fSHawking Zhang #define regCP_MES_LOCAL_INSTR_MASK_LO 0x288a 7599f33ac92fSHawking Zhang #define regCP_MES_LOCAL_INSTR_MASK_LO_BASE_IDX 1 7600f33ac92fSHawking Zhang #define regCP_MES_LOCAL_INSTR_MASK_HI 0x288b 7601f33ac92fSHawking Zhang #define regCP_MES_LOCAL_INSTR_MASK_HI_BASE_IDX 1 7602f33ac92fSHawking Zhang #define regCP_MES_LOCAL_INSTR_APERTURE 0x288c 7603f33ac92fSHawking Zhang #define regCP_MES_LOCAL_INSTR_APERTURE_BASE_IDX 1 7604f33ac92fSHawking Zhang #define regCP_MES_LOCAL_SCRATCH_APERTURE 0x288d 7605f33ac92fSHawking Zhang #define regCP_MES_LOCAL_SCRATCH_APERTURE_BASE_IDX 1 7606f33ac92fSHawking Zhang #define regCP_MES_LOCAL_SCRATCH_BASE_LO 0x288e 7607f33ac92fSHawking Zhang #define regCP_MES_LOCAL_SCRATCH_BASE_LO_BASE_IDX 1 7608f33ac92fSHawking Zhang #define regCP_MES_LOCAL_SCRATCH_BASE_HI 0x288f 7609f33ac92fSHawking Zhang #define regCP_MES_LOCAL_SCRATCH_BASE_HI_BASE_IDX 1 7610f33ac92fSHawking Zhang #define regCP_MES_PERFCOUNT_CNTL 0x2899 7611f33ac92fSHawking Zhang #define regCP_MES_PERFCOUNT_CNTL_BASE_IDX 1 7612f33ac92fSHawking Zhang #define regCP_MES_PENDING_INTERRUPT 0x289a 7613f33ac92fSHawking Zhang #define regCP_MES_PENDING_INTERRUPT_BASE_IDX 1 7614f33ac92fSHawking Zhang #define regCP_MES_PRGRM_CNTR_START_HI 0x289d 7615f33ac92fSHawking Zhang #define regCP_MES_PRGRM_CNTR_START_HI_BASE_IDX 1 7616f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_16 0x289f 7617f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_16_BASE_IDX 1 7618f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_17 0x28a0 7619f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_17_BASE_IDX 1 7620f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_18 0x28a1 7621f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_18_BASE_IDX 1 7622f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_19 0x28a2 7623f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_19_BASE_IDX 1 7624f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_20 0x28a3 7625f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_20_BASE_IDX 1 7626f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_21 0x28a4 7627f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_21_BASE_IDX 1 7628f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_22 0x28a5 7629f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_22_BASE_IDX 1 7630f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_23 0x28a6 7631f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_23_BASE_IDX 1 7632f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_24 0x28a7 7633f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_24_BASE_IDX 1 7634f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_25 0x28a8 7635f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_25_BASE_IDX 1 7636f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_26 0x28a9 7637f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_26_BASE_IDX 1 7638f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_27 0x28aa 7639f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_27_BASE_IDX 1 7640f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_28 0x28ab 7641f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_28_BASE_IDX 1 7642f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_29 0x28ac 7643f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_29_BASE_IDX 1 7644f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_30 0x28ad 7645f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_30_BASE_IDX 1 7646f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_31 0x28ae 7647f33ac92fSHawking Zhang #define regCP_MES_INTERRUPT_DATA_31_BASE_IDX 1 7648f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE0_BASE 0x28af 7649f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE0_BASE_BASE_IDX 1 7650f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE0_MASK 0x28b0 7651f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE0_MASK_BASE_IDX 1 7652f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE0_CNTL 0x28b1 7653f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE0_CNTL_BASE_IDX 1 7654f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE1_BASE 0x28b2 7655f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE1_BASE_BASE_IDX 1 7656f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE1_MASK 0x28b3 7657f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE1_MASK_BASE_IDX 1 7658f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE1_CNTL 0x28b4 7659f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE1_CNTL_BASE_IDX 1 7660f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE2_BASE 0x28b5 7661f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE2_BASE_BASE_IDX 1 7662f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE2_MASK 0x28b6 7663f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE2_MASK_BASE_IDX 1 7664f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE2_CNTL 0x28b7 7665f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE2_CNTL_BASE_IDX 1 7666f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE3_BASE 0x28b8 7667f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE3_BASE_BASE_IDX 1 7668f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE3_MASK 0x28b9 7669f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE3_MASK_BASE_IDX 1 7670f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE3_CNTL 0x28ba 7671f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE3_CNTL_BASE_IDX 1 7672f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE4_BASE 0x28bb 7673f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE4_BASE_BASE_IDX 1 7674f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE4_MASK 0x28bc 7675f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE4_MASK_BASE_IDX 1 7676f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE4_CNTL 0x28bd 7677f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE4_CNTL_BASE_IDX 1 7678f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE5_BASE 0x28be 7679f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE5_BASE_BASE_IDX 1 7680f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE5_MASK 0x28bf 7681f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE5_MASK_BASE_IDX 1 7682f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE5_CNTL 0x28c0 7683f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE5_CNTL_BASE_IDX 1 7684f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE6_BASE 0x28c1 7685f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE6_BASE_BASE_IDX 1 7686f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE6_MASK 0x28c2 7687f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE6_MASK_BASE_IDX 1 7688f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE6_CNTL 0x28c3 7689f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE6_CNTL_BASE_IDX 1 7690f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE7_BASE 0x28c4 7691f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE7_BASE_BASE_IDX 1 7692f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE7_MASK 0x28c5 7693f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE7_MASK_BASE_IDX 1 7694f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE7_CNTL 0x28c6 7695f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE7_CNTL_BASE_IDX 1 7696f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE8_BASE 0x28c7 7697f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE8_BASE_BASE_IDX 1 7698f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE8_MASK 0x28c8 7699f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE8_MASK_BASE_IDX 1 7700f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE8_CNTL 0x28c9 7701f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE8_CNTL_BASE_IDX 1 7702f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE9_BASE 0x28ca 7703f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE9_BASE_BASE_IDX 1 7704f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE9_MASK 0x28cb 7705f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE9_MASK_BASE_IDX 1 7706f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE9_CNTL 0x28cc 7707f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE9_CNTL_BASE_IDX 1 7708f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE10_BASE 0x28cd 7709f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE10_BASE_BASE_IDX 1 7710f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE10_MASK 0x28ce 7711f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE10_MASK_BASE_IDX 1 7712f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE10_CNTL 0x28cf 7713f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE10_CNTL_BASE_IDX 1 7714f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE11_BASE 0x28d0 7715f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE11_BASE_BASE_IDX 1 7716f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE11_MASK 0x28d1 7717f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE11_MASK_BASE_IDX 1 7718f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE11_CNTL 0x28d2 7719f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE11_CNTL_BASE_IDX 1 7720f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE12_BASE 0x28d3 7721f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE12_BASE_BASE_IDX 1 7722f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE12_MASK 0x28d4 7723f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE12_MASK_BASE_IDX 1 7724f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE12_CNTL 0x28d5 7725f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE12_CNTL_BASE_IDX 1 7726f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE13_BASE 0x28d6 7727f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE13_BASE_BASE_IDX 1 7728f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE13_MASK 0x28d7 7729f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE13_MASK_BASE_IDX 1 7730f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE13_CNTL 0x28d8 7731f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE13_CNTL_BASE_IDX 1 7732f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE14_BASE 0x28d9 7733f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE14_BASE_BASE_IDX 1 7734f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE14_MASK 0x28da 7735f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE14_MASK_BASE_IDX 1 7736f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE14_CNTL 0x28db 7737f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE14_CNTL_BASE_IDX 1 7738f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE15_BASE 0x28dc 7739f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE15_BASE_BASE_IDX 1 7740f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE15_MASK 0x28dd 7741f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE15_MASK_BASE_IDX 1 7742f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE15_CNTL 0x28de 7743f33ac92fSHawking Zhang #define regCP_MES_DC_APERTURE15_CNTL_BASE_IDX 1 7744f33ac92fSHawking Zhang #define regCP_MEC_RS64_PRGRM_CNTR_START 0x2900 7745f33ac92fSHawking Zhang #define regCP_MEC_RS64_PRGRM_CNTR_START_BASE_IDX 1 7746f33ac92fSHawking Zhang #define regCP_MEC_MTVEC_LO 0x2901 7747f33ac92fSHawking Zhang #define regCP_MEC_MTVEC_LO_BASE_IDX 1 7748f33ac92fSHawking Zhang #define regCP_MEC_MTVEC_HI 0x2902 7749f33ac92fSHawking Zhang #define regCP_MEC_MTVEC_HI_BASE_IDX 1 7750f33ac92fSHawking Zhang #define regCP_MEC_ISA_CNTL 0x2903 7751f33ac92fSHawking Zhang #define regCP_MEC_ISA_CNTL_BASE_IDX 1 7752f33ac92fSHawking Zhang #define regCP_MEC_RS64_CNTL 0x2904 7753f33ac92fSHawking Zhang #define regCP_MEC_RS64_CNTL_BASE_IDX 1 7754f33ac92fSHawking Zhang #define regCP_MEC_MIE_LO 0x2905 7755f33ac92fSHawking Zhang #define regCP_MEC_MIE_LO_BASE_IDX 1 7756f33ac92fSHawking Zhang #define regCP_MEC_MIE_HI 0x2906 7757f33ac92fSHawking Zhang #define regCP_MEC_MIE_HI_BASE_IDX 1 7758f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT 0x2907 7759f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_BASE_IDX 1 7760f33ac92fSHawking Zhang #define regCP_MEC_RS64_INSTR_PNTR 0x2908 7761f33ac92fSHawking Zhang #define regCP_MEC_RS64_INSTR_PNTR_BASE_IDX 1 7762f33ac92fSHawking Zhang #define regCP_MEC_MIP_LO 0x2909 7763f33ac92fSHawking Zhang #define regCP_MEC_MIP_LO_BASE_IDX 1 7764f33ac92fSHawking Zhang #define regCP_MEC_MIP_HI 0x290a 7765f33ac92fSHawking Zhang #define regCP_MEC_MIP_HI_BASE_IDX 1 7766f33ac92fSHawking Zhang #define regCP_MEC_DC_BASE_CNTL 0x290b 7767f33ac92fSHawking Zhang #define regCP_MEC_DC_BASE_CNTL_BASE_IDX 1 7768f33ac92fSHawking Zhang #define regCP_MEC_DC_OP_CNTL 0x290c 7769f33ac92fSHawking Zhang #define regCP_MEC_DC_OP_CNTL_BASE_IDX 1 7770f33ac92fSHawking Zhang #define regCP_MEC_MTIMECMP_LO 0x290d 7771f33ac92fSHawking Zhang #define regCP_MEC_MTIMECMP_LO_BASE_IDX 1 7772f33ac92fSHawking Zhang #define regCP_MEC_MTIMECMP_HI 0x290e 7773f33ac92fSHawking Zhang #define regCP_MEC_MTIMECMP_HI_BASE_IDX 1 7774f33ac92fSHawking Zhang #define regCP_MEC_GP0_LO 0x2910 7775f33ac92fSHawking Zhang #define regCP_MEC_GP0_LO_BASE_IDX 1 7776f33ac92fSHawking Zhang #define regCP_MEC_GP0_HI 0x2911 7777f33ac92fSHawking Zhang #define regCP_MEC_GP0_HI_BASE_IDX 1 7778f33ac92fSHawking Zhang #define regCP_MEC_GP1_LO 0x2912 7779f33ac92fSHawking Zhang #define regCP_MEC_GP1_LO_BASE_IDX 1 7780f33ac92fSHawking Zhang #define regCP_MEC_GP1_HI 0x2913 7781f33ac92fSHawking Zhang #define regCP_MEC_GP1_HI_BASE_IDX 1 7782f33ac92fSHawking Zhang #define regCP_MEC_GP2_LO 0x2914 7783f33ac92fSHawking Zhang #define regCP_MEC_GP2_LO_BASE_IDX 1 7784f33ac92fSHawking Zhang #define regCP_MEC_GP2_HI 0x2915 7785f33ac92fSHawking Zhang #define regCP_MEC_GP2_HI_BASE_IDX 1 7786f33ac92fSHawking Zhang #define regCP_MEC_GP3_LO 0x2916 7787f33ac92fSHawking Zhang #define regCP_MEC_GP3_LO_BASE_IDX 1 7788f33ac92fSHawking Zhang #define regCP_MEC_GP3_HI 0x2917 7789f33ac92fSHawking Zhang #define regCP_MEC_GP3_HI_BASE_IDX 1 7790f33ac92fSHawking Zhang #define regCP_MEC_GP4_LO 0x2918 7791f33ac92fSHawking Zhang #define regCP_MEC_GP4_LO_BASE_IDX 1 7792f33ac92fSHawking Zhang #define regCP_MEC_GP4_HI 0x2919 7793f33ac92fSHawking Zhang #define regCP_MEC_GP4_HI_BASE_IDX 1 7794f33ac92fSHawking Zhang #define regCP_MEC_GP5_LO 0x291a 7795f33ac92fSHawking Zhang #define regCP_MEC_GP5_LO_BASE_IDX 1 7796f33ac92fSHawking Zhang #define regCP_MEC_GP5_HI 0x291b 7797f33ac92fSHawking Zhang #define regCP_MEC_GP5_HI_BASE_IDX 1 7798f33ac92fSHawking Zhang #define regCP_MEC_GP6_LO 0x291c 7799f33ac92fSHawking Zhang #define regCP_MEC_GP6_LO_BASE_IDX 1 7800f33ac92fSHawking Zhang #define regCP_MEC_GP6_HI 0x291d 7801f33ac92fSHawking Zhang #define regCP_MEC_GP6_HI_BASE_IDX 1 7802f33ac92fSHawking Zhang #define regCP_MEC_GP7_LO 0x291e 7803f33ac92fSHawking Zhang #define regCP_MEC_GP7_LO_BASE_IDX 1 7804f33ac92fSHawking Zhang #define regCP_MEC_GP7_HI 0x291f 7805f33ac92fSHawking Zhang #define regCP_MEC_GP7_HI_BASE_IDX 1 7806f33ac92fSHawking Zhang #define regCP_MEC_GP8_LO 0x2920 7807f33ac92fSHawking Zhang #define regCP_MEC_GP8_LO_BASE_IDX 1 7808f33ac92fSHawking Zhang #define regCP_MEC_GP8_HI 0x2921 7809f33ac92fSHawking Zhang #define regCP_MEC_GP8_HI_BASE_IDX 1 7810f33ac92fSHawking Zhang #define regCP_MEC_GP9_LO 0x2922 7811f33ac92fSHawking Zhang #define regCP_MEC_GP9_LO_BASE_IDX 1 7812f33ac92fSHawking Zhang #define regCP_MEC_GP9_HI 0x2923 7813f33ac92fSHawking Zhang #define regCP_MEC_GP9_HI_BASE_IDX 1 7814f33ac92fSHawking Zhang #define regCP_MEC_LOCAL_BASE0_LO 0x2927 7815f33ac92fSHawking Zhang #define regCP_MEC_LOCAL_BASE0_LO_BASE_IDX 1 7816f33ac92fSHawking Zhang #define regCP_MEC_LOCAL_BASE0_HI 0x2928 7817f33ac92fSHawking Zhang #define regCP_MEC_LOCAL_BASE0_HI_BASE_IDX 1 7818f33ac92fSHawking Zhang #define regCP_MEC_LOCAL_MASK0_LO 0x2929 7819f33ac92fSHawking Zhang #define regCP_MEC_LOCAL_MASK0_LO_BASE_IDX 1 7820f33ac92fSHawking Zhang #define regCP_MEC_LOCAL_MASK0_HI 0x292a 7821f33ac92fSHawking Zhang #define regCP_MEC_LOCAL_MASK0_HI_BASE_IDX 1 7822f33ac92fSHawking Zhang #define regCP_MEC_LOCAL_APERTURE 0x292b 7823f33ac92fSHawking Zhang #define regCP_MEC_LOCAL_APERTURE_BASE_IDX 1 7824f33ac92fSHawking Zhang #define regCP_MEC_LOCAL_INSTR_BASE_LO 0x292c 7825f33ac92fSHawking Zhang #define regCP_MEC_LOCAL_INSTR_BASE_LO_BASE_IDX 1 7826f33ac92fSHawking Zhang #define regCP_MEC_LOCAL_INSTR_BASE_HI 0x292d 7827f33ac92fSHawking Zhang #define regCP_MEC_LOCAL_INSTR_BASE_HI_BASE_IDX 1 7828f33ac92fSHawking Zhang #define regCP_MEC_LOCAL_INSTR_MASK_LO 0x292e 7829f33ac92fSHawking Zhang #define regCP_MEC_LOCAL_INSTR_MASK_LO_BASE_IDX 1 7830f33ac92fSHawking Zhang #define regCP_MEC_LOCAL_INSTR_MASK_HI 0x292f 7831f33ac92fSHawking Zhang #define regCP_MEC_LOCAL_INSTR_MASK_HI_BASE_IDX 1 7832f33ac92fSHawking Zhang #define regCP_MEC_LOCAL_INSTR_APERTURE 0x2930 7833f33ac92fSHawking Zhang #define regCP_MEC_LOCAL_INSTR_APERTURE_BASE_IDX 1 7834f33ac92fSHawking Zhang #define regCP_MEC_LOCAL_SCRATCH_APERTURE 0x2931 7835f33ac92fSHawking Zhang #define regCP_MEC_LOCAL_SCRATCH_APERTURE_BASE_IDX 1 7836f33ac92fSHawking Zhang #define regCP_MEC_LOCAL_SCRATCH_BASE_LO 0x2932 7837f33ac92fSHawking Zhang #define regCP_MEC_LOCAL_SCRATCH_BASE_LO_BASE_IDX 1 7838f33ac92fSHawking Zhang #define regCP_MEC_LOCAL_SCRATCH_BASE_HI 0x2933 7839f33ac92fSHawking Zhang #define regCP_MEC_LOCAL_SCRATCH_BASE_HI_BASE_IDX 1 7840f33ac92fSHawking Zhang #define regCP_MEC_RS64_PERFCOUNT_CNTL 0x2934 7841f33ac92fSHawking Zhang #define regCP_MEC_RS64_PERFCOUNT_CNTL_BASE_IDX 1 7842f33ac92fSHawking Zhang #define regCP_MEC_RS64_PENDING_INTERRUPT 0x2935 7843f33ac92fSHawking Zhang #define regCP_MEC_RS64_PENDING_INTERRUPT_BASE_IDX 1 7844f33ac92fSHawking Zhang #define regCP_MEC_RS64_PRGRM_CNTR_START_HI 0x2938 7845f33ac92fSHawking Zhang #define regCP_MEC_RS64_PRGRM_CNTR_START_HI_BASE_IDX 1 7846f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_16 0x293a 7847f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_16_BASE_IDX 1 7848f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_17 0x293b 7849f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_17_BASE_IDX 1 7850f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_18 0x293c 7851f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_18_BASE_IDX 1 7852f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_19 0x293d 7853f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_19_BASE_IDX 1 7854f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_20 0x293e 7855f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_20_BASE_IDX 1 7856f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_21 0x293f 7857f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_21_BASE_IDX 1 7858f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_22 0x2940 7859f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_22_BASE_IDX 1 7860f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_23 0x2941 7861f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_23_BASE_IDX 1 7862f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_24 0x2942 7863f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_24_BASE_IDX 1 7864f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_25 0x2943 7865f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_25_BASE_IDX 1 7866f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_26 0x2944 7867f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_26_BASE_IDX 1 7868f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_27 0x2945 7869f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_27_BASE_IDX 1 7870f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_28 0x2946 7871f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_28_BASE_IDX 1 7872f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_29 0x2947 7873f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_29_BASE_IDX 1 7874f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_30 0x2948 7875f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_30_BASE_IDX 1 7876f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_31 0x2949 7877f33ac92fSHawking Zhang #define regCP_MEC_RS64_INTERRUPT_DATA_31_BASE_IDX 1 7878f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE0_BASE 0x294a 7879f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE0_BASE_BASE_IDX 1 7880f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE0_MASK 0x294b 7881f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE0_MASK_BASE_IDX 1 7882f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE0_CNTL 0x294c 7883f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE0_CNTL_BASE_IDX 1 7884f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE1_BASE 0x294d 7885f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE1_BASE_BASE_IDX 1 7886f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE1_MASK 0x294e 7887f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE1_MASK_BASE_IDX 1 7888f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE1_CNTL 0x294f 7889f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE1_CNTL_BASE_IDX 1 7890f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE2_BASE 0x2950 7891f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE2_BASE_BASE_IDX 1 7892f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE2_MASK 0x2951 7893f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE2_MASK_BASE_IDX 1 7894f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE2_CNTL 0x2952 7895f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE2_CNTL_BASE_IDX 1 7896f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE3_BASE 0x2953 7897f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE3_BASE_BASE_IDX 1 7898f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE3_MASK 0x2954 7899f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE3_MASK_BASE_IDX 1 7900f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE3_CNTL 0x2955 7901f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE3_CNTL_BASE_IDX 1 7902f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE4_BASE 0x2956 7903f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE4_BASE_BASE_IDX 1 7904f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE4_MASK 0x2957 7905f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE4_MASK_BASE_IDX 1 7906f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE4_CNTL 0x2958 7907f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE4_CNTL_BASE_IDX 1 7908f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE5_BASE 0x2959 7909f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE5_BASE_BASE_IDX 1 7910f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE5_MASK 0x295a 7911f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE5_MASK_BASE_IDX 1 7912f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE5_CNTL 0x295b 7913f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE5_CNTL_BASE_IDX 1 7914f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE6_BASE 0x295c 7915f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE6_BASE_BASE_IDX 1 7916f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE6_MASK 0x295d 7917f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE6_MASK_BASE_IDX 1 7918f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE6_CNTL 0x295e 7919f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE6_CNTL_BASE_IDX 1 7920f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE7_BASE 0x295f 7921f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE7_BASE_BASE_IDX 1 7922f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE7_MASK 0x2960 7923f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE7_MASK_BASE_IDX 1 7924f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE7_CNTL 0x2961 7925f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE7_CNTL_BASE_IDX 1 7926f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE8_BASE 0x2962 7927f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE8_BASE_BASE_IDX 1 7928f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE8_MASK 0x2963 7929f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE8_MASK_BASE_IDX 1 7930f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE8_CNTL 0x2964 7931f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE8_CNTL_BASE_IDX 1 7932f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE9_BASE 0x2965 7933f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE9_BASE_BASE_IDX 1 7934f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE9_MASK 0x2966 7935f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE9_MASK_BASE_IDX 1 7936f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE9_CNTL 0x2967 7937f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE9_CNTL_BASE_IDX 1 7938f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE10_BASE 0x2968 7939f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE10_BASE_BASE_IDX 1 7940f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE10_MASK 0x2969 7941f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE10_MASK_BASE_IDX 1 7942f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE10_CNTL 0x296a 7943f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE10_CNTL_BASE_IDX 1 7944f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE11_BASE 0x296b 7945f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE11_BASE_BASE_IDX 1 7946f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE11_MASK 0x296c 7947f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE11_MASK_BASE_IDX 1 7948f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE11_CNTL 0x296d 7949f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE11_CNTL_BASE_IDX 1 7950f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE12_BASE 0x296e 7951f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE12_BASE_BASE_IDX 1 7952f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE12_MASK 0x296f 7953f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE12_MASK_BASE_IDX 1 7954f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE12_CNTL 0x2970 7955f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE12_CNTL_BASE_IDX 1 7956f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE13_BASE 0x2971 7957f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE13_BASE_BASE_IDX 1 7958f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE13_MASK 0x2972 7959f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE13_MASK_BASE_IDX 1 7960f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE13_CNTL 0x2973 7961f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE13_CNTL_BASE_IDX 1 7962f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE14_BASE 0x2974 7963f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE14_BASE_BASE_IDX 1 7964f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE14_MASK 0x2975 7965f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE14_MASK_BASE_IDX 1 7966f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE14_CNTL 0x2976 7967f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE14_CNTL_BASE_IDX 1 7968f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE15_BASE 0x2977 7969f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE15_BASE_BASE_IDX 1 7970f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE15_MASK 0x2978 7971f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE15_MASK_BASE_IDX 1 7972f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE15_CNTL 0x2979 7973f33ac92fSHawking Zhang #define regCP_MEC_DC_APERTURE15_CNTL_BASE_IDX 1 7974f33ac92fSHawking Zhang #define regCP_CPC_IC_OP_CNTL 0x297a 7975f33ac92fSHawking Zhang #define regCP_CPC_IC_OP_CNTL_BASE_IDX 1 7976f33ac92fSHawking Zhang #define regCP_GFX_CNTL 0x2a00 7977f33ac92fSHawking Zhang #define regCP_GFX_CNTL_BASE_IDX 1 7978f33ac92fSHawking Zhang #define regCP_GFX_RS64_INTERRUPT0 0x2a01 7979f33ac92fSHawking Zhang #define regCP_GFX_RS64_INTERRUPT0_BASE_IDX 1 7980f33ac92fSHawking Zhang #define regCP_GFX_RS64_INTR_EN0 0x2a02 7981f33ac92fSHawking Zhang #define regCP_GFX_RS64_INTR_EN0_BASE_IDX 1 7982f33ac92fSHawking Zhang #define regCP_GFX_RS64_INTR_EN1 0x2a03 7983f33ac92fSHawking Zhang #define regCP_GFX_RS64_INTR_EN1_BASE_IDX 1 7984f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_BASE_CNTL 0x2a08 7985f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_BASE_CNTL_BASE_IDX 1 7986f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_OP_CNTL 0x2a09 7987f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_OP_CNTL_BASE_IDX 1 7988f33ac92fSHawking Zhang #define regCP_GFX_RS64_LOCAL_BASE0_LO 0x2a0a 7989f33ac92fSHawking Zhang #define regCP_GFX_RS64_LOCAL_BASE0_LO_BASE_IDX 1 7990f33ac92fSHawking Zhang #define regCP_GFX_RS64_LOCAL_BASE0_HI 0x2a0b 7991f33ac92fSHawking Zhang #define regCP_GFX_RS64_LOCAL_BASE0_HI_BASE_IDX 1 7992f33ac92fSHawking Zhang #define regCP_GFX_RS64_LOCAL_MASK0_LO 0x2a0c 7993f33ac92fSHawking Zhang #define regCP_GFX_RS64_LOCAL_MASK0_LO_BASE_IDX 1 7994f33ac92fSHawking Zhang #define regCP_GFX_RS64_LOCAL_MASK0_HI 0x2a0d 7995f33ac92fSHawking Zhang #define regCP_GFX_RS64_LOCAL_MASK0_HI_BASE_IDX 1 7996f33ac92fSHawking Zhang #define regCP_GFX_RS64_LOCAL_APERTURE 0x2a0e 7997f33ac92fSHawking Zhang #define regCP_GFX_RS64_LOCAL_APERTURE_BASE_IDX 1 7998f33ac92fSHawking Zhang #define regCP_GFX_RS64_LOCAL_INSTR_BASE_LO 0x2a0f 7999f33ac92fSHawking Zhang #define regCP_GFX_RS64_LOCAL_INSTR_BASE_LO_BASE_IDX 1 8000f33ac92fSHawking Zhang #define regCP_GFX_RS64_LOCAL_INSTR_BASE_HI 0x2a10 8001f33ac92fSHawking Zhang #define regCP_GFX_RS64_LOCAL_INSTR_BASE_HI_BASE_IDX 1 8002f33ac92fSHawking Zhang #define regCP_GFX_RS64_LOCAL_INSTR_MASK_LO 0x2a11 8003f33ac92fSHawking Zhang #define regCP_GFX_RS64_LOCAL_INSTR_MASK_LO_BASE_IDX 1 8004f33ac92fSHawking Zhang #define regCP_GFX_RS64_LOCAL_INSTR_MASK_HI 0x2a12 8005f33ac92fSHawking Zhang #define regCP_GFX_RS64_LOCAL_INSTR_MASK_HI_BASE_IDX 1 8006f33ac92fSHawking Zhang #define regCP_GFX_RS64_LOCAL_INSTR_APERTURE 0x2a13 8007f33ac92fSHawking Zhang #define regCP_GFX_RS64_LOCAL_INSTR_APERTURE_BASE_IDX 1 8008f33ac92fSHawking Zhang #define regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE 0x2a14 8009f33ac92fSHawking Zhang #define regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE_BASE_IDX 1 8010f33ac92fSHawking Zhang #define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO 0x2a15 8011f33ac92fSHawking Zhang #define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO_BASE_IDX 1 8012f33ac92fSHawking Zhang #define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI 0x2a16 8013f33ac92fSHawking Zhang #define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI_BASE_IDX 1 8014f33ac92fSHawking Zhang #define regCP_GFX_RS64_PERFCOUNT_CNTL0 0x2a1a 8015f33ac92fSHawking Zhang #define regCP_GFX_RS64_PERFCOUNT_CNTL0_BASE_IDX 1 8016f33ac92fSHawking Zhang #define regCP_GFX_RS64_PERFCOUNT_CNTL1 0x2a1b 8017f33ac92fSHawking Zhang #define regCP_GFX_RS64_PERFCOUNT_CNTL1_BASE_IDX 1 8018f33ac92fSHawking Zhang #define regCP_GFX_RS64_MIP_LO0 0x2a1c 8019f33ac92fSHawking Zhang #define regCP_GFX_RS64_MIP_LO0_BASE_IDX 1 8020f33ac92fSHawking Zhang #define regCP_GFX_RS64_MIP_LO1 0x2a1d 8021f33ac92fSHawking Zhang #define regCP_GFX_RS64_MIP_LO1_BASE_IDX 1 8022f33ac92fSHawking Zhang #define regCP_GFX_RS64_MIP_HI0 0x2a1e 8023f33ac92fSHawking Zhang #define regCP_GFX_RS64_MIP_HI0_BASE_IDX 1 8024f33ac92fSHawking Zhang #define regCP_GFX_RS64_MIP_HI1 0x2a1f 8025f33ac92fSHawking Zhang #define regCP_GFX_RS64_MIP_HI1_BASE_IDX 1 8026f33ac92fSHawking Zhang #define regCP_GFX_RS64_MTIMECMP_LO0 0x2a20 8027f33ac92fSHawking Zhang #define regCP_GFX_RS64_MTIMECMP_LO0_BASE_IDX 1 8028f33ac92fSHawking Zhang #define regCP_GFX_RS64_MTIMECMP_LO1 0x2a21 8029f33ac92fSHawking Zhang #define regCP_GFX_RS64_MTIMECMP_LO1_BASE_IDX 1 8030f33ac92fSHawking Zhang #define regCP_GFX_RS64_MTIMECMP_HI0 0x2a22 8031f33ac92fSHawking Zhang #define regCP_GFX_RS64_MTIMECMP_HI0_BASE_IDX 1 8032f33ac92fSHawking Zhang #define regCP_GFX_RS64_MTIMECMP_HI1 0x2a23 8033f33ac92fSHawking Zhang #define regCP_GFX_RS64_MTIMECMP_HI1_BASE_IDX 1 8034f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP0_LO0 0x2a24 8035f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP0_LO0_BASE_IDX 1 8036f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP0_LO1 0x2a25 8037f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP0_LO1_BASE_IDX 1 8038f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP0_HI0 0x2a26 8039f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP0_HI0_BASE_IDX 1 8040f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP0_HI1 0x2a27 8041f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP0_HI1_BASE_IDX 1 8042f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP1_LO0 0x2a28 8043f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP1_LO0_BASE_IDX 1 8044f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP1_LO1 0x2a29 8045f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP1_LO1_BASE_IDX 1 8046f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP1_HI0 0x2a2a 8047f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP1_HI0_BASE_IDX 1 8048f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP1_HI1 0x2a2b 8049f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP1_HI1_BASE_IDX 1 8050f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP2_LO0 0x2a2c 8051f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP2_LO0_BASE_IDX 1 8052f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP2_LO1 0x2a2d 8053f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP2_LO1_BASE_IDX 1 8054f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP2_HI0 0x2a2e 8055f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP2_HI0_BASE_IDX 1 8056f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP2_HI1 0x2a2f 8057f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP2_HI1_BASE_IDX 1 8058f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP3_LO0 0x2a30 8059f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP3_LO0_BASE_IDX 1 8060f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP3_LO1 0x2a31 8061f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP3_LO1_BASE_IDX 1 8062f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP3_HI0 0x2a32 8063f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP3_HI0_BASE_IDX 1 8064f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP3_HI1 0x2a33 8065f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP3_HI1_BASE_IDX 1 8066f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP4_LO0 0x2a34 8067f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP4_LO0_BASE_IDX 1 8068f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP4_LO1 0x2a35 8069f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP4_LO1_BASE_IDX 1 8070f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP4_HI0 0x2a36 8071f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP4_HI0_BASE_IDX 1 8072f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP4_HI1 0x2a37 8073f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP4_HI1_BASE_IDX 1 8074f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP5_LO0 0x2a38 8075f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP5_LO0_BASE_IDX 1 8076f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP5_LO1 0x2a39 8077f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP5_LO1_BASE_IDX 1 8078f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP5_HI0 0x2a3a 8079f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP5_HI0_BASE_IDX 1 8080f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP5_HI1 0x2a3b 8081f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP5_HI1_BASE_IDX 1 8082f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP6_LO 0x2a3c 8083f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP6_LO_BASE_IDX 1 8084f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP6_HI 0x2a3d 8085f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP6_HI_BASE_IDX 1 8086f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP7_LO 0x2a3e 8087f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP7_LO_BASE_IDX 1 8088f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP7_HI 0x2a3f 8089f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP7_HI_BASE_IDX 1 8090f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP8_LO 0x2a40 8091f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP8_LO_BASE_IDX 1 8092f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP8_HI 0x2a41 8093f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP8_HI_BASE_IDX 1 8094f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP9_LO 0x2a42 8095f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP9_LO_BASE_IDX 1 8096f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP9_HI 0x2a43 8097f33ac92fSHawking Zhang #define regCP_GFX_RS64_GP9_HI_BASE_IDX 1 8098f33ac92fSHawking Zhang #define regCP_GFX_RS64_INSTR_PNTR0 0x2a44 8099f33ac92fSHawking Zhang #define regCP_GFX_RS64_INSTR_PNTR0_BASE_IDX 1 8100f33ac92fSHawking Zhang #define regCP_GFX_RS64_INSTR_PNTR1 0x2a45 8101f33ac92fSHawking Zhang #define regCP_GFX_RS64_INSTR_PNTR1_BASE_IDX 1 8102f33ac92fSHawking Zhang #define regCP_GFX_RS64_PENDING_INTERRUPT0 0x2a46 8103f33ac92fSHawking Zhang #define regCP_GFX_RS64_PENDING_INTERRUPT0_BASE_IDX 1 8104f33ac92fSHawking Zhang #define regCP_GFX_RS64_PENDING_INTERRUPT1 0x2a47 8105f33ac92fSHawking Zhang #define regCP_GFX_RS64_PENDING_INTERRUPT1_BASE_IDX 1 8106f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE0_BASE0 0x2a49 8107f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE0_BASE0_BASE_IDX 1 8108f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE0_MASK0 0x2a4a 8109f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE0_MASK0_BASE_IDX 1 8110f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE0_CNTL0 0x2a4b 8111f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE0_CNTL0_BASE_IDX 1 8112f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE1_BASE0 0x2a4c 8113f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE1_BASE0_BASE_IDX 1 8114f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE1_MASK0 0x2a4d 8115f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE1_MASK0_BASE_IDX 1 8116f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE1_CNTL0 0x2a4e 8117f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE1_CNTL0_BASE_IDX 1 8118f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE2_BASE0 0x2a4f 8119f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE2_BASE0_BASE_IDX 1 8120f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE2_MASK0 0x2a50 8121f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE2_MASK0_BASE_IDX 1 8122f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE2_CNTL0 0x2a51 8123f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE2_CNTL0_BASE_IDX 1 8124f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE3_BASE0 0x2a52 8125f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE3_BASE0_BASE_IDX 1 8126f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE3_MASK0 0x2a53 8127f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE3_MASK0_BASE_IDX 1 8128f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE3_CNTL0 0x2a54 8129f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE3_CNTL0_BASE_IDX 1 8130f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE4_BASE0 0x2a55 8131f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE4_BASE0_BASE_IDX 1 8132f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE4_MASK0 0x2a56 8133f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE4_MASK0_BASE_IDX 1 8134f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE4_CNTL0 0x2a57 8135f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE4_CNTL0_BASE_IDX 1 8136f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE5_BASE0 0x2a58 8137f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE5_BASE0_BASE_IDX 1 8138f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE5_MASK0 0x2a59 8139f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE5_MASK0_BASE_IDX 1 8140f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE5_CNTL0 0x2a5a 8141f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE5_CNTL0_BASE_IDX 1 8142f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE6_BASE0 0x2a5b 8143f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE6_BASE0_BASE_IDX 1 8144f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE6_MASK0 0x2a5c 8145f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE6_MASK0_BASE_IDX 1 8146f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE6_CNTL0 0x2a5d 8147f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE6_CNTL0_BASE_IDX 1 8148f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE7_BASE0 0x2a5e 8149f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE7_BASE0_BASE_IDX 1 8150f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE7_MASK0 0x2a5f 8151f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE7_MASK0_BASE_IDX 1 8152f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE7_CNTL0 0x2a60 8153f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE7_CNTL0_BASE_IDX 1 8154f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE8_BASE0 0x2a61 8155f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE8_BASE0_BASE_IDX 1 8156f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE8_MASK0 0x2a62 8157f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE8_MASK0_BASE_IDX 1 8158f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE8_CNTL0 0x2a63 8159f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE8_CNTL0_BASE_IDX 1 8160f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE9_BASE0 0x2a64 8161f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE9_BASE0_BASE_IDX 1 8162f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE9_MASK0 0x2a65 8163f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE9_MASK0_BASE_IDX 1 8164f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE9_CNTL0 0x2a66 8165f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE9_CNTL0_BASE_IDX 1 8166f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE10_BASE0 0x2a67 8167f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE10_BASE0_BASE_IDX 1 8168f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE10_MASK0 0x2a68 8169f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE10_MASK0_BASE_IDX 1 8170f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE10_CNTL0 0x2a69 8171f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE10_CNTL0_BASE_IDX 1 8172f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE11_BASE0 0x2a6a 8173f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE11_BASE0_BASE_IDX 1 8174f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE11_MASK0 0x2a6b 8175f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE11_MASK0_BASE_IDX 1 8176f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE11_CNTL0 0x2a6c 8177f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE11_CNTL0_BASE_IDX 1 8178f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE12_BASE0 0x2a6d 8179f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE12_BASE0_BASE_IDX 1 8180f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE12_MASK0 0x2a6e 8181f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE12_MASK0_BASE_IDX 1 8182f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE12_CNTL0 0x2a6f 8183f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE12_CNTL0_BASE_IDX 1 8184f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE13_BASE0 0x2a70 8185f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE13_BASE0_BASE_IDX 1 8186f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE13_MASK0 0x2a71 8187f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE13_MASK0_BASE_IDX 1 8188f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE13_CNTL0 0x2a72 8189f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE13_CNTL0_BASE_IDX 1 8190f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE14_BASE0 0x2a73 8191f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE14_BASE0_BASE_IDX 1 8192f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE14_MASK0 0x2a74 8193f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE14_MASK0_BASE_IDX 1 8194f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE14_CNTL0 0x2a75 8195f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE14_CNTL0_BASE_IDX 1 8196f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE15_BASE0 0x2a76 8197f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE15_BASE0_BASE_IDX 1 8198f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE15_MASK0 0x2a77 8199f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE15_MASK0_BASE_IDX 1 8200f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE15_CNTL0 0x2a78 8201f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE15_CNTL0_BASE_IDX 1 8202f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE0_BASE1 0x2a79 8203f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE0_BASE1_BASE_IDX 1 8204f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE0_MASK1 0x2a7a 8205f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE0_MASK1_BASE_IDX 1 8206f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE0_CNTL1 0x2a7b 8207f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE0_CNTL1_BASE_IDX 1 8208f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE1_BASE1 0x2a7c 8209f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE1_BASE1_BASE_IDX 1 8210f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE1_MASK1 0x2a7d 8211f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE1_MASK1_BASE_IDX 1 8212f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE1_CNTL1 0x2a7e 8213f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE1_CNTL1_BASE_IDX 1 8214f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE2_BASE1 0x2a7f 8215f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE2_BASE1_BASE_IDX 1 8216f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE2_MASK1 0x2a80 8217f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE2_MASK1_BASE_IDX 1 8218f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE2_CNTL1 0x2a81 8219f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE2_CNTL1_BASE_IDX 1 8220f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE3_BASE1 0x2a82 8221f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE3_BASE1_BASE_IDX 1 8222f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE3_MASK1 0x2a83 8223f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE3_MASK1_BASE_IDX 1 8224f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE3_CNTL1 0x2a84 8225f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE3_CNTL1_BASE_IDX 1 8226f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE4_BASE1 0x2a85 8227f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE4_BASE1_BASE_IDX 1 8228f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE4_MASK1 0x2a86 8229f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE4_MASK1_BASE_IDX 1 8230f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE4_CNTL1 0x2a87 8231f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE4_CNTL1_BASE_IDX 1 8232f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE5_BASE1 0x2a88 8233f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE5_BASE1_BASE_IDX 1 8234f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE5_MASK1 0x2a89 8235f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE5_MASK1_BASE_IDX 1 8236f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE5_CNTL1 0x2a8a 8237f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE5_CNTL1_BASE_IDX 1 8238f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE6_BASE1 0x2a8b 8239f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE6_BASE1_BASE_IDX 1 8240f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE6_MASK1 0x2a8c 8241f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE6_MASK1_BASE_IDX 1 8242f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE6_CNTL1 0x2a8d 8243f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE6_CNTL1_BASE_IDX 1 8244f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE7_BASE1 0x2a8e 8245f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE7_BASE1_BASE_IDX 1 8246f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE7_MASK1 0x2a8f 8247f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE7_MASK1_BASE_IDX 1 8248f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE7_CNTL1 0x2a90 8249f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE7_CNTL1_BASE_IDX 1 8250f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE8_BASE1 0x2a91 8251f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE8_BASE1_BASE_IDX 1 8252f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE8_MASK1 0x2a92 8253f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE8_MASK1_BASE_IDX 1 8254f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE8_CNTL1 0x2a93 8255f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE8_CNTL1_BASE_IDX 1 8256f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE9_BASE1 0x2a94 8257f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE9_BASE1_BASE_IDX 1 8258f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE9_MASK1 0x2a95 8259f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE9_MASK1_BASE_IDX 1 8260f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE9_CNTL1 0x2a96 8261f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE9_CNTL1_BASE_IDX 1 8262f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE10_BASE1 0x2a97 8263f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE10_BASE1_BASE_IDX 1 8264f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE10_MASK1 0x2a98 8265f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE10_MASK1_BASE_IDX 1 8266f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE10_CNTL1 0x2a99 8267f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE10_CNTL1_BASE_IDX 1 8268f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE11_BASE1 0x2a9a 8269f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE11_BASE1_BASE_IDX 1 8270f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE11_MASK1 0x2a9b 8271f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE11_MASK1_BASE_IDX 1 8272f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE11_CNTL1 0x2a9c 8273f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE11_CNTL1_BASE_IDX 1 8274f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE12_BASE1 0x2a9d 8275f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE12_BASE1_BASE_IDX 1 8276f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE12_MASK1 0x2a9e 8277f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE12_MASK1_BASE_IDX 1 8278f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE12_CNTL1 0x2a9f 8279f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE12_CNTL1_BASE_IDX 1 8280f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE13_BASE1 0x2aa0 8281f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE13_BASE1_BASE_IDX 1 8282f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE13_MASK1 0x2aa1 8283f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE13_MASK1_BASE_IDX 1 8284f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE13_CNTL1 0x2aa2 8285f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE13_CNTL1_BASE_IDX 1 8286f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE14_BASE1 0x2aa3 8287f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE14_BASE1_BASE_IDX 1 8288f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE14_MASK1 0x2aa4 8289f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE14_MASK1_BASE_IDX 1 8290f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE14_CNTL1 0x2aa5 8291f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE14_CNTL1_BASE_IDX 1 8292f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE15_BASE1 0x2aa6 8293f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE15_BASE1_BASE_IDX 1 8294f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE15_MASK1 0x2aa7 8295f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE15_MASK1_BASE_IDX 1 8296f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE15_CNTL1 0x2aa8 8297f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_APERTURE15_CNTL1_BASE_IDX 1 8298f33ac92fSHawking Zhang #define regCP_GFX_RS64_INTERRUPT1 0x2aac 8299f33ac92fSHawking Zhang #define regCP_GFX_RS64_INTERRUPT1_BASE_IDX 1 8300f33ac92fSHawking Zhang 8301f33ac92fSHawking Zhang 8302f33ac92fSHawking Zhang // addressBlock: gc_gl1dec 8303f33ac92fSHawking Zhang // base address: 0x33400 8304f33ac92fSHawking Zhang #define regGL1_DRAM_BURST_MASK 0x2d02 8305f33ac92fSHawking Zhang #define regGL1_DRAM_BURST_MASK_BASE_IDX 1 8306f33ac92fSHawking Zhang #define regGL1_ARB_STATUS 0x2d03 8307f33ac92fSHawking Zhang #define regGL1_ARB_STATUS_BASE_IDX 1 8308f33ac92fSHawking Zhang #define regGL1I_GL1R_REP_FGCG_OVERRIDE 0x2d05 8309f33ac92fSHawking Zhang #define regGL1I_GL1R_REP_FGCG_OVERRIDE_BASE_IDX 1 8310f33ac92fSHawking Zhang #define regGL1C_STATUS 0x2d41 8311f33ac92fSHawking Zhang #define regGL1C_STATUS_BASE_IDX 1 83127c8e4a25SChengming Gui #define regGL1C_UTCL0_CNTL1 0x2d42 83137c8e4a25SChengming Gui #define regGL1C_UTCL0_CNTL1_BASE_IDX 1 8314f33ac92fSHawking Zhang #define regGL1C_UTCL0_CNTL2 0x2d43 8315f33ac92fSHawking Zhang #define regGL1C_UTCL0_CNTL2_BASE_IDX 1 8316f33ac92fSHawking Zhang #define regGL1C_UTCL0_STATUS 0x2d44 8317f33ac92fSHawking Zhang #define regGL1C_UTCL0_STATUS_BASE_IDX 1 8318f33ac92fSHawking Zhang #define regGL1C_UTCL0_RETRY 0x2d45 8319f33ac92fSHawking Zhang #define regGL1C_UTCL0_RETRY_BASE_IDX 1 8320f33ac92fSHawking Zhang 8321f33ac92fSHawking Zhang 8322f33ac92fSHawking Zhang // addressBlock: gc_chdec 8323f33ac92fSHawking Zhang // base address: 0x33600 8324f33ac92fSHawking Zhang #define regCH_ARB_CTRL 0x2d80 8325f33ac92fSHawking Zhang #define regCH_ARB_CTRL_BASE_IDX 1 8326f33ac92fSHawking Zhang #define regCH_DRAM_BURST_MASK 0x2d82 8327f33ac92fSHawking Zhang #define regCH_DRAM_BURST_MASK_BASE_IDX 1 8328f33ac92fSHawking Zhang #define regCH_ARB_STATUS 0x2d83 8329f33ac92fSHawking Zhang #define regCH_ARB_STATUS_BASE_IDX 1 8330f33ac92fSHawking Zhang #define regCH_DRAM_BURST_CTRL 0x2d84 8331f33ac92fSHawking Zhang #define regCH_DRAM_BURST_CTRL_BASE_IDX 1 8332f33ac92fSHawking Zhang #define regCHA_CHC_CREDITS 0x2d88 8333f33ac92fSHawking Zhang #define regCHA_CHC_CREDITS_BASE_IDX 1 8334f33ac92fSHawking Zhang #define regCHA_CLIENT_FREE_DELAY 0x2d89 8335f33ac92fSHawking Zhang #define regCHA_CLIENT_FREE_DELAY_BASE_IDX 1 8336f33ac92fSHawking Zhang #define regCHI_CHR_REP_FGCG_OVERRIDE 0x2d8c 8337f33ac92fSHawking Zhang #define regCHI_CHR_REP_FGCG_OVERRIDE_BASE_IDX 1 8338f33ac92fSHawking Zhang #define regCH_VC5_ENABLE 0x2d94 8339f33ac92fSHawking Zhang #define regCH_VC5_ENABLE_BASE_IDX 1 8340f33ac92fSHawking Zhang #define regCHC_CTRL 0x2dc0 8341f33ac92fSHawking Zhang #define regCHC_CTRL_BASE_IDX 1 8342f33ac92fSHawking Zhang #define regCHC_STATUS 0x2dc1 8343f33ac92fSHawking Zhang #define regCHC_STATUS_BASE_IDX 1 8344f33ac92fSHawking Zhang #define regCHCG_CTRL 0x2dc2 8345f33ac92fSHawking Zhang #define regCHCG_CTRL_BASE_IDX 1 8346f33ac92fSHawking Zhang #define regCHCG_STATUS 0x2dc3 8347f33ac92fSHawking Zhang #define regCHCG_STATUS_BASE_IDX 1 8348f33ac92fSHawking Zhang 8349f33ac92fSHawking Zhang 8350f33ac92fSHawking Zhang // addressBlock: gc_gl2dec 8351f33ac92fSHawking Zhang // base address: 0x33800 8352f33ac92fSHawking Zhang #define regGL2C_CTRL 0x2e00 8353f33ac92fSHawking Zhang #define regGL2C_CTRL_BASE_IDX 1 8354f33ac92fSHawking Zhang #define regGL2C_CTRL2 0x2e01 8355f33ac92fSHawking Zhang #define regGL2C_CTRL2_BASE_IDX 1 8356f33ac92fSHawking Zhang #define regGL2C_ADDR_MATCH_MASK 0x2e03 8357f33ac92fSHawking Zhang #define regGL2C_ADDR_MATCH_MASK_BASE_IDX 1 8358f33ac92fSHawking Zhang #define regGL2C_ADDR_MATCH_SIZE 0x2e04 8359f33ac92fSHawking Zhang #define regGL2C_ADDR_MATCH_SIZE_BASE_IDX 1 8360f33ac92fSHawking Zhang #define regGL2C_WBINVL2 0x2e05 8361f33ac92fSHawking Zhang #define regGL2C_WBINVL2_BASE_IDX 1 8362f33ac92fSHawking Zhang #define regGL2C_SOFT_RESET 0x2e06 8363f33ac92fSHawking Zhang #define regGL2C_SOFT_RESET_BASE_IDX 1 8364f33ac92fSHawking Zhang #define regGL2C_CM_CTRL0 0x2e07 8365f33ac92fSHawking Zhang #define regGL2C_CM_CTRL0_BASE_IDX 1 8366f33ac92fSHawking Zhang #define regGL2C_CM_CTRL1 0x2e08 8367f33ac92fSHawking Zhang #define regGL2C_CM_CTRL1_BASE_IDX 1 8368f33ac92fSHawking Zhang #define regGL2C_CM_STALL 0x2e09 8369f33ac92fSHawking Zhang #define regGL2C_CM_STALL_BASE_IDX 1 8370f33ac92fSHawking Zhang #define regGL2C_CTRL3 0x2e0c 8371f33ac92fSHawking Zhang #define regGL2C_CTRL3_BASE_IDX 1 8372f33ac92fSHawking Zhang #define regGL2C_LB_CTR_CTRL 0x2e0d 8373f33ac92fSHawking Zhang #define regGL2C_LB_CTR_CTRL_BASE_IDX 1 8374f33ac92fSHawking Zhang #define regGL2C_LB_DATA0 0x2e0e 8375f33ac92fSHawking Zhang #define regGL2C_LB_DATA0_BASE_IDX 1 8376f33ac92fSHawking Zhang #define regGL2C_LB_DATA1 0x2e0f 8377f33ac92fSHawking Zhang #define regGL2C_LB_DATA1_BASE_IDX 1 8378f33ac92fSHawking Zhang #define regGL2C_LB_DATA2 0x2e10 8379f33ac92fSHawking Zhang #define regGL2C_LB_DATA2_BASE_IDX 1 8380f33ac92fSHawking Zhang #define regGL2C_LB_DATA3 0x2e11 8381f33ac92fSHawking Zhang #define regGL2C_LB_DATA3_BASE_IDX 1 8382f33ac92fSHawking Zhang #define regGL2C_LB_CTR_SEL0 0x2e12 8383f33ac92fSHawking Zhang #define regGL2C_LB_CTR_SEL0_BASE_IDX 1 8384f33ac92fSHawking Zhang #define regGL2C_LB_CTR_SEL1 0x2e13 8385f33ac92fSHawking Zhang #define regGL2C_LB_CTR_SEL1_BASE_IDX 1 8386f33ac92fSHawking Zhang #define regGL2C_CTRL4 0x2e17 8387f33ac92fSHawking Zhang #define regGL2C_CTRL4_BASE_IDX 1 8388f33ac92fSHawking Zhang #define regGL2C_DISCARD_STALL_CTRL 0x2e18 8389f33ac92fSHawking Zhang #define regGL2C_DISCARD_STALL_CTRL_BASE_IDX 1 8390f33ac92fSHawking Zhang #define regGL2A_ADDR_MATCH_CTRL 0x2e20 8391f33ac92fSHawking Zhang #define regGL2A_ADDR_MATCH_CTRL_BASE_IDX 1 8392f33ac92fSHawking Zhang #define regGL2A_ADDR_MATCH_MASK 0x2e21 8393f33ac92fSHawking Zhang #define regGL2A_ADDR_MATCH_MASK_BASE_IDX 1 8394f33ac92fSHawking Zhang #define regGL2A_ADDR_MATCH_SIZE 0x2e22 8395f33ac92fSHawking Zhang #define regGL2A_ADDR_MATCH_SIZE_BASE_IDX 1 8396f33ac92fSHawking Zhang #define regGL2A_PRIORITY_CTRL 0x2e23 8397f33ac92fSHawking Zhang #define regGL2A_PRIORITY_CTRL_BASE_IDX 1 8398f33ac92fSHawking Zhang #define regGL2A_RESP_THROTTLE_CTRL 0x2e2a 8399f33ac92fSHawking Zhang #define regGL2A_RESP_THROTTLE_CTRL_BASE_IDX 1 8400f33ac92fSHawking Zhang 8401f33ac92fSHawking Zhang 8402f33ac92fSHawking Zhang // addressBlock: gc_gl1hdec 8403f33ac92fSHawking Zhang // base address: 0x33900 8404f33ac92fSHawking Zhang #define regGL1H_ARB_CTRL 0x2e40 8405f33ac92fSHawking Zhang #define regGL1H_ARB_CTRL_BASE_IDX 1 8406f33ac92fSHawking Zhang #define regGL1H_GL1_CREDITS 0x2e41 8407f33ac92fSHawking Zhang #define regGL1H_GL1_CREDITS_BASE_IDX 1 8408f33ac92fSHawking Zhang #define regGL1H_BURST_MASK 0x2e42 8409f33ac92fSHawking Zhang #define regGL1H_BURST_MASK_BASE_IDX 1 8410f33ac92fSHawking Zhang #define regGL1H_BURST_CTRL 0x2e43 8411f33ac92fSHawking Zhang #define regGL1H_BURST_CTRL_BASE_IDX 1 8412f33ac92fSHawking Zhang #define regGL1H_ARB_STATUS 0x2e44 8413f33ac92fSHawking Zhang #define regGL1H_ARB_STATUS_BASE_IDX 1 8414f33ac92fSHawking Zhang 8415f33ac92fSHawking Zhang 8416f33ac92fSHawking Zhang // addressBlock: gc_perfddec 8417f33ac92fSHawking Zhang // base address: 0x34000 8418f33ac92fSHawking Zhang #define regCPG_PERFCOUNTER1_LO 0x3000 8419f33ac92fSHawking Zhang #define regCPG_PERFCOUNTER1_LO_BASE_IDX 1 8420f33ac92fSHawking Zhang #define regCPG_PERFCOUNTER1_HI 0x3001 8421f33ac92fSHawking Zhang #define regCPG_PERFCOUNTER1_HI_BASE_IDX 1 8422f33ac92fSHawking Zhang #define regCPG_PERFCOUNTER0_LO 0x3002 8423f33ac92fSHawking Zhang #define regCPG_PERFCOUNTER0_LO_BASE_IDX 1 8424f33ac92fSHawking Zhang #define regCPG_PERFCOUNTER0_HI 0x3003 8425f33ac92fSHawking Zhang #define regCPG_PERFCOUNTER0_HI_BASE_IDX 1 8426f33ac92fSHawking Zhang #define regCPC_PERFCOUNTER1_LO 0x3004 8427f33ac92fSHawking Zhang #define regCPC_PERFCOUNTER1_LO_BASE_IDX 1 8428f33ac92fSHawking Zhang #define regCPC_PERFCOUNTER1_HI 0x3005 8429f33ac92fSHawking Zhang #define regCPC_PERFCOUNTER1_HI_BASE_IDX 1 8430f33ac92fSHawking Zhang #define regCPC_PERFCOUNTER0_LO 0x3006 8431f33ac92fSHawking Zhang #define regCPC_PERFCOUNTER0_LO_BASE_IDX 1 8432f33ac92fSHawking Zhang #define regCPC_PERFCOUNTER0_HI 0x3007 8433f33ac92fSHawking Zhang #define regCPC_PERFCOUNTER0_HI_BASE_IDX 1 8434f33ac92fSHawking Zhang #define regCPF_PERFCOUNTER1_LO 0x3008 8435f33ac92fSHawking Zhang #define regCPF_PERFCOUNTER1_LO_BASE_IDX 1 8436f33ac92fSHawking Zhang #define regCPF_PERFCOUNTER1_HI 0x3009 8437f33ac92fSHawking Zhang #define regCPF_PERFCOUNTER1_HI_BASE_IDX 1 8438f33ac92fSHawking Zhang #define regCPF_PERFCOUNTER0_LO 0x300a 8439f33ac92fSHawking Zhang #define regCPF_PERFCOUNTER0_LO_BASE_IDX 1 8440f33ac92fSHawking Zhang #define regCPF_PERFCOUNTER0_HI 0x300b 8441f33ac92fSHawking Zhang #define regCPF_PERFCOUNTER0_HI_BASE_IDX 1 8442f33ac92fSHawking Zhang #define regCPF_LATENCY_STATS_DATA 0x300c 8443f33ac92fSHawking Zhang #define regCPF_LATENCY_STATS_DATA_BASE_IDX 1 8444f33ac92fSHawking Zhang #define regCPG_LATENCY_STATS_DATA 0x300d 8445f33ac92fSHawking Zhang #define regCPG_LATENCY_STATS_DATA_BASE_IDX 1 8446f33ac92fSHawking Zhang #define regCPC_LATENCY_STATS_DATA 0x300e 8447f33ac92fSHawking Zhang #define regCPC_LATENCY_STATS_DATA_BASE_IDX 1 8448f33ac92fSHawking Zhang #define regGRBM_PERFCOUNTER0_LO 0x3040 8449f33ac92fSHawking Zhang #define regGRBM_PERFCOUNTER0_LO_BASE_IDX 1 8450f33ac92fSHawking Zhang #define regGRBM_PERFCOUNTER0_HI 0x3041 8451f33ac92fSHawking Zhang #define regGRBM_PERFCOUNTER0_HI_BASE_IDX 1 8452f33ac92fSHawking Zhang #define regGRBM_PERFCOUNTER1_LO 0x3043 8453f33ac92fSHawking Zhang #define regGRBM_PERFCOUNTER1_LO_BASE_IDX 1 8454f33ac92fSHawking Zhang #define regGRBM_PERFCOUNTER1_HI 0x3044 8455f33ac92fSHawking Zhang #define regGRBM_PERFCOUNTER1_HI_BASE_IDX 1 8456f33ac92fSHawking Zhang #define regGRBM_SE0_PERFCOUNTER_LO 0x3045 8457f33ac92fSHawking Zhang #define regGRBM_SE0_PERFCOUNTER_LO_BASE_IDX 1 8458f33ac92fSHawking Zhang #define regGRBM_SE0_PERFCOUNTER_HI 0x3046 8459f33ac92fSHawking Zhang #define regGRBM_SE0_PERFCOUNTER_HI_BASE_IDX 1 8460f33ac92fSHawking Zhang #define regGRBM_SE1_PERFCOUNTER_LO 0x3047 8461f33ac92fSHawking Zhang #define regGRBM_SE1_PERFCOUNTER_LO_BASE_IDX 1 8462f33ac92fSHawking Zhang #define regGRBM_SE1_PERFCOUNTER_HI 0x3048 8463f33ac92fSHawking Zhang #define regGRBM_SE1_PERFCOUNTER_HI_BASE_IDX 1 8464f33ac92fSHawking Zhang #define regGRBM_SE2_PERFCOUNTER_LO 0x3049 8465f33ac92fSHawking Zhang #define regGRBM_SE2_PERFCOUNTER_LO_BASE_IDX 1 8466f33ac92fSHawking Zhang #define regGRBM_SE2_PERFCOUNTER_HI 0x304a 8467f33ac92fSHawking Zhang #define regGRBM_SE2_PERFCOUNTER_HI_BASE_IDX 1 8468f33ac92fSHawking Zhang #define regGRBM_SE3_PERFCOUNTER_LO 0x304b 8469f33ac92fSHawking Zhang #define regGRBM_SE3_PERFCOUNTER_LO_BASE_IDX 1 8470f33ac92fSHawking Zhang #define regGRBM_SE3_PERFCOUNTER_HI 0x304c 8471f33ac92fSHawking Zhang #define regGRBM_SE3_PERFCOUNTER_HI_BASE_IDX 1 8472f33ac92fSHawking Zhang #define regGRBM_SE4_PERFCOUNTER_LO 0x304d 8473f33ac92fSHawking Zhang #define regGRBM_SE4_PERFCOUNTER_LO_BASE_IDX 1 8474f33ac92fSHawking Zhang #define regGRBM_SE4_PERFCOUNTER_HI 0x304e 8475f33ac92fSHawking Zhang #define regGRBM_SE4_PERFCOUNTER_HI_BASE_IDX 1 8476f33ac92fSHawking Zhang #define regGRBM_SE5_PERFCOUNTER_LO 0x304f 8477f33ac92fSHawking Zhang #define regGRBM_SE5_PERFCOUNTER_LO_BASE_IDX 1 8478f33ac92fSHawking Zhang #define regGRBM_SE5_PERFCOUNTER_HI 0x3050 8479f33ac92fSHawking Zhang #define regGRBM_SE5_PERFCOUNTER_HI_BASE_IDX 1 8480f33ac92fSHawking Zhang #define regGRBM_SE6_PERFCOUNTER_LO 0x3051 8481f33ac92fSHawking Zhang #define regGRBM_SE6_PERFCOUNTER_LO_BASE_IDX 1 8482f33ac92fSHawking Zhang #define regGRBM_SE6_PERFCOUNTER_HI 0x3052 8483f33ac92fSHawking Zhang #define regGRBM_SE6_PERFCOUNTER_HI_BASE_IDX 1 8484f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER0_LO 0x30a4 8485f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER0_LO_BASE_IDX 1 8486f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER0_HI 0x30a5 8487f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER0_HI_BASE_IDX 1 8488f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER1_LO 0x30a6 8489f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER1_LO_BASE_IDX 1 8490f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER1_HI 0x30a7 8491f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER1_HI_BASE_IDX 1 8492f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER2_LO 0x30a8 8493f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER2_LO_BASE_IDX 1 8494f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER2_HI 0x30a9 8495f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER2_HI_BASE_IDX 1 8496f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER3_LO 0x30aa 8497f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER3_LO_BASE_IDX 1 8498f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER3_HI 0x30ab 8499f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER3_HI_BASE_IDX 1 8500f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER0_LO 0x30ac 8501f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER0_LO_BASE_IDX 1 8502f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER0_HI 0x30ad 8503f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER0_HI_BASE_IDX 1 8504f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER1_LO 0x30ae 8505f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER1_LO_BASE_IDX 1 8506f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER1_HI 0x30af 8507f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER1_HI_BASE_IDX 1 8508f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER2_LO 0x30b0 8509f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER2_LO_BASE_IDX 1 8510f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER2_HI 0x30b1 8511f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER2_HI_BASE_IDX 1 8512f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER3_LO 0x30b2 8513f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER3_LO_BASE_IDX 1 8514f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER3_HI 0x30b3 8515f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER3_HI_BASE_IDX 1 8516f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER0_LO 0x30b4 8517f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER0_LO_BASE_IDX 1 8518f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER0_HI 0x30b5 8519f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER0_HI_BASE_IDX 1 8520f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER1_LO 0x30b6 8521f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER1_LO_BASE_IDX 1 8522f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER1_HI 0x30b7 8523f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER1_HI_BASE_IDX 1 8524f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER2_LO 0x30b8 8525f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER2_LO_BASE_IDX 1 8526f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER2_HI 0x30b9 8527f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER2_HI_BASE_IDX 1 8528f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER3_LO 0x30ba 8529f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER3_LO_BASE_IDX 1 8530f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER3_HI 0x30bb 8531f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER3_HI_BASE_IDX 1 8532f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER0_LO 0x3100 8533f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER0_LO_BASE_IDX 1 8534f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER0_HI 0x3101 8535f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER0_HI_BASE_IDX 1 8536f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER1_LO 0x3102 8537f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER1_LO_BASE_IDX 1 8538f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER1_HI 0x3103 8539f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER1_HI_BASE_IDX 1 8540f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER2_LO 0x3104 8541f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER2_LO_BASE_IDX 1 8542f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER2_HI 0x3105 8543f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER2_HI_BASE_IDX 1 8544f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER3_LO 0x3106 8545f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER3_LO_BASE_IDX 1 8546f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER3_HI 0x3107 8547f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER3_HI_BASE_IDX 1 8548f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER0_LO 0x3140 8549f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER0_LO_BASE_IDX 1 8550f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER0_HI 0x3141 8551f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER0_HI_BASE_IDX 1 8552f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER1_LO 0x3142 8553f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER1_LO_BASE_IDX 1 8554f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER1_HI 0x3143 8555f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER1_HI_BASE_IDX 1 8556f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER2_LO 0x3144 8557f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER2_LO_BASE_IDX 1 8558f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER2_HI 0x3145 8559f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER2_HI_BASE_IDX 1 8560f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER3_LO 0x3146 8561f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER3_LO_BASE_IDX 1 8562f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER3_HI 0x3147 8563f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER3_HI_BASE_IDX 1 8564f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER4_LO 0x3148 8565f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER4_LO_BASE_IDX 1 8566f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER4_HI 0x3149 8567f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER4_HI_BASE_IDX 1 8568f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER5_LO 0x314a 8569f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER5_LO_BASE_IDX 1 8570f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER5_HI 0x314b 8571f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER5_HI_BASE_IDX 1 8572f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER6_LO 0x314c 8573f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER6_LO_BASE_IDX 1 8574f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER6_HI 0x314d 8575f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER6_HI_BASE_IDX 1 8576f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER7_LO 0x314e 8577f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER7_LO_BASE_IDX 1 8578f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER7_HI 0x314f 8579f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER7_HI_BASE_IDX 1 8580f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER0_HI 0x3180 8581f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER0_HI_BASE_IDX 1 8582f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER0_LO 0x3181 8583f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER0_LO_BASE_IDX 1 8584f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER1_HI 0x3182 8585f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER1_HI_BASE_IDX 1 8586f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER1_LO 0x3183 8587f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER1_LO_BASE_IDX 1 8588f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER2_HI 0x3184 8589f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER2_HI_BASE_IDX 1 8590f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER2_LO 0x3185 8591f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER2_LO_BASE_IDX 1 8592f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER3_HI 0x3186 8593f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER3_HI_BASE_IDX 1 8594f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER3_LO 0x3187 8595f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER3_LO_BASE_IDX 1 8596f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER4_HI 0x3188 8597f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER4_HI_BASE_IDX 1 8598f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER4_LO 0x3189 8599f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER4_LO_BASE_IDX 1 8600f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER5_HI 0x318a 8601f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER5_HI_BASE_IDX 1 8602f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER5_LO 0x318b 8603f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER5_LO_BASE_IDX 1 8604f33ac92fSHawking Zhang #define regPC_PERFCOUNTER0_HI 0x318c 8605f33ac92fSHawking Zhang #define regPC_PERFCOUNTER0_HI_BASE_IDX 1 8606f33ac92fSHawking Zhang #define regPC_PERFCOUNTER0_LO 0x318d 8607f33ac92fSHawking Zhang #define regPC_PERFCOUNTER0_LO_BASE_IDX 1 8608f33ac92fSHawking Zhang #define regPC_PERFCOUNTER1_HI 0x318e 8609f33ac92fSHawking Zhang #define regPC_PERFCOUNTER1_HI_BASE_IDX 1 8610f33ac92fSHawking Zhang #define regPC_PERFCOUNTER1_LO 0x318f 8611f33ac92fSHawking Zhang #define regPC_PERFCOUNTER1_LO_BASE_IDX 1 8612f33ac92fSHawking Zhang #define regPC_PERFCOUNTER2_HI 0x3190 8613f33ac92fSHawking Zhang #define regPC_PERFCOUNTER2_HI_BASE_IDX 1 8614f33ac92fSHawking Zhang #define regPC_PERFCOUNTER2_LO 0x3191 8615f33ac92fSHawking Zhang #define regPC_PERFCOUNTER2_LO_BASE_IDX 1 8616f33ac92fSHawking Zhang #define regPC_PERFCOUNTER3_HI 0x3192 8617f33ac92fSHawking Zhang #define regPC_PERFCOUNTER3_HI_BASE_IDX 1 8618f33ac92fSHawking Zhang #define regPC_PERFCOUNTER3_LO 0x3193 8619f33ac92fSHawking Zhang #define regPC_PERFCOUNTER3_LO_BASE_IDX 1 8620f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER0_LO 0x31c0 8621f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER0_LO_BASE_IDX 1 8622f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER1_LO 0x31c2 8623f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER1_LO_BASE_IDX 1 8624f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER2_LO 0x31c4 8625f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER2_LO_BASE_IDX 1 8626f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER3_LO 0x31c6 8627f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER3_LO_BASE_IDX 1 8628f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER4_LO 0x31c8 8629f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER4_LO_BASE_IDX 1 8630f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER5_LO 0x31ca 8631f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER5_LO_BASE_IDX 1 8632f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER6_LO 0x31cc 8633f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER6_LO_BASE_IDX 1 8634f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER7_LO 0x31ce 8635f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER7_LO_BASE_IDX 1 8636f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER0_LO 0x31e4 8637f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER0_LO_BASE_IDX 1 8638f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER0_HI 0x31e5 8639f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER0_HI_BASE_IDX 1 8640f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER1_LO 0x31e6 8641f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER1_LO_BASE_IDX 1 8642f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER1_HI 0x31e7 8643f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER1_HI_BASE_IDX 1 8644f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER2_LO 0x31e8 8645f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER2_LO_BASE_IDX 1 8646f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER2_HI 0x31e9 8647f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER2_HI_BASE_IDX 1 8648f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER3_LO 0x31ea 8649f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER3_LO_BASE_IDX 1 8650f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER3_HI 0x31eb 8651f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER3_HI_BASE_IDX 1 8652f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER4_LO 0x31ec 8653f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER4_LO_BASE_IDX 1 8654f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER4_HI 0x31ed 8655f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER4_HI_BASE_IDX 1 8656f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER5_LO 0x31ee 8657f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER5_LO_BASE_IDX 1 8658f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER5_HI 0x31ef 8659f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER5_HI_BASE_IDX 1 8660f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER6_LO 0x31f0 8661f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER6_LO_BASE_IDX 1 8662f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER6_HI 0x31f1 8663f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER6_HI_BASE_IDX 1 8664f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER7_LO 0x31f2 8665f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER7_LO_BASE_IDX 1 8666f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER7_HI 0x31f3 8667f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER7_HI_BASE_IDX 1 8668f33ac92fSHawking Zhang #define regSX_PERFCOUNTER0_LO 0x3240 8669f33ac92fSHawking Zhang #define regSX_PERFCOUNTER0_LO_BASE_IDX 1 8670f33ac92fSHawking Zhang #define regSX_PERFCOUNTER0_HI 0x3241 8671f33ac92fSHawking Zhang #define regSX_PERFCOUNTER0_HI_BASE_IDX 1 8672f33ac92fSHawking Zhang #define regSX_PERFCOUNTER1_LO 0x3242 8673f33ac92fSHawking Zhang #define regSX_PERFCOUNTER1_LO_BASE_IDX 1 8674f33ac92fSHawking Zhang #define regSX_PERFCOUNTER1_HI 0x3243 8675f33ac92fSHawking Zhang #define regSX_PERFCOUNTER1_HI_BASE_IDX 1 8676f33ac92fSHawking Zhang #define regSX_PERFCOUNTER2_LO 0x3244 8677f33ac92fSHawking Zhang #define regSX_PERFCOUNTER2_LO_BASE_IDX 1 8678f33ac92fSHawking Zhang #define regSX_PERFCOUNTER2_HI 0x3245 8679f33ac92fSHawking Zhang #define regSX_PERFCOUNTER2_HI_BASE_IDX 1 8680f33ac92fSHawking Zhang #define regSX_PERFCOUNTER3_LO 0x3246 8681f33ac92fSHawking Zhang #define regSX_PERFCOUNTER3_LO_BASE_IDX 1 8682f33ac92fSHawking Zhang #define regSX_PERFCOUNTER3_HI 0x3247 8683f33ac92fSHawking Zhang #define regSX_PERFCOUNTER3_HI_BASE_IDX 1 8684f33ac92fSHawking Zhang #define regGCEA_PERFCOUNTER2_LO 0x3260 8685f33ac92fSHawking Zhang #define regGCEA_PERFCOUNTER2_LO_BASE_IDX 1 8686f33ac92fSHawking Zhang #define regGCEA_PERFCOUNTER2_HI 0x3261 8687f33ac92fSHawking Zhang #define regGCEA_PERFCOUNTER2_HI_BASE_IDX 1 8688f33ac92fSHawking Zhang #define regGCEA_PERFCOUNTER_LO 0x3262 8689f33ac92fSHawking Zhang #define regGCEA_PERFCOUNTER_LO_BASE_IDX 1 8690f33ac92fSHawking Zhang #define regGCEA_PERFCOUNTER_HI 0x3263 8691f33ac92fSHawking Zhang #define regGCEA_PERFCOUNTER_HI_BASE_IDX 1 8692f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER0_LO 0x3280 8693f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER0_LO_BASE_IDX 1 8694f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER0_HI 0x3281 8695f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER0_HI_BASE_IDX 1 8696f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER1_LO 0x3282 8697f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER1_LO_BASE_IDX 1 8698f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER1_HI 0x3283 8699f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER1_HI_BASE_IDX 1 8700f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER2_LO 0x3284 8701f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER2_LO_BASE_IDX 1 8702f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER2_HI 0x3285 8703f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER2_HI_BASE_IDX 1 8704f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER3_LO 0x3286 8705f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER3_LO_BASE_IDX 1 8706f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER3_HI 0x3287 8707f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER3_HI_BASE_IDX 1 8708f33ac92fSHawking Zhang #define regTA_PERFCOUNTER0_LO 0x32c0 8709f33ac92fSHawking Zhang #define regTA_PERFCOUNTER0_LO_BASE_IDX 1 8710f33ac92fSHawking Zhang #define regTA_PERFCOUNTER0_HI 0x32c1 8711f33ac92fSHawking Zhang #define regTA_PERFCOUNTER0_HI_BASE_IDX 1 8712f33ac92fSHawking Zhang #define regTA_PERFCOUNTER1_LO 0x32c2 8713f33ac92fSHawking Zhang #define regTA_PERFCOUNTER1_LO_BASE_IDX 1 8714f33ac92fSHawking Zhang #define regTA_PERFCOUNTER1_HI 0x32c3 8715f33ac92fSHawking Zhang #define regTA_PERFCOUNTER1_HI_BASE_IDX 1 8716f33ac92fSHawking Zhang #define regTD_PERFCOUNTER0_LO 0x3300 8717f33ac92fSHawking Zhang #define regTD_PERFCOUNTER0_LO_BASE_IDX 1 8718f33ac92fSHawking Zhang #define regTD_PERFCOUNTER0_HI 0x3301 8719f33ac92fSHawking Zhang #define regTD_PERFCOUNTER0_HI_BASE_IDX 1 8720f33ac92fSHawking Zhang #define regTD_PERFCOUNTER1_LO 0x3302 8721f33ac92fSHawking Zhang #define regTD_PERFCOUNTER1_LO_BASE_IDX 1 8722f33ac92fSHawking Zhang #define regTD_PERFCOUNTER1_HI 0x3303 8723f33ac92fSHawking Zhang #define regTD_PERFCOUNTER1_HI_BASE_IDX 1 8724f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER0_LO 0x3340 8725f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER0_LO_BASE_IDX 1 8726f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER0_HI 0x3341 8727f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER0_HI_BASE_IDX 1 8728f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER1_LO 0x3342 8729f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER1_LO_BASE_IDX 1 8730f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER1_HI 0x3343 8731f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER1_HI_BASE_IDX 1 8732f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER2_LO 0x3344 8733f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER2_LO_BASE_IDX 1 8734f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER2_HI 0x3345 8735f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER2_HI_BASE_IDX 1 8736f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER3_LO 0x3346 8737f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER3_LO_BASE_IDX 1 8738f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER3_HI 0x3347 8739f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER3_HI_BASE_IDX 1 8740f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER_FILTER 0x3348 8741f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER_FILTER_BASE_IDX 1 8742f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER_FILTER2 0x3349 8743f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER_FILTER2_BASE_IDX 1 8744f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER_FILTER_EN 0x334a 8745f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER_FILTER_EN_BASE_IDX 1 8746f33ac92fSHawking Zhang #define regGL2C_PERFCOUNTER0_LO 0x3380 8747f33ac92fSHawking Zhang #define regGL2C_PERFCOUNTER0_LO_BASE_IDX 1 8748f33ac92fSHawking Zhang #define regGL2C_PERFCOUNTER0_HI 0x3381 8749f33ac92fSHawking Zhang #define regGL2C_PERFCOUNTER0_HI_BASE_IDX 1 8750f33ac92fSHawking Zhang #define regGL2C_PERFCOUNTER1_LO 0x3382 8751f33ac92fSHawking Zhang #define regGL2C_PERFCOUNTER1_LO_BASE_IDX 1 8752f33ac92fSHawking Zhang #define regGL2C_PERFCOUNTER1_HI 0x3383 8753f33ac92fSHawking Zhang #define regGL2C_PERFCOUNTER1_HI_BASE_IDX 1 8754f33ac92fSHawking Zhang #define regGL2C_PERFCOUNTER2_LO 0x3384 8755f33ac92fSHawking Zhang #define regGL2C_PERFCOUNTER2_LO_BASE_IDX 1 8756f33ac92fSHawking Zhang #define regGL2C_PERFCOUNTER2_HI 0x3385 8757f33ac92fSHawking Zhang #define regGL2C_PERFCOUNTER2_HI_BASE_IDX 1 8758f33ac92fSHawking Zhang #define regGL2C_PERFCOUNTER3_LO 0x3386 8759f33ac92fSHawking Zhang #define regGL2C_PERFCOUNTER3_LO_BASE_IDX 1 8760f33ac92fSHawking Zhang #define regGL2C_PERFCOUNTER3_HI 0x3387 8761f33ac92fSHawking Zhang #define regGL2C_PERFCOUNTER3_HI_BASE_IDX 1 8762f33ac92fSHawking Zhang #define regGL2A_PERFCOUNTER0_LO 0x3390 8763f33ac92fSHawking Zhang #define regGL2A_PERFCOUNTER0_LO_BASE_IDX 1 8764f33ac92fSHawking Zhang #define regGL2A_PERFCOUNTER0_HI 0x3391 8765f33ac92fSHawking Zhang #define regGL2A_PERFCOUNTER0_HI_BASE_IDX 1 8766f33ac92fSHawking Zhang #define regGL2A_PERFCOUNTER1_LO 0x3392 8767f33ac92fSHawking Zhang #define regGL2A_PERFCOUNTER1_LO_BASE_IDX 1 8768f33ac92fSHawking Zhang #define regGL2A_PERFCOUNTER1_HI 0x3393 8769f33ac92fSHawking Zhang #define regGL2A_PERFCOUNTER1_HI_BASE_IDX 1 8770f33ac92fSHawking Zhang #define regGL2A_PERFCOUNTER2_LO 0x3394 8771f33ac92fSHawking Zhang #define regGL2A_PERFCOUNTER2_LO_BASE_IDX 1 8772f33ac92fSHawking Zhang #define regGL2A_PERFCOUNTER2_HI 0x3395 8773f33ac92fSHawking Zhang #define regGL2A_PERFCOUNTER2_HI_BASE_IDX 1 8774f33ac92fSHawking Zhang #define regGL2A_PERFCOUNTER3_LO 0x3396 8775f33ac92fSHawking Zhang #define regGL2A_PERFCOUNTER3_LO_BASE_IDX 1 8776f33ac92fSHawking Zhang #define regGL2A_PERFCOUNTER3_HI 0x3397 8777f33ac92fSHawking Zhang #define regGL2A_PERFCOUNTER3_HI_BASE_IDX 1 8778f33ac92fSHawking Zhang #define regGL1C_PERFCOUNTER0_LO 0x33a0 8779f33ac92fSHawking Zhang #define regGL1C_PERFCOUNTER0_LO_BASE_IDX 1 8780f33ac92fSHawking Zhang #define regGL1C_PERFCOUNTER0_HI 0x33a1 8781f33ac92fSHawking Zhang #define regGL1C_PERFCOUNTER0_HI_BASE_IDX 1 8782f33ac92fSHawking Zhang #define regGL1C_PERFCOUNTER1_LO 0x33a2 8783f33ac92fSHawking Zhang #define regGL1C_PERFCOUNTER1_LO_BASE_IDX 1 8784f33ac92fSHawking Zhang #define regGL1C_PERFCOUNTER1_HI 0x33a3 8785f33ac92fSHawking Zhang #define regGL1C_PERFCOUNTER1_HI_BASE_IDX 1 8786f33ac92fSHawking Zhang #define regGL1C_PERFCOUNTER2_LO 0x33a4 8787f33ac92fSHawking Zhang #define regGL1C_PERFCOUNTER2_LO_BASE_IDX 1 8788f33ac92fSHawking Zhang #define regGL1C_PERFCOUNTER2_HI 0x33a5 8789f33ac92fSHawking Zhang #define regGL1C_PERFCOUNTER2_HI_BASE_IDX 1 8790f33ac92fSHawking Zhang #define regGL1C_PERFCOUNTER3_LO 0x33a6 8791f33ac92fSHawking Zhang #define regGL1C_PERFCOUNTER3_LO_BASE_IDX 1 8792f33ac92fSHawking Zhang #define regGL1C_PERFCOUNTER3_HI 0x33a7 8793f33ac92fSHawking Zhang #define regGL1C_PERFCOUNTER3_HI_BASE_IDX 1 8794f33ac92fSHawking Zhang #define regCHC_PERFCOUNTER0_LO 0x33c0 8795f33ac92fSHawking Zhang #define regCHC_PERFCOUNTER0_LO_BASE_IDX 1 8796f33ac92fSHawking Zhang #define regCHC_PERFCOUNTER0_HI 0x33c1 8797f33ac92fSHawking Zhang #define regCHC_PERFCOUNTER0_HI_BASE_IDX 1 8798f33ac92fSHawking Zhang #define regCHC_PERFCOUNTER1_LO 0x33c2 8799f33ac92fSHawking Zhang #define regCHC_PERFCOUNTER1_LO_BASE_IDX 1 8800f33ac92fSHawking Zhang #define regCHC_PERFCOUNTER1_HI 0x33c3 8801f33ac92fSHawking Zhang #define regCHC_PERFCOUNTER1_HI_BASE_IDX 1 8802f33ac92fSHawking Zhang #define regCHC_PERFCOUNTER2_LO 0x33c4 8803f33ac92fSHawking Zhang #define regCHC_PERFCOUNTER2_LO_BASE_IDX 1 8804f33ac92fSHawking Zhang #define regCHC_PERFCOUNTER2_HI 0x33c5 8805f33ac92fSHawking Zhang #define regCHC_PERFCOUNTER2_HI_BASE_IDX 1 8806f33ac92fSHawking Zhang #define regCHC_PERFCOUNTER3_LO 0x33c6 8807f33ac92fSHawking Zhang #define regCHC_PERFCOUNTER3_LO_BASE_IDX 1 8808f33ac92fSHawking Zhang #define regCHC_PERFCOUNTER3_HI 0x33c7 8809f33ac92fSHawking Zhang #define regCHC_PERFCOUNTER3_HI_BASE_IDX 1 8810f33ac92fSHawking Zhang #define regCHCG_PERFCOUNTER0_LO 0x33c8 8811f33ac92fSHawking Zhang #define regCHCG_PERFCOUNTER0_LO_BASE_IDX 1 8812f33ac92fSHawking Zhang #define regCHCG_PERFCOUNTER0_HI 0x33c9 8813f33ac92fSHawking Zhang #define regCHCG_PERFCOUNTER0_HI_BASE_IDX 1 8814f33ac92fSHawking Zhang #define regCHCG_PERFCOUNTER1_LO 0x33ca 8815f33ac92fSHawking Zhang #define regCHCG_PERFCOUNTER1_LO_BASE_IDX 1 8816f33ac92fSHawking Zhang #define regCHCG_PERFCOUNTER1_HI 0x33cb 8817f33ac92fSHawking Zhang #define regCHCG_PERFCOUNTER1_HI_BASE_IDX 1 8818f33ac92fSHawking Zhang #define regCHCG_PERFCOUNTER2_LO 0x33cc 8819f33ac92fSHawking Zhang #define regCHCG_PERFCOUNTER2_LO_BASE_IDX 1 8820f33ac92fSHawking Zhang #define regCHCG_PERFCOUNTER2_HI 0x33cd 8821f33ac92fSHawking Zhang #define regCHCG_PERFCOUNTER2_HI_BASE_IDX 1 8822f33ac92fSHawking Zhang #define regCHCG_PERFCOUNTER3_LO 0x33ce 8823f33ac92fSHawking Zhang #define regCHCG_PERFCOUNTER3_LO_BASE_IDX 1 8824f33ac92fSHawking Zhang #define regCHCG_PERFCOUNTER3_HI 0x33cf 8825f33ac92fSHawking Zhang #define regCHCG_PERFCOUNTER3_HI_BASE_IDX 1 8826f33ac92fSHawking Zhang #define regCB_PERFCOUNTER0_LO 0x3406 8827f33ac92fSHawking Zhang #define regCB_PERFCOUNTER0_LO_BASE_IDX 1 8828f33ac92fSHawking Zhang #define regCB_PERFCOUNTER0_HI 0x3407 8829f33ac92fSHawking Zhang #define regCB_PERFCOUNTER0_HI_BASE_IDX 1 8830f33ac92fSHawking Zhang #define regCB_PERFCOUNTER1_LO 0x3408 8831f33ac92fSHawking Zhang #define regCB_PERFCOUNTER1_LO_BASE_IDX 1 8832f33ac92fSHawking Zhang #define regCB_PERFCOUNTER1_HI 0x3409 8833f33ac92fSHawking Zhang #define regCB_PERFCOUNTER1_HI_BASE_IDX 1 8834f33ac92fSHawking Zhang #define regCB_PERFCOUNTER2_LO 0x340a 8835f33ac92fSHawking Zhang #define regCB_PERFCOUNTER2_LO_BASE_IDX 1 8836f33ac92fSHawking Zhang #define regCB_PERFCOUNTER2_HI 0x340b 8837f33ac92fSHawking Zhang #define regCB_PERFCOUNTER2_HI_BASE_IDX 1 8838f33ac92fSHawking Zhang #define regCB_PERFCOUNTER3_LO 0x340c 8839f33ac92fSHawking Zhang #define regCB_PERFCOUNTER3_LO_BASE_IDX 1 8840f33ac92fSHawking Zhang #define regCB_PERFCOUNTER3_HI 0x340d 8841f33ac92fSHawking Zhang #define regCB_PERFCOUNTER3_HI_BASE_IDX 1 8842f33ac92fSHawking Zhang #define regDB_PERFCOUNTER0_LO 0x3440 8843f33ac92fSHawking Zhang #define regDB_PERFCOUNTER0_LO_BASE_IDX 1 8844f33ac92fSHawking Zhang #define regDB_PERFCOUNTER0_HI 0x3441 8845f33ac92fSHawking Zhang #define regDB_PERFCOUNTER0_HI_BASE_IDX 1 8846f33ac92fSHawking Zhang #define regDB_PERFCOUNTER1_LO 0x3442 8847f33ac92fSHawking Zhang #define regDB_PERFCOUNTER1_LO_BASE_IDX 1 8848f33ac92fSHawking Zhang #define regDB_PERFCOUNTER1_HI 0x3443 8849f33ac92fSHawking Zhang #define regDB_PERFCOUNTER1_HI_BASE_IDX 1 8850f33ac92fSHawking Zhang #define regDB_PERFCOUNTER2_LO 0x3444 8851f33ac92fSHawking Zhang #define regDB_PERFCOUNTER2_LO_BASE_IDX 1 8852f33ac92fSHawking Zhang #define regDB_PERFCOUNTER2_HI 0x3445 8853f33ac92fSHawking Zhang #define regDB_PERFCOUNTER2_HI_BASE_IDX 1 8854f33ac92fSHawking Zhang #define regDB_PERFCOUNTER3_LO 0x3446 8855f33ac92fSHawking Zhang #define regDB_PERFCOUNTER3_LO_BASE_IDX 1 8856f33ac92fSHawking Zhang #define regDB_PERFCOUNTER3_HI 0x3447 8857f33ac92fSHawking Zhang #define regDB_PERFCOUNTER3_HI_BASE_IDX 1 8858f33ac92fSHawking Zhang #define regRLC_PERFCOUNTER0_LO 0x3480 8859f33ac92fSHawking Zhang #define regRLC_PERFCOUNTER0_LO_BASE_IDX 1 8860f33ac92fSHawking Zhang #define regRLC_PERFCOUNTER0_HI 0x3481 8861f33ac92fSHawking Zhang #define regRLC_PERFCOUNTER0_HI_BASE_IDX 1 8862f33ac92fSHawking Zhang #define regRLC_PERFCOUNTER1_LO 0x3482 8863f33ac92fSHawking Zhang #define regRLC_PERFCOUNTER1_LO_BASE_IDX 1 8864f33ac92fSHawking Zhang #define regRLC_PERFCOUNTER1_HI 0x3483 8865f33ac92fSHawking Zhang #define regRLC_PERFCOUNTER1_HI_BASE_IDX 1 8866f33ac92fSHawking Zhang #define regRMI_PERFCOUNTER0_LO 0x34c0 8867f33ac92fSHawking Zhang #define regRMI_PERFCOUNTER0_LO_BASE_IDX 1 8868f33ac92fSHawking Zhang #define regRMI_PERFCOUNTER0_HI 0x34c1 8869f33ac92fSHawking Zhang #define regRMI_PERFCOUNTER0_HI_BASE_IDX 1 8870f33ac92fSHawking Zhang #define regRMI_PERFCOUNTER1_LO 0x34c2 8871f33ac92fSHawking Zhang #define regRMI_PERFCOUNTER1_LO_BASE_IDX 1 8872f33ac92fSHawking Zhang #define regRMI_PERFCOUNTER1_HI 0x34c3 8873f33ac92fSHawking Zhang #define regRMI_PERFCOUNTER1_HI_BASE_IDX 1 8874f33ac92fSHawking Zhang #define regRMI_PERFCOUNTER2_LO 0x34c4 8875f33ac92fSHawking Zhang #define regRMI_PERFCOUNTER2_LO_BASE_IDX 1 8876f33ac92fSHawking Zhang #define regRMI_PERFCOUNTER2_HI 0x34c5 8877f33ac92fSHawking Zhang #define regRMI_PERFCOUNTER2_HI_BASE_IDX 1 8878f33ac92fSHawking Zhang #define regRMI_PERFCOUNTER3_LO 0x34c6 8879f33ac92fSHawking Zhang #define regRMI_PERFCOUNTER3_LO_BASE_IDX 1 8880f33ac92fSHawking Zhang #define regRMI_PERFCOUNTER3_HI 0x34c7 8881f33ac92fSHawking Zhang #define regRMI_PERFCOUNTER3_HI_BASE_IDX 1 8882f33ac92fSHawking Zhang #define regGCR_PERFCOUNTER0_LO 0x3520 8883f33ac92fSHawking Zhang #define regGCR_PERFCOUNTER0_LO_BASE_IDX 1 8884f33ac92fSHawking Zhang #define regGCR_PERFCOUNTER0_HI 0x3521 8885f33ac92fSHawking Zhang #define regGCR_PERFCOUNTER0_HI_BASE_IDX 1 8886f33ac92fSHawking Zhang #define regGCR_PERFCOUNTER1_LO 0x3522 8887f33ac92fSHawking Zhang #define regGCR_PERFCOUNTER1_LO_BASE_IDX 1 8888f33ac92fSHawking Zhang #define regGCR_PERFCOUNTER1_HI 0x3523 8889f33ac92fSHawking Zhang #define regGCR_PERFCOUNTER1_HI_BASE_IDX 1 8890f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER0_LO 0x3580 8891f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER0_LO_BASE_IDX 1 8892f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER0_HI 0x3581 8893f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER0_HI_BASE_IDX 1 8894f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER1_LO 0x3582 8895f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER1_LO_BASE_IDX 1 8896f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER1_HI 0x3583 8897f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER1_HI_BASE_IDX 1 8898f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER2_LO 0x3584 8899f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER2_LO_BASE_IDX 1 8900f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER2_HI 0x3585 8901f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER2_HI_BASE_IDX 1 8902f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER3_LO 0x3586 8903f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER3_LO_BASE_IDX 1 8904f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER3_HI 0x3587 8905f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER3_HI_BASE_IDX 1 8906f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER4_LO 0x3588 8907f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER4_LO_BASE_IDX 1 8908f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER4_HI 0x3589 8909f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER4_HI_BASE_IDX 1 8910f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER5_LO 0x358a 8911f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER5_LO_BASE_IDX 1 8912f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER5_HI 0x358b 8913f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER5_HI_BASE_IDX 1 8914f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER6_LO 0x358c 8915f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER6_LO_BASE_IDX 1 8916f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER6_HI 0x358d 8917f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER6_HI_BASE_IDX 1 8918f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER7_LO 0x358e 8919f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER7_LO_BASE_IDX 1 8920f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER7_HI 0x358f 8921f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER7_HI_BASE_IDX 1 8922f33ac92fSHawking Zhang #define regUTCL1_PERFCOUNTER0_LO 0x35a0 8923f33ac92fSHawking Zhang #define regUTCL1_PERFCOUNTER0_LO_BASE_IDX 1 8924f33ac92fSHawking Zhang #define regUTCL1_PERFCOUNTER0_HI 0x35a1 8925f33ac92fSHawking Zhang #define regUTCL1_PERFCOUNTER0_HI_BASE_IDX 1 8926f33ac92fSHawking Zhang #define regUTCL1_PERFCOUNTER1_LO 0x35a2 8927f33ac92fSHawking Zhang #define regUTCL1_PERFCOUNTER1_LO_BASE_IDX 1 8928f33ac92fSHawking Zhang #define regUTCL1_PERFCOUNTER1_HI 0x35a3 8929f33ac92fSHawking Zhang #define regUTCL1_PERFCOUNTER1_HI_BASE_IDX 1 8930f33ac92fSHawking Zhang #define regUTCL1_PERFCOUNTER2_LO 0x35a4 8931f33ac92fSHawking Zhang #define regUTCL1_PERFCOUNTER2_LO_BASE_IDX 1 8932f33ac92fSHawking Zhang #define regUTCL1_PERFCOUNTER2_HI 0x35a5 8933f33ac92fSHawking Zhang #define regUTCL1_PERFCOUNTER2_HI_BASE_IDX 1 8934f33ac92fSHawking Zhang #define regUTCL1_PERFCOUNTER3_LO 0x35a6 8935f33ac92fSHawking Zhang #define regUTCL1_PERFCOUNTER3_LO_BASE_IDX 1 8936f33ac92fSHawking Zhang #define regUTCL1_PERFCOUNTER3_HI 0x35a7 8937f33ac92fSHawking Zhang #define regUTCL1_PERFCOUNTER3_HI_BASE_IDX 1 8938f33ac92fSHawking Zhang #define regGL1A_PERFCOUNTER0_LO 0x35c0 8939f33ac92fSHawking Zhang #define regGL1A_PERFCOUNTER0_LO_BASE_IDX 1 8940f33ac92fSHawking Zhang #define regGL1A_PERFCOUNTER0_HI 0x35c1 8941f33ac92fSHawking Zhang #define regGL1A_PERFCOUNTER0_HI_BASE_IDX 1 8942f33ac92fSHawking Zhang #define regGL1A_PERFCOUNTER1_LO 0x35c2 8943f33ac92fSHawking Zhang #define regGL1A_PERFCOUNTER1_LO_BASE_IDX 1 8944f33ac92fSHawking Zhang #define regGL1A_PERFCOUNTER1_HI 0x35c3 8945f33ac92fSHawking Zhang #define regGL1A_PERFCOUNTER1_HI_BASE_IDX 1 8946f33ac92fSHawking Zhang #define regGL1A_PERFCOUNTER2_LO 0x35c4 8947f33ac92fSHawking Zhang #define regGL1A_PERFCOUNTER2_LO_BASE_IDX 1 8948f33ac92fSHawking Zhang #define regGL1A_PERFCOUNTER2_HI 0x35c5 8949f33ac92fSHawking Zhang #define regGL1A_PERFCOUNTER2_HI_BASE_IDX 1 8950f33ac92fSHawking Zhang #define regGL1A_PERFCOUNTER3_LO 0x35c6 8951f33ac92fSHawking Zhang #define regGL1A_PERFCOUNTER3_LO_BASE_IDX 1 8952f33ac92fSHawking Zhang #define regGL1A_PERFCOUNTER3_HI 0x35c7 8953f33ac92fSHawking Zhang #define regGL1A_PERFCOUNTER3_HI_BASE_IDX 1 8954f33ac92fSHawking Zhang #define regGL1H_PERFCOUNTER0_LO 0x35d0 8955f33ac92fSHawking Zhang #define regGL1H_PERFCOUNTER0_LO_BASE_IDX 1 8956f33ac92fSHawking Zhang #define regGL1H_PERFCOUNTER0_HI 0x35d1 8957f33ac92fSHawking Zhang #define regGL1H_PERFCOUNTER0_HI_BASE_IDX 1 8958f33ac92fSHawking Zhang #define regGL1H_PERFCOUNTER1_LO 0x35d2 8959f33ac92fSHawking Zhang #define regGL1H_PERFCOUNTER1_LO_BASE_IDX 1 8960f33ac92fSHawking Zhang #define regGL1H_PERFCOUNTER1_HI 0x35d3 8961f33ac92fSHawking Zhang #define regGL1H_PERFCOUNTER1_HI_BASE_IDX 1 8962f33ac92fSHawking Zhang #define regGL1H_PERFCOUNTER2_LO 0x35d4 8963f33ac92fSHawking Zhang #define regGL1H_PERFCOUNTER2_LO_BASE_IDX 1 8964f33ac92fSHawking Zhang #define regGL1H_PERFCOUNTER2_HI 0x35d5 8965f33ac92fSHawking Zhang #define regGL1H_PERFCOUNTER2_HI_BASE_IDX 1 8966f33ac92fSHawking Zhang #define regGL1H_PERFCOUNTER3_LO 0x35d6 8967f33ac92fSHawking Zhang #define regGL1H_PERFCOUNTER3_LO_BASE_IDX 1 8968f33ac92fSHawking Zhang #define regGL1H_PERFCOUNTER3_HI 0x35d7 8969f33ac92fSHawking Zhang #define regGL1H_PERFCOUNTER3_HI_BASE_IDX 1 8970f33ac92fSHawking Zhang #define regCHA_PERFCOUNTER0_LO 0x3600 8971f33ac92fSHawking Zhang #define regCHA_PERFCOUNTER0_LO_BASE_IDX 1 8972f33ac92fSHawking Zhang #define regCHA_PERFCOUNTER0_HI 0x3601 8973f33ac92fSHawking Zhang #define regCHA_PERFCOUNTER0_HI_BASE_IDX 1 8974f33ac92fSHawking Zhang #define regCHA_PERFCOUNTER1_LO 0x3602 8975f33ac92fSHawking Zhang #define regCHA_PERFCOUNTER1_LO_BASE_IDX 1 8976f33ac92fSHawking Zhang #define regCHA_PERFCOUNTER1_HI 0x3603 8977f33ac92fSHawking Zhang #define regCHA_PERFCOUNTER1_HI_BASE_IDX 1 8978f33ac92fSHawking Zhang #define regCHA_PERFCOUNTER2_LO 0x3604 8979f33ac92fSHawking Zhang #define regCHA_PERFCOUNTER2_LO_BASE_IDX 1 8980f33ac92fSHawking Zhang #define regCHA_PERFCOUNTER2_HI 0x3605 8981f33ac92fSHawking Zhang #define regCHA_PERFCOUNTER2_HI_BASE_IDX 1 8982f33ac92fSHawking Zhang #define regCHA_PERFCOUNTER3_LO 0x3606 8983f33ac92fSHawking Zhang #define regCHA_PERFCOUNTER3_LO_BASE_IDX 1 8984f33ac92fSHawking Zhang #define regCHA_PERFCOUNTER3_HI 0x3607 8985f33ac92fSHawking Zhang #define regCHA_PERFCOUNTER3_HI_BASE_IDX 1 8986f33ac92fSHawking Zhang #define regGUS_PERFCOUNTER2_LO 0x3640 8987f33ac92fSHawking Zhang #define regGUS_PERFCOUNTER2_LO_BASE_IDX 1 8988f33ac92fSHawking Zhang #define regGUS_PERFCOUNTER2_HI 0x3641 8989f33ac92fSHawking Zhang #define regGUS_PERFCOUNTER2_HI_BASE_IDX 1 8990f33ac92fSHawking Zhang #define regGUS_PERFCOUNTER_LO 0x3642 8991f33ac92fSHawking Zhang #define regGUS_PERFCOUNTER_LO_BASE_IDX 1 8992f33ac92fSHawking Zhang #define regGUS_PERFCOUNTER_HI 0x3643 8993f33ac92fSHawking Zhang #define regGUS_PERFCOUNTER_HI_BASE_IDX 1 8994f33ac92fSHawking Zhang 8995f33ac92fSHawking Zhang 8996f33ac92fSHawking Zhang // addressBlock: gc_perfsdec 8997f33ac92fSHawking Zhang // base address: 0x36000 8998f33ac92fSHawking Zhang #define regCPG_PERFCOUNTER1_SELECT 0x3800 8999f33ac92fSHawking Zhang #define regCPG_PERFCOUNTER1_SELECT_BASE_IDX 1 9000f33ac92fSHawking Zhang #define regCPG_PERFCOUNTER0_SELECT1 0x3801 9001f33ac92fSHawking Zhang #define regCPG_PERFCOUNTER0_SELECT1_BASE_IDX 1 9002f33ac92fSHawking Zhang #define regCPG_PERFCOUNTER0_SELECT 0x3802 9003f33ac92fSHawking Zhang #define regCPG_PERFCOUNTER0_SELECT_BASE_IDX 1 9004f33ac92fSHawking Zhang #define regCPC_PERFCOUNTER1_SELECT 0x3803 9005f33ac92fSHawking Zhang #define regCPC_PERFCOUNTER1_SELECT_BASE_IDX 1 9006f33ac92fSHawking Zhang #define regCPC_PERFCOUNTER0_SELECT1 0x3804 9007f33ac92fSHawking Zhang #define regCPC_PERFCOUNTER0_SELECT1_BASE_IDX 1 9008f33ac92fSHawking Zhang #define regCPF_PERFCOUNTER1_SELECT 0x3805 9009f33ac92fSHawking Zhang #define regCPF_PERFCOUNTER1_SELECT_BASE_IDX 1 9010f33ac92fSHawking Zhang #define regCPF_PERFCOUNTER0_SELECT1 0x3806 9011f33ac92fSHawking Zhang #define regCPF_PERFCOUNTER0_SELECT1_BASE_IDX 1 9012f33ac92fSHawking Zhang #define regCPF_PERFCOUNTER0_SELECT 0x3807 9013f33ac92fSHawking Zhang #define regCPF_PERFCOUNTER0_SELECT_BASE_IDX 1 9014f33ac92fSHawking Zhang #define regCP_PERFMON_CNTL 0x3808 9015f33ac92fSHawking Zhang #define regCP_PERFMON_CNTL_BASE_IDX 1 9016f33ac92fSHawking Zhang #define regCPC_PERFCOUNTER0_SELECT 0x3809 9017f33ac92fSHawking Zhang #define regCPC_PERFCOUNTER0_SELECT_BASE_IDX 1 9018f33ac92fSHawking Zhang #define regCPF_TC_PERF_COUNTER_WINDOW_SELECT 0x380a 9019f33ac92fSHawking Zhang #define regCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 9020f33ac92fSHawking Zhang #define regCPG_TC_PERF_COUNTER_WINDOW_SELECT 0x380b 9021f33ac92fSHawking Zhang #define regCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 9022f33ac92fSHawking Zhang #define regCPF_LATENCY_STATS_SELECT 0x380c 9023f33ac92fSHawking Zhang #define regCPF_LATENCY_STATS_SELECT_BASE_IDX 1 9024f33ac92fSHawking Zhang #define regCPG_LATENCY_STATS_SELECT 0x380d 9025f33ac92fSHawking Zhang #define regCPG_LATENCY_STATS_SELECT_BASE_IDX 1 9026f33ac92fSHawking Zhang #define regCPC_LATENCY_STATS_SELECT 0x380e 9027f33ac92fSHawking Zhang #define regCPC_LATENCY_STATS_SELECT_BASE_IDX 1 9028f33ac92fSHawking Zhang #define regCPC_TC_PERF_COUNTER_WINDOW_SELECT 0x380f 9029f33ac92fSHawking Zhang #define regCPC_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 9030f33ac92fSHawking Zhang #define regCP_DRAW_OBJECT 0x3810 9031f33ac92fSHawking Zhang #define regCP_DRAW_OBJECT_BASE_IDX 1 9032f33ac92fSHawking Zhang #define regCP_DRAW_OBJECT_COUNTER 0x3811 9033f33ac92fSHawking Zhang #define regCP_DRAW_OBJECT_COUNTER_BASE_IDX 1 9034f33ac92fSHawking Zhang #define regCP_DRAW_WINDOW_MASK_HI 0x3812 9035f33ac92fSHawking Zhang #define regCP_DRAW_WINDOW_MASK_HI_BASE_IDX 1 9036f33ac92fSHawking Zhang #define regCP_DRAW_WINDOW_HI 0x3813 9037f33ac92fSHawking Zhang #define regCP_DRAW_WINDOW_HI_BASE_IDX 1 9038f33ac92fSHawking Zhang #define regCP_DRAW_WINDOW_LO 0x3814 9039f33ac92fSHawking Zhang #define regCP_DRAW_WINDOW_LO_BASE_IDX 1 9040f33ac92fSHawking Zhang #define regCP_DRAW_WINDOW_CNTL 0x3815 9041f33ac92fSHawking Zhang #define regCP_DRAW_WINDOW_CNTL_BASE_IDX 1 9042f33ac92fSHawking Zhang #define regGRBM_PERFCOUNTER0_SELECT 0x3840 9043f33ac92fSHawking Zhang #define regGRBM_PERFCOUNTER0_SELECT_BASE_IDX 1 9044f33ac92fSHawking Zhang #define regGRBM_PERFCOUNTER1_SELECT 0x3841 9045f33ac92fSHawking Zhang #define regGRBM_PERFCOUNTER1_SELECT_BASE_IDX 1 9046f33ac92fSHawking Zhang #define regGRBM_SE0_PERFCOUNTER_SELECT 0x3842 9047f33ac92fSHawking Zhang #define regGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX 1 9048f33ac92fSHawking Zhang #define regGRBM_SE1_PERFCOUNTER_SELECT 0x3843 9049f33ac92fSHawking Zhang #define regGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX 1 9050f33ac92fSHawking Zhang #define regGRBM_SE2_PERFCOUNTER_SELECT 0x3844 9051f33ac92fSHawking Zhang #define regGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX 1 9052f33ac92fSHawking Zhang #define regGRBM_SE3_PERFCOUNTER_SELECT 0x3845 9053f33ac92fSHawking Zhang #define regGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX 1 9054f33ac92fSHawking Zhang #define regGRBM_SE4_PERFCOUNTER_SELECT 0x3846 9055f33ac92fSHawking Zhang #define regGRBM_SE4_PERFCOUNTER_SELECT_BASE_IDX 1 9056f33ac92fSHawking Zhang #define regGRBM_SE5_PERFCOUNTER_SELECT 0x3847 9057f33ac92fSHawking Zhang #define regGRBM_SE5_PERFCOUNTER_SELECT_BASE_IDX 1 9058f33ac92fSHawking Zhang #define regGRBM_SE6_PERFCOUNTER_SELECT 0x3848 9059f33ac92fSHawking Zhang #define regGRBM_SE6_PERFCOUNTER_SELECT_BASE_IDX 1 9060f33ac92fSHawking Zhang #define regGRBM_PERFCOUNTER0_SELECT_HI 0x384d 9061f33ac92fSHawking Zhang #define regGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX 1 9062f33ac92fSHawking Zhang #define regGRBM_PERFCOUNTER1_SELECT_HI 0x384e 9063f33ac92fSHawking Zhang #define regGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX 1 9064f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER0_SELECT 0x38a4 9065f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER0_SELECT_BASE_IDX 1 9066f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER0_SELECT1 0x38a5 9067f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER0_SELECT1_BASE_IDX 1 9068f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER1_SELECT 0x38a6 9069f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER1_SELECT_BASE_IDX 1 9070f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER1_SELECT1 0x38a7 9071f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER1_SELECT1_BASE_IDX 1 9072f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER2_SELECT 0x38a8 9073f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER2_SELECT_BASE_IDX 1 9074f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER2_SELECT1 0x38a9 9075f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER2_SELECT1_BASE_IDX 1 9076f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER3_SELECT 0x38aa 9077f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER3_SELECT_BASE_IDX 1 9078f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER3_SELECT1 0x38ab 9079f33ac92fSHawking Zhang #define regGE1_PERFCOUNTER3_SELECT1_BASE_IDX 1 9080f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER0_SELECT 0x38ac 9081f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER0_SELECT_BASE_IDX 1 9082f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER0_SELECT1 0x38ad 9083f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER0_SELECT1_BASE_IDX 1 9084f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER1_SELECT 0x38ae 9085f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER1_SELECT_BASE_IDX 1 9086f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER1_SELECT1 0x38af 9087f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER1_SELECT1_BASE_IDX 1 9088f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER2_SELECT 0x38b0 9089f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER2_SELECT_BASE_IDX 1 9090f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER2_SELECT1 0x38b1 9091f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER2_SELECT1_BASE_IDX 1 9092f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER3_SELECT 0x38b2 9093f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER3_SELECT_BASE_IDX 1 9094f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER3_SELECT1 0x38b3 9095f33ac92fSHawking Zhang #define regGE2_DIST_PERFCOUNTER3_SELECT1_BASE_IDX 1 9096f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER0_SELECT 0x38b4 9097f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER0_SELECT_BASE_IDX 1 9098f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER0_SELECT1 0x38b5 9099f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER0_SELECT1_BASE_IDX 1 9100f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER1_SELECT 0x38b6 9101f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER1_SELECT_BASE_IDX 1 9102f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER1_SELECT1 0x38b7 9103f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER1_SELECT1_BASE_IDX 1 9104f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER2_SELECT 0x38b8 9105f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER2_SELECT_BASE_IDX 1 9106f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER2_SELECT1 0x38b9 9107f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER2_SELECT1_BASE_IDX 1 9108f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER3_SELECT 0x38ba 9109f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER3_SELECT_BASE_IDX 1 9110f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER3_SELECT1 0x38bb 9111f33ac92fSHawking Zhang #define regGE2_SE_PERFCOUNTER3_SELECT1_BASE_IDX 1 9112f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER0_SELECT 0x3900 9113f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER0_SELECT_BASE_IDX 1 9114f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER0_SELECT1 0x3901 9115f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX 1 9116f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER1_SELECT 0x3902 9117f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER1_SELECT_BASE_IDX 1 9118f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER1_SELECT1 0x3903 9119f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX 1 9120f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER2_SELECT 0x3904 9121f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER2_SELECT_BASE_IDX 1 9122f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER2_SELECT1 0x3905 9123f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX 1 9124f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER3_SELECT 0x3906 9125f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER3_SELECT_BASE_IDX 1 9126f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER3_SELECT1 0x3907 9127f33ac92fSHawking Zhang #define regPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX 1 9128f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER0_SELECT 0x3940 9129f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER0_SELECT_BASE_IDX 1 9130f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER0_SELECT1 0x3941 9131f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX 1 9132f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER1_SELECT 0x3942 9133f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER1_SELECT_BASE_IDX 1 9134f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER2_SELECT 0x3943 9135f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER2_SELECT_BASE_IDX 1 9136f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER3_SELECT 0x3944 9137f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER3_SELECT_BASE_IDX 1 9138f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER4_SELECT 0x3945 9139f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER4_SELECT_BASE_IDX 1 9140f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER5_SELECT 0x3946 9141f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER5_SELECT_BASE_IDX 1 9142f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER6_SELECT 0x3947 9143f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER6_SELECT_BASE_IDX 1 9144f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER7_SELECT 0x3948 9145f33ac92fSHawking Zhang #define regPA_SC_PERFCOUNTER7_SELECT_BASE_IDX 1 9146f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER0_SELECT 0x3980 9147f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER0_SELECT_BASE_IDX 1 9148f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER1_SELECT 0x3981 9149f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER1_SELECT_BASE_IDX 1 9150f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER2_SELECT 0x3982 9151f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER2_SELECT_BASE_IDX 1 9152f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER3_SELECT 0x3983 9153f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER3_SELECT_BASE_IDX 1 9154f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER0_SELECT1 0x3984 9155f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER0_SELECT1_BASE_IDX 1 9156f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER1_SELECT1 0x3985 9157f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER1_SELECT1_BASE_IDX 1 9158f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER2_SELECT1 0x3986 9159f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER2_SELECT1_BASE_IDX 1 9160f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER3_SELECT1 0x3987 9161f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER3_SELECT1_BASE_IDX 1 9162f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER4_SELECT 0x3988 9163f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER4_SELECT_BASE_IDX 1 9164f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER5_SELECT 0x3989 9165f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER5_SELECT_BASE_IDX 1 9166f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER_BINS 0x398a 9167f33ac92fSHawking Zhang #define regSPI_PERFCOUNTER_BINS_BASE_IDX 1 9168f33ac92fSHawking Zhang #define regPC_PERFCOUNTER0_SELECT 0x398c 9169f33ac92fSHawking Zhang #define regPC_PERFCOUNTER0_SELECT_BASE_IDX 1 9170f33ac92fSHawking Zhang #define regPC_PERFCOUNTER1_SELECT 0x398d 9171f33ac92fSHawking Zhang #define regPC_PERFCOUNTER1_SELECT_BASE_IDX 1 9172f33ac92fSHawking Zhang #define regPC_PERFCOUNTER2_SELECT 0x398e 9173f33ac92fSHawking Zhang #define regPC_PERFCOUNTER2_SELECT_BASE_IDX 1 9174f33ac92fSHawking Zhang #define regPC_PERFCOUNTER3_SELECT 0x398f 9175f33ac92fSHawking Zhang #define regPC_PERFCOUNTER3_SELECT_BASE_IDX 1 9176f33ac92fSHawking Zhang #define regPC_PERFCOUNTER0_SELECT1 0x3990 9177f33ac92fSHawking Zhang #define regPC_PERFCOUNTER0_SELECT1_BASE_IDX 1 9178f33ac92fSHawking Zhang #define regPC_PERFCOUNTER1_SELECT1 0x3991 9179f33ac92fSHawking Zhang #define regPC_PERFCOUNTER1_SELECT1_BASE_IDX 1 9180f33ac92fSHawking Zhang #define regPC_PERFCOUNTER2_SELECT1 0x3992 9181f33ac92fSHawking Zhang #define regPC_PERFCOUNTER2_SELECT1_BASE_IDX 1 9182f33ac92fSHawking Zhang #define regPC_PERFCOUNTER3_SELECT1 0x3993 9183f33ac92fSHawking Zhang #define regPC_PERFCOUNTER3_SELECT1_BASE_IDX 1 9184f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER0_SELECT 0x39c0 9185f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER0_SELECT_BASE_IDX 1 9186f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER1_SELECT 0x39c1 9187f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER1_SELECT_BASE_IDX 1 9188f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER2_SELECT 0x39c2 9189f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER2_SELECT_BASE_IDX 1 9190f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER3_SELECT 0x39c3 9191f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER3_SELECT_BASE_IDX 1 9192f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER4_SELECT 0x39c4 9193f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER4_SELECT_BASE_IDX 1 9194f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER5_SELECT 0x39c5 9195f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER5_SELECT_BASE_IDX 1 9196f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER6_SELECT 0x39c6 9197f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER6_SELECT_BASE_IDX 1 9198f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER7_SELECT 0x39c7 9199f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER7_SELECT_BASE_IDX 1 9200f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER8_SELECT 0x39c8 9201f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER8_SELECT_BASE_IDX 1 9202f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER9_SELECT 0x39c9 9203f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER9_SELECT_BASE_IDX 1 9204f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER10_SELECT 0x39ca 9205f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER10_SELECT_BASE_IDX 1 9206f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER11_SELECT 0x39cb 9207f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER11_SELECT_BASE_IDX 1 9208f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER12_SELECT 0x39cc 9209f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER12_SELECT_BASE_IDX 1 9210f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER13_SELECT 0x39cd 9211f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER13_SELECT_BASE_IDX 1 9212f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER14_SELECT 0x39ce 9213f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER14_SELECT_BASE_IDX 1 9214f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER15_SELECT 0x39cf 9215f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER15_SELECT_BASE_IDX 1 9216f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER0_SELECT 0x39d0 9217f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER0_SELECT_BASE_IDX 1 9218f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER1_SELECT 0x39d1 9219f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER1_SELECT_BASE_IDX 1 9220f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER2_SELECT 0x39d2 9221f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER2_SELECT_BASE_IDX 1 9222f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER3_SELECT 0x39d3 9223f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER3_SELECT_BASE_IDX 1 9224f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER4_SELECT 0x39d4 9225f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER4_SELECT_BASE_IDX 1 9226f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER5_SELECT 0x39d5 9227f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER5_SELECT_BASE_IDX 1 9228f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER6_SELECT 0x39d6 9229f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER6_SELECT_BASE_IDX 1 9230f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER7_SELECT 0x39d7 9231f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER7_SELECT_BASE_IDX 1 9232f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER_CTRL 0x39d8 9233f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER_CTRL_BASE_IDX 1 9234f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER_CTRL2 0x39da 9235f33ac92fSHawking Zhang #define regSQG_PERFCOUNTER_CTRL2_BASE_IDX 1 9236f33ac92fSHawking Zhang #define regSQG_PERF_SAMPLE_FINISH 0x39db 9237f33ac92fSHawking Zhang #define regSQG_PERF_SAMPLE_FINISH_BASE_IDX 1 9238f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER_CTRL 0x39e0 9239f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER_CTRL_BASE_IDX 1 9240f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER_CTRL2 0x39e2 9241f33ac92fSHawking Zhang #define regSQ_PERFCOUNTER_CTRL2_BASE_IDX 1 9242f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_BUF0_BASE 0x39e8 9243f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_BUF0_BASE_BASE_IDX 1 9244f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_BUF0_SIZE 0x39e9 9245f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX 1 9246f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_BUF1_BASE 0x39ea 9247f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_BUF1_BASE_BASE_IDX 1 9248f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_BUF1_SIZE 0x39eb 9249f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX 1 9250f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_CTRL 0x39ec 9251f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_CTRL_BASE_IDX 1 9252f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_MASK 0x39ed 9253f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_MASK_BASE_IDX 1 9254f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_TOKEN_MASK 0x39ee 9255f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX 1 9256f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_WPTR 0x39ef 9257f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_WPTR_BASE_IDX 1 9258f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_STATUS 0x39f4 9259f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_STATUS_BASE_IDX 1 9260f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_STATUS2 0x39f5 9261f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_STATUS2_BASE_IDX 1 9262f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_GFX_DRAW_CNTR 0x39f6 9263f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX 1 9264f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_GFX_MARKER_CNTR 0x39f7 9265f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX 1 9266f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_HP3D_DRAW_CNTR 0x39f8 9267f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX 1 9268f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_HP3D_MARKER_CNTR 0x39f9 9269f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX 1 9270f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_DROPPED_CNTR 0x39fa 9271f33ac92fSHawking Zhang #define regSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX 1 9272f33ac92fSHawking Zhang #define regGCEA_PERFCOUNTER2_SELECT 0x3a00 9273f33ac92fSHawking Zhang #define regGCEA_PERFCOUNTER2_SELECT_BASE_IDX 1 9274f33ac92fSHawking Zhang #define regGCEA_PERFCOUNTER2_SELECT1 0x3a01 9275f33ac92fSHawking Zhang #define regGCEA_PERFCOUNTER2_SELECT1_BASE_IDX 1 9276f33ac92fSHawking Zhang #define regGCEA_PERFCOUNTER2_MODE 0x3a02 9277f33ac92fSHawking Zhang #define regGCEA_PERFCOUNTER2_MODE_BASE_IDX 1 9278f33ac92fSHawking Zhang #define regGCEA_PERFCOUNTER0_CFG 0x3a03 9279f33ac92fSHawking Zhang #define regGCEA_PERFCOUNTER0_CFG_BASE_IDX 1 9280f33ac92fSHawking Zhang #define regGCEA_PERFCOUNTER1_CFG 0x3a04 9281f33ac92fSHawking Zhang #define regGCEA_PERFCOUNTER1_CFG_BASE_IDX 1 9282f33ac92fSHawking Zhang #define regGCEA_PERFCOUNTER_RSLT_CNTL 0x3a05 9283f33ac92fSHawking Zhang #define regGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 9284f33ac92fSHawking Zhang #define regSX_PERFCOUNTER0_SELECT 0x3a40 9285f33ac92fSHawking Zhang #define regSX_PERFCOUNTER0_SELECT_BASE_IDX 1 9286f33ac92fSHawking Zhang #define regSX_PERFCOUNTER1_SELECT 0x3a41 9287f33ac92fSHawking Zhang #define regSX_PERFCOUNTER1_SELECT_BASE_IDX 1 9288f33ac92fSHawking Zhang #define regSX_PERFCOUNTER2_SELECT 0x3a42 9289f33ac92fSHawking Zhang #define regSX_PERFCOUNTER2_SELECT_BASE_IDX 1 9290f33ac92fSHawking Zhang #define regSX_PERFCOUNTER3_SELECT 0x3a43 9291f33ac92fSHawking Zhang #define regSX_PERFCOUNTER3_SELECT_BASE_IDX 1 9292f33ac92fSHawking Zhang #define regSX_PERFCOUNTER0_SELECT1 0x3a44 9293f33ac92fSHawking Zhang #define regSX_PERFCOUNTER0_SELECT1_BASE_IDX 1 9294f33ac92fSHawking Zhang #define regSX_PERFCOUNTER1_SELECT1 0x3a45 9295f33ac92fSHawking Zhang #define regSX_PERFCOUNTER1_SELECT1_BASE_IDX 1 9296f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER0_SELECT 0x3a80 9297f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER0_SELECT_BASE_IDX 1 9298f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER1_SELECT 0x3a81 9299f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER1_SELECT_BASE_IDX 1 9300f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER2_SELECT 0x3a82 9301f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER2_SELECT_BASE_IDX 1 9302f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER3_SELECT 0x3a83 9303f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER3_SELECT_BASE_IDX 1 9304f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER0_SELECT1 0x3a84 9305f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER0_SELECT1_BASE_IDX 1 9306f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER1_SELECT1 0x3a85 9307f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER1_SELECT1_BASE_IDX 1 9308f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER2_SELECT1 0x3a86 9309f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER2_SELECT1_BASE_IDX 1 9310f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER3_SELECT1 0x3a87 9311f33ac92fSHawking Zhang #define regGDS_PERFCOUNTER3_SELECT1_BASE_IDX 1 9312f33ac92fSHawking Zhang #define regTA_PERFCOUNTER0_SELECT 0x3ac0 9313f33ac92fSHawking Zhang #define regTA_PERFCOUNTER0_SELECT_BASE_IDX 1 9314f33ac92fSHawking Zhang #define regTA_PERFCOUNTER0_SELECT1 0x3ac1 9315f33ac92fSHawking Zhang #define regTA_PERFCOUNTER0_SELECT1_BASE_IDX 1 9316f33ac92fSHawking Zhang #define regTA_PERFCOUNTER1_SELECT 0x3ac2 9317f33ac92fSHawking Zhang #define regTA_PERFCOUNTER1_SELECT_BASE_IDX 1 9318f33ac92fSHawking Zhang #define regTD_PERFCOUNTER0_SELECT 0x3b00 9319f33ac92fSHawking Zhang #define regTD_PERFCOUNTER0_SELECT_BASE_IDX 1 9320f33ac92fSHawking Zhang #define regTD_PERFCOUNTER0_SELECT1 0x3b01 9321f33ac92fSHawking Zhang #define regTD_PERFCOUNTER0_SELECT1_BASE_IDX 1 9322f33ac92fSHawking Zhang #define regTD_PERFCOUNTER1_SELECT 0x3b02 9323f33ac92fSHawking Zhang #define regTD_PERFCOUNTER1_SELECT_BASE_IDX 1 9324f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER0_SELECT 0x3b40 9325f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER0_SELECT_BASE_IDX 1 9326f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER0_SELECT1 0x3b41 9327f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER0_SELECT1_BASE_IDX 1 9328f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER1_SELECT 0x3b42 9329f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER1_SELECT_BASE_IDX 1 9330f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER1_SELECT1 0x3b43 9331f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER1_SELECT1_BASE_IDX 1 9332f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER2_SELECT 0x3b44 9333f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER2_SELECT_BASE_IDX 1 9334f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER3_SELECT 0x3b45 9335f33ac92fSHawking Zhang #define regTCP_PERFCOUNTER3_SELECT_BASE_IDX 1 9336f33ac92fSHawking Zhang #define regGL2C_PERFCOUNTER0_SELECT 0x3b80 9337f33ac92fSHawking Zhang #define regGL2C_PERFCOUNTER0_SELECT_BASE_IDX 1 9338f33ac92fSHawking Zhang #define regGL2C_PERFCOUNTER0_SELECT1 0x3b81 9339f33ac92fSHawking Zhang #define regGL2C_PERFCOUNTER0_SELECT1_BASE_IDX 1 9340f33ac92fSHawking Zhang #define regGL2C_PERFCOUNTER1_SELECT 0x3b82 9341f33ac92fSHawking Zhang #define regGL2C_PERFCOUNTER1_SELECT_BASE_IDX 1 9342f33ac92fSHawking Zhang #define regGL2C_PERFCOUNTER1_SELECT1 0x3b83 9343f33ac92fSHawking Zhang #define regGL2C_PERFCOUNTER1_SELECT1_BASE_IDX 1 9344f33ac92fSHawking Zhang #define regGL2C_PERFCOUNTER2_SELECT 0x3b84 9345f33ac92fSHawking Zhang #define regGL2C_PERFCOUNTER2_SELECT_BASE_IDX 1 9346f33ac92fSHawking Zhang #define regGL2C_PERFCOUNTER3_SELECT 0x3b85 9347f33ac92fSHawking Zhang #define regGL2C_PERFCOUNTER3_SELECT_BASE_IDX 1 9348f33ac92fSHawking Zhang #define regGL2A_PERFCOUNTER0_SELECT 0x3b90 9349f33ac92fSHawking Zhang #define regGL2A_PERFCOUNTER0_SELECT_BASE_IDX 1 9350f33ac92fSHawking Zhang #define regGL2A_PERFCOUNTER0_SELECT1 0x3b91 9351f33ac92fSHawking Zhang #define regGL2A_PERFCOUNTER0_SELECT1_BASE_IDX 1 9352f33ac92fSHawking Zhang #define regGL2A_PERFCOUNTER1_SELECT 0x3b92 9353f33ac92fSHawking Zhang #define regGL2A_PERFCOUNTER1_SELECT_BASE_IDX 1 9354f33ac92fSHawking Zhang #define regGL2A_PERFCOUNTER1_SELECT1 0x3b93 9355f33ac92fSHawking Zhang #define regGL2A_PERFCOUNTER1_SELECT1_BASE_IDX 1 9356f33ac92fSHawking Zhang #define regGL2A_PERFCOUNTER2_SELECT 0x3b94 9357f33ac92fSHawking Zhang #define regGL2A_PERFCOUNTER2_SELECT_BASE_IDX 1 9358f33ac92fSHawking Zhang #define regGL2A_PERFCOUNTER3_SELECT 0x3b95 9359f33ac92fSHawking Zhang #define regGL2A_PERFCOUNTER3_SELECT_BASE_IDX 1 9360f33ac92fSHawking Zhang #define regGL1C_PERFCOUNTER0_SELECT 0x3ba0 9361f33ac92fSHawking Zhang #define regGL1C_PERFCOUNTER0_SELECT_BASE_IDX 1 9362f33ac92fSHawking Zhang #define regGL1C_PERFCOUNTER0_SELECT1 0x3ba1 9363f33ac92fSHawking Zhang #define regGL1C_PERFCOUNTER0_SELECT1_BASE_IDX 1 9364f33ac92fSHawking Zhang #define regGL1C_PERFCOUNTER1_SELECT 0x3ba2 9365f33ac92fSHawking Zhang #define regGL1C_PERFCOUNTER1_SELECT_BASE_IDX 1 9366f33ac92fSHawking Zhang #define regGL1C_PERFCOUNTER2_SELECT 0x3ba3 9367f33ac92fSHawking Zhang #define regGL1C_PERFCOUNTER2_SELECT_BASE_IDX 1 9368f33ac92fSHawking Zhang #define regGL1C_PERFCOUNTER3_SELECT 0x3ba4 9369f33ac92fSHawking Zhang #define regGL1C_PERFCOUNTER3_SELECT_BASE_IDX 1 9370f33ac92fSHawking Zhang #define regCHC_PERFCOUNTER0_SELECT 0x3bc0 9371f33ac92fSHawking Zhang #define regCHC_PERFCOUNTER0_SELECT_BASE_IDX 1 9372f33ac92fSHawking Zhang #define regCHC_PERFCOUNTER0_SELECT1 0x3bc1 9373f33ac92fSHawking Zhang #define regCHC_PERFCOUNTER0_SELECT1_BASE_IDX 1 9374f33ac92fSHawking Zhang #define regCHC_PERFCOUNTER1_SELECT 0x3bc2 9375f33ac92fSHawking Zhang #define regCHC_PERFCOUNTER1_SELECT_BASE_IDX 1 9376f33ac92fSHawking Zhang #define regCHC_PERFCOUNTER2_SELECT 0x3bc3 9377f33ac92fSHawking Zhang #define regCHC_PERFCOUNTER2_SELECT_BASE_IDX 1 9378f33ac92fSHawking Zhang #define regCHC_PERFCOUNTER3_SELECT 0x3bc4 9379f33ac92fSHawking Zhang #define regCHC_PERFCOUNTER3_SELECT_BASE_IDX 1 9380f33ac92fSHawking Zhang #define regCHCG_PERFCOUNTER0_SELECT 0x3bc6 9381f33ac92fSHawking Zhang #define regCHCG_PERFCOUNTER0_SELECT_BASE_IDX 1 9382f33ac92fSHawking Zhang #define regCHCG_PERFCOUNTER0_SELECT1 0x3bc7 9383f33ac92fSHawking Zhang #define regCHCG_PERFCOUNTER0_SELECT1_BASE_IDX 1 9384f33ac92fSHawking Zhang #define regCHCG_PERFCOUNTER1_SELECT 0x3bc8 9385f33ac92fSHawking Zhang #define regCHCG_PERFCOUNTER1_SELECT_BASE_IDX 1 9386f33ac92fSHawking Zhang #define regCHCG_PERFCOUNTER2_SELECT 0x3bc9 9387f33ac92fSHawking Zhang #define regCHCG_PERFCOUNTER2_SELECT_BASE_IDX 1 9388f33ac92fSHawking Zhang #define regCHCG_PERFCOUNTER3_SELECT 0x3bca 9389f33ac92fSHawking Zhang #define regCHCG_PERFCOUNTER3_SELECT_BASE_IDX 1 9390f33ac92fSHawking Zhang #define regCB_PERFCOUNTER_FILTER 0x3c00 9391f33ac92fSHawking Zhang #define regCB_PERFCOUNTER_FILTER_BASE_IDX 1 9392f33ac92fSHawking Zhang #define regCB_PERFCOUNTER0_SELECT 0x3c01 9393f33ac92fSHawking Zhang #define regCB_PERFCOUNTER0_SELECT_BASE_IDX 1 9394f33ac92fSHawking Zhang #define regCB_PERFCOUNTER0_SELECT1 0x3c02 9395f33ac92fSHawking Zhang #define regCB_PERFCOUNTER0_SELECT1_BASE_IDX 1 9396f33ac92fSHawking Zhang #define regCB_PERFCOUNTER1_SELECT 0x3c03 9397f33ac92fSHawking Zhang #define regCB_PERFCOUNTER1_SELECT_BASE_IDX 1 9398f33ac92fSHawking Zhang #define regCB_PERFCOUNTER2_SELECT 0x3c04 9399f33ac92fSHawking Zhang #define regCB_PERFCOUNTER2_SELECT_BASE_IDX 1 9400f33ac92fSHawking Zhang #define regCB_PERFCOUNTER3_SELECT 0x3c05 9401f33ac92fSHawking Zhang #define regCB_PERFCOUNTER3_SELECT_BASE_IDX 1 9402f33ac92fSHawking Zhang #define regDB_PERFCOUNTER0_SELECT 0x3c40 9403f33ac92fSHawking Zhang #define regDB_PERFCOUNTER0_SELECT_BASE_IDX 1 9404f33ac92fSHawking Zhang #define regDB_PERFCOUNTER0_SELECT1 0x3c41 9405f33ac92fSHawking Zhang #define regDB_PERFCOUNTER0_SELECT1_BASE_IDX 1 9406f33ac92fSHawking Zhang #define regDB_PERFCOUNTER1_SELECT 0x3c42 9407f33ac92fSHawking Zhang #define regDB_PERFCOUNTER1_SELECT_BASE_IDX 1 9408f33ac92fSHawking Zhang #define regDB_PERFCOUNTER1_SELECT1 0x3c43 9409f33ac92fSHawking Zhang #define regDB_PERFCOUNTER1_SELECT1_BASE_IDX 1 9410f33ac92fSHawking Zhang #define regDB_PERFCOUNTER2_SELECT 0x3c44 9411f33ac92fSHawking Zhang #define regDB_PERFCOUNTER2_SELECT_BASE_IDX 1 9412f33ac92fSHawking Zhang #define regDB_PERFCOUNTER3_SELECT 0x3c46 9413f33ac92fSHawking Zhang #define regDB_PERFCOUNTER3_SELECT_BASE_IDX 1 9414f33ac92fSHawking Zhang #define regRLC_SPM_PERFMON_CNTL 0x3c80 9415f33ac92fSHawking Zhang #define regRLC_SPM_PERFMON_CNTL_BASE_IDX 1 9416f33ac92fSHawking Zhang #define regRLC_SPM_PERFMON_RING_BASE_LO 0x3c81 9417f33ac92fSHawking Zhang #define regRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX 1 9418f33ac92fSHawking Zhang #define regRLC_SPM_PERFMON_RING_BASE_HI 0x3c82 9419f33ac92fSHawking Zhang #define regRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX 1 9420f33ac92fSHawking Zhang #define regRLC_SPM_PERFMON_RING_SIZE 0x3c83 9421f33ac92fSHawking Zhang #define regRLC_SPM_PERFMON_RING_SIZE_BASE_IDX 1 9422f33ac92fSHawking Zhang #define regRLC_SPM_RING_WRPTR 0x3c84 9423f33ac92fSHawking Zhang #define regRLC_SPM_RING_WRPTR_BASE_IDX 1 9424f33ac92fSHawking Zhang #define regRLC_SPM_RING_RDPTR 0x3c85 9425f33ac92fSHawking Zhang #define regRLC_SPM_RING_RDPTR_BASE_IDX 1 9426f33ac92fSHawking Zhang #define regRLC_SPM_SEGMENT_THRESHOLD 0x3c86 9427f33ac92fSHawking Zhang #define regRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX 1 9428f33ac92fSHawking Zhang #define regRLC_SPM_PERFMON_SEGMENT_SIZE 0x3c87 9429f33ac92fSHawking Zhang #define regRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX 1 9430f33ac92fSHawking Zhang #define regRLC_SPM_GLOBAL_MUXSEL_ADDR 0x3c88 9431f33ac92fSHawking Zhang #define regRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX 1 9432f33ac92fSHawking Zhang #define regRLC_SPM_GLOBAL_MUXSEL_DATA 0x3c89 9433f33ac92fSHawking Zhang #define regRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX 1 9434f33ac92fSHawking Zhang #define regRLC_SPM_SE_MUXSEL_ADDR 0x3c8a 9435f33ac92fSHawking Zhang #define regRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX 1 9436f33ac92fSHawking Zhang #define regRLC_SPM_SE_MUXSEL_DATA 0x3c8b 9437f33ac92fSHawking Zhang #define regRLC_SPM_SE_MUXSEL_DATA_BASE_IDX 1 9438f33ac92fSHawking Zhang #define regRLC_SPM_ACCUM_DATARAM_ADDR 0x3c92 9439f33ac92fSHawking Zhang #define regRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX 1 9440f33ac92fSHawking Zhang #define regRLC_SPM_ACCUM_DATARAM_DATA 0x3c93 9441f33ac92fSHawking Zhang #define regRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX 1 9442f33ac92fSHawking Zhang #define regRLC_SPM_ACCUM_SWA_DATARAM_ADDR 0x3c94 9443f33ac92fSHawking Zhang #define regRLC_SPM_ACCUM_SWA_DATARAM_ADDR_BASE_IDX 1 9444f33ac92fSHawking Zhang #define regRLC_SPM_ACCUM_SWA_DATARAM_DATA 0x3c95 9445f33ac92fSHawking Zhang #define regRLC_SPM_ACCUM_SWA_DATARAM_DATA_BASE_IDX 1 9446f33ac92fSHawking Zhang #define regRLC_SPM_ACCUM_CTRLRAM_ADDR 0x3c96 9447f33ac92fSHawking Zhang #define regRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX 1 9448f33ac92fSHawking Zhang #define regRLC_SPM_ACCUM_CTRLRAM_DATA 0x3c97 9449f33ac92fSHawking Zhang #define regRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX 1 9450f33ac92fSHawking Zhang #define regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET 0x3c98 9451f33ac92fSHawking Zhang #define regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET_BASE_IDX 1 9452f33ac92fSHawking Zhang #define regRLC_SPM_ACCUM_STATUS 0x3c99 9453f33ac92fSHawking Zhang #define regRLC_SPM_ACCUM_STATUS_BASE_IDX 1 9454f33ac92fSHawking Zhang #define regRLC_SPM_ACCUM_CTRL 0x3c9a 9455f33ac92fSHawking Zhang #define regRLC_SPM_ACCUM_CTRL_BASE_IDX 1 9456f33ac92fSHawking Zhang #define regRLC_SPM_ACCUM_MODE 0x3c9b 9457f33ac92fSHawking Zhang #define regRLC_SPM_ACCUM_MODE_BASE_IDX 1 9458f33ac92fSHawking Zhang #define regRLC_SPM_ACCUM_THRESHOLD 0x3c9c 9459f33ac92fSHawking Zhang #define regRLC_SPM_ACCUM_THRESHOLD_BASE_IDX 1 9460f33ac92fSHawking Zhang #define regRLC_SPM_ACCUM_SAMPLES_REQUESTED 0x3c9d 9461f33ac92fSHawking Zhang #define regRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX 1 9462f33ac92fSHawking Zhang #define regRLC_SPM_ACCUM_DATARAM_WRCOUNT 0x3c9e 9463f33ac92fSHawking Zhang #define regRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX 1 9464f33ac92fSHawking Zhang #define regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS 0x3c9f 9465f33ac92fSHawking Zhang #define regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS_BASE_IDX 1 9466f33ac92fSHawking Zhang #define regRLC_SPM_PAUSE 0x3ca2 9467f33ac92fSHawking Zhang #define regRLC_SPM_PAUSE_BASE_IDX 1 9468f33ac92fSHawking Zhang #define regRLC_SPM_STATUS 0x3ca3 9469f33ac92fSHawking Zhang #define regRLC_SPM_STATUS_BASE_IDX 1 9470f33ac92fSHawking Zhang #define regRLC_SPM_GFXCLOCK_LOWCOUNT 0x3ca4 9471f33ac92fSHawking Zhang #define regRLC_SPM_GFXCLOCK_LOWCOUNT_BASE_IDX 1 9472f33ac92fSHawking Zhang #define regRLC_SPM_GFXCLOCK_HIGHCOUNT 0x3ca5 9473f33ac92fSHawking Zhang #define regRLC_SPM_GFXCLOCK_HIGHCOUNT_BASE_IDX 1 9474f33ac92fSHawking Zhang #define regRLC_SPM_MODE 0x3cad 9475f33ac92fSHawking Zhang #define regRLC_SPM_MODE_BASE_IDX 1 9476f33ac92fSHawking Zhang #define regRLC_SPM_RSPM_REQ_DATA_LO 0x3cae 9477f33ac92fSHawking Zhang #define regRLC_SPM_RSPM_REQ_DATA_LO_BASE_IDX 1 9478f33ac92fSHawking Zhang #define regRLC_SPM_RSPM_REQ_DATA_HI 0x3caf 9479f33ac92fSHawking Zhang #define regRLC_SPM_RSPM_REQ_DATA_HI_BASE_IDX 1 9480f33ac92fSHawking Zhang #define regRLC_SPM_RSPM_REQ_OP 0x3cb0 9481f33ac92fSHawking Zhang #define regRLC_SPM_RSPM_REQ_OP_BASE_IDX 1 9482f33ac92fSHawking Zhang #define regRLC_SPM_RSPM_RET_DATA 0x3cb1 9483f33ac92fSHawking Zhang #define regRLC_SPM_RSPM_RET_DATA_BASE_IDX 1 9484f33ac92fSHawking Zhang #define regRLC_SPM_RSPM_RET_OP 0x3cb2 9485f33ac92fSHawking Zhang #define regRLC_SPM_RSPM_RET_OP_BASE_IDX 1 9486f33ac92fSHawking Zhang #define regRLC_SPM_SE_RSPM_REQ_DATA_LO 0x3cb3 9487f33ac92fSHawking Zhang #define regRLC_SPM_SE_RSPM_REQ_DATA_LO_BASE_IDX 1 9488f33ac92fSHawking Zhang #define regRLC_SPM_SE_RSPM_REQ_DATA_HI 0x3cb4 9489f33ac92fSHawking Zhang #define regRLC_SPM_SE_RSPM_REQ_DATA_HI_BASE_IDX 1 9490f33ac92fSHawking Zhang #define regRLC_SPM_SE_RSPM_REQ_OP 0x3cb5 9491f33ac92fSHawking Zhang #define regRLC_SPM_SE_RSPM_REQ_OP_BASE_IDX 1 9492f33ac92fSHawking Zhang #define regRLC_SPM_SE_RSPM_RET_DATA 0x3cb6 9493f33ac92fSHawking Zhang #define regRLC_SPM_SE_RSPM_RET_DATA_BASE_IDX 1 9494f33ac92fSHawking Zhang #define regRLC_SPM_SE_RSPM_RET_OP 0x3cb7 9495f33ac92fSHawking Zhang #define regRLC_SPM_SE_RSPM_RET_OP_BASE_IDX 1 9496f33ac92fSHawking Zhang #define regRLC_SPM_RSPM_CMD 0x3cb8 9497f33ac92fSHawking Zhang #define regRLC_SPM_RSPM_CMD_BASE_IDX 1 9498f33ac92fSHawking Zhang #define regRLC_SPM_RSPM_CMD_ACK 0x3cb9 9499f33ac92fSHawking Zhang #define regRLC_SPM_RSPM_CMD_ACK_BASE_IDX 1 9500f33ac92fSHawking Zhang #define regRLC_SPM_SPARE 0x3cbf 9501f33ac92fSHawking Zhang #define regRLC_SPM_SPARE_BASE_IDX 1 9502f33ac92fSHawking Zhang #define regRLC_PERFMON_CNTL 0x3cc0 9503f33ac92fSHawking Zhang #define regRLC_PERFMON_CNTL_BASE_IDX 1 9504f33ac92fSHawking Zhang #define regRLC_PERFCOUNTER0_SELECT 0x3cc1 9505f33ac92fSHawking Zhang #define regRLC_PERFCOUNTER0_SELECT_BASE_IDX 1 9506f33ac92fSHawking Zhang #define regRLC_PERFCOUNTER1_SELECT 0x3cc2 9507f33ac92fSHawking Zhang #define regRLC_PERFCOUNTER1_SELECT_BASE_IDX 1 9508f33ac92fSHawking Zhang #define regRLC_GPU_IOV_PERF_CNT_CNTL 0x3cc3 9509f33ac92fSHawking Zhang #define regRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX 1 9510f33ac92fSHawking Zhang #define regRLC_GPU_IOV_PERF_CNT_WR_ADDR 0x3cc4 9511f33ac92fSHawking Zhang #define regRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX 1 9512f33ac92fSHawking Zhang #define regRLC_GPU_IOV_PERF_CNT_WR_DATA 0x3cc5 9513f33ac92fSHawking Zhang #define regRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX 1 9514f33ac92fSHawking Zhang #define regRLC_GPU_IOV_PERF_CNT_RD_ADDR 0x3cc6 9515f33ac92fSHawking Zhang #define regRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX 1 9516f33ac92fSHawking Zhang #define regRLC_GPU_IOV_PERF_CNT_RD_DATA 0x3cc7 9517f33ac92fSHawking Zhang #define regRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX 1 9518f33ac92fSHawking Zhang #define regRMI_PERFCOUNTER0_SELECT 0x3d00 9519f33ac92fSHawking Zhang #define regRMI_PERFCOUNTER0_SELECT_BASE_IDX 1 9520f33ac92fSHawking Zhang #define regRMI_PERFCOUNTER0_SELECT1 0x3d01 9521f33ac92fSHawking Zhang #define regRMI_PERFCOUNTER0_SELECT1_BASE_IDX 1 9522f33ac92fSHawking Zhang #define regRMI_PERFCOUNTER1_SELECT 0x3d02 9523f33ac92fSHawking Zhang #define regRMI_PERFCOUNTER1_SELECT_BASE_IDX 1 9524f33ac92fSHawking Zhang #define regRMI_PERFCOUNTER2_SELECT 0x3d03 9525f33ac92fSHawking Zhang #define regRMI_PERFCOUNTER2_SELECT_BASE_IDX 1 9526f33ac92fSHawking Zhang #define regRMI_PERFCOUNTER2_SELECT1 0x3d04 9527f33ac92fSHawking Zhang #define regRMI_PERFCOUNTER2_SELECT1_BASE_IDX 1 9528f33ac92fSHawking Zhang #define regRMI_PERFCOUNTER3_SELECT 0x3d05 9529f33ac92fSHawking Zhang #define regRMI_PERFCOUNTER3_SELECT_BASE_IDX 1 9530f33ac92fSHawking Zhang #define regRMI_PERF_COUNTER_CNTL 0x3d06 9531f33ac92fSHawking Zhang #define regRMI_PERF_COUNTER_CNTL_BASE_IDX 1 9532f33ac92fSHawking Zhang #define regGCR_PERFCOUNTER0_SELECT 0x3d60 9533f33ac92fSHawking Zhang #define regGCR_PERFCOUNTER0_SELECT_BASE_IDX 1 9534f33ac92fSHawking Zhang #define regGCR_PERFCOUNTER0_SELECT1 0x3d61 9535f33ac92fSHawking Zhang #define regGCR_PERFCOUNTER0_SELECT1_BASE_IDX 1 9536f33ac92fSHawking Zhang #define regGCR_PERFCOUNTER1_SELECT 0x3d62 9537f33ac92fSHawking Zhang #define regGCR_PERFCOUNTER1_SELECT_BASE_IDX 1 9538f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER0_SELECT 0x3d80 9539f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER0_SELECT_BASE_IDX 1 9540f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER0_SELECT1 0x3d81 9541f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX 1 9542f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER1_SELECT 0x3d82 9543f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER1_SELECT_BASE_IDX 1 9544f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER2_SELECT 0x3d83 9545f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER2_SELECT_BASE_IDX 1 9546f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER3_SELECT 0x3d84 9547f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER3_SELECT_BASE_IDX 1 9548f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER4_SELECT 0x3d85 9549f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER4_SELECT_BASE_IDX 1 9550f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER5_SELECT 0x3d86 9551f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER5_SELECT_BASE_IDX 1 9552f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER6_SELECT 0x3d87 9553f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER6_SELECT_BASE_IDX 1 9554f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER7_SELECT 0x3d88 9555f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER7_SELECT_BASE_IDX 1 9556f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER1_SELECT1 0x3d90 9557f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX 1 9558f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER2_SELECT1 0x3d91 9559f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX 1 9560f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER3_SELECT1 0x3d92 9561f33ac92fSHawking Zhang #define regPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX 1 9562f33ac92fSHawking Zhang #define regUTCL1_PERFCOUNTER0_SELECT 0x3da0 9563f33ac92fSHawking Zhang #define regUTCL1_PERFCOUNTER0_SELECT_BASE_IDX 1 9564f33ac92fSHawking Zhang #define regUTCL1_PERFCOUNTER1_SELECT 0x3da1 9565f33ac92fSHawking Zhang #define regUTCL1_PERFCOUNTER1_SELECT_BASE_IDX 1 9566f33ac92fSHawking Zhang #define regUTCL1_PERFCOUNTER2_SELECT 0x3da2 9567f33ac92fSHawking Zhang #define regUTCL1_PERFCOUNTER2_SELECT_BASE_IDX 1 9568f33ac92fSHawking Zhang #define regUTCL1_PERFCOUNTER3_SELECT 0x3da3 9569f33ac92fSHawking Zhang #define regUTCL1_PERFCOUNTER3_SELECT_BASE_IDX 1 9570f33ac92fSHawking Zhang #define regGL1A_PERFCOUNTER0_SELECT 0x3dc0 9571f33ac92fSHawking Zhang #define regGL1A_PERFCOUNTER0_SELECT_BASE_IDX 1 9572f33ac92fSHawking Zhang #define regGL1A_PERFCOUNTER0_SELECT1 0x3dc1 9573f33ac92fSHawking Zhang #define regGL1A_PERFCOUNTER0_SELECT1_BASE_IDX 1 9574f33ac92fSHawking Zhang #define regGL1A_PERFCOUNTER1_SELECT 0x3dc2 9575f33ac92fSHawking Zhang #define regGL1A_PERFCOUNTER1_SELECT_BASE_IDX 1 9576f33ac92fSHawking Zhang #define regGL1A_PERFCOUNTER2_SELECT 0x3dc3 9577f33ac92fSHawking Zhang #define regGL1A_PERFCOUNTER2_SELECT_BASE_IDX 1 9578f33ac92fSHawking Zhang #define regGL1A_PERFCOUNTER3_SELECT 0x3dc4 9579f33ac92fSHawking Zhang #define regGL1A_PERFCOUNTER3_SELECT_BASE_IDX 1 9580f33ac92fSHawking Zhang #define regGL1H_PERFCOUNTER0_SELECT 0x3dd0 9581f33ac92fSHawking Zhang #define regGL1H_PERFCOUNTER0_SELECT_BASE_IDX 1 9582f33ac92fSHawking Zhang #define regGL1H_PERFCOUNTER0_SELECT1 0x3dd1 9583f33ac92fSHawking Zhang #define regGL1H_PERFCOUNTER0_SELECT1_BASE_IDX 1 9584f33ac92fSHawking Zhang #define regGL1H_PERFCOUNTER1_SELECT 0x3dd2 9585f33ac92fSHawking Zhang #define regGL1H_PERFCOUNTER1_SELECT_BASE_IDX 1 9586f33ac92fSHawking Zhang #define regGL1H_PERFCOUNTER2_SELECT 0x3dd3 9587f33ac92fSHawking Zhang #define regGL1H_PERFCOUNTER2_SELECT_BASE_IDX 1 9588f33ac92fSHawking Zhang #define regGL1H_PERFCOUNTER3_SELECT 0x3dd4 9589f33ac92fSHawking Zhang #define regGL1H_PERFCOUNTER3_SELECT_BASE_IDX 1 9590f33ac92fSHawking Zhang #define regCHA_PERFCOUNTER0_SELECT 0x3de0 9591f33ac92fSHawking Zhang #define regCHA_PERFCOUNTER0_SELECT_BASE_IDX 1 9592f33ac92fSHawking Zhang #define regCHA_PERFCOUNTER0_SELECT1 0x3de1 9593f33ac92fSHawking Zhang #define regCHA_PERFCOUNTER0_SELECT1_BASE_IDX 1 9594f33ac92fSHawking Zhang #define regCHA_PERFCOUNTER1_SELECT 0x3de2 9595f33ac92fSHawking Zhang #define regCHA_PERFCOUNTER1_SELECT_BASE_IDX 1 9596f33ac92fSHawking Zhang #define regCHA_PERFCOUNTER2_SELECT 0x3de3 9597f33ac92fSHawking Zhang #define regCHA_PERFCOUNTER2_SELECT_BASE_IDX 1 9598f33ac92fSHawking Zhang #define regCHA_PERFCOUNTER3_SELECT 0x3de4 9599f33ac92fSHawking Zhang #define regCHA_PERFCOUNTER3_SELECT_BASE_IDX 1 9600f33ac92fSHawking Zhang #define regGUS_PERFCOUNTER2_SELECT 0x3e00 9601f33ac92fSHawking Zhang #define regGUS_PERFCOUNTER2_SELECT_BASE_IDX 1 9602f33ac92fSHawking Zhang #define regGUS_PERFCOUNTER2_SELECT1 0x3e01 9603f33ac92fSHawking Zhang #define regGUS_PERFCOUNTER2_SELECT1_BASE_IDX 1 9604f33ac92fSHawking Zhang #define regGUS_PERFCOUNTER2_MODE 0x3e02 9605f33ac92fSHawking Zhang #define regGUS_PERFCOUNTER2_MODE_BASE_IDX 1 9606f33ac92fSHawking Zhang #define regGUS_PERFCOUNTER0_CFG 0x3e03 9607f33ac92fSHawking Zhang #define regGUS_PERFCOUNTER0_CFG_BASE_IDX 1 9608f33ac92fSHawking Zhang #define regGUS_PERFCOUNTER1_CFG 0x3e04 9609f33ac92fSHawking Zhang #define regGUS_PERFCOUNTER1_CFG_BASE_IDX 1 9610f33ac92fSHawking Zhang #define regGUS_PERFCOUNTER_RSLT_CNTL 0x3e05 9611f33ac92fSHawking Zhang #define regGUS_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 9612f33ac92fSHawking Zhang 9613f33ac92fSHawking Zhang 9614f33ac92fSHawking Zhang // addressBlock: gc_grtavfs_grtavfs_dec 9615f33ac92fSHawking Zhang // base address: 0x3ac00 9616f33ac92fSHawking Zhang #define regGRTAVFS_RTAVFS_REG_ADDR 0x4b00 9617f33ac92fSHawking Zhang #define regGRTAVFS_RTAVFS_REG_ADDR_BASE_IDX 1 9618f33ac92fSHawking Zhang #define regGRTAVFS_RTAVFS_WR_DATA 0x4b01 9619f33ac92fSHawking Zhang #define regGRTAVFS_RTAVFS_WR_DATA_BASE_IDX 1 9620f33ac92fSHawking Zhang #define regGRTAVFS_GENERAL_0 0x4b02 9621f33ac92fSHawking Zhang #define regGRTAVFS_GENERAL_0_BASE_IDX 1 9622f33ac92fSHawking Zhang #define regGRTAVFS_RTAVFS_RD_DATA 0x4b03 9623f33ac92fSHawking Zhang #define regGRTAVFS_RTAVFS_RD_DATA_BASE_IDX 1 9624f33ac92fSHawking Zhang #define regGRTAVFS_RTAVFS_REG_CTRL 0x4b04 9625f33ac92fSHawking Zhang #define regGRTAVFS_RTAVFS_REG_CTRL_BASE_IDX 1 9626f33ac92fSHawking Zhang #define regGRTAVFS_RTAVFS_REG_STATUS 0x4b05 9627f33ac92fSHawking Zhang #define regGRTAVFS_RTAVFS_REG_STATUS_BASE_IDX 1 9628f33ac92fSHawking Zhang #define regGRTAVFS_TARG_FREQ 0x4b06 9629f33ac92fSHawking Zhang #define regGRTAVFS_TARG_FREQ_BASE_IDX 1 9630f33ac92fSHawking Zhang #define regGRTAVFS_TARG_VOLT 0x4b07 9631f33ac92fSHawking Zhang #define regGRTAVFS_TARG_VOLT_BASE_IDX 1 9632f33ac92fSHawking Zhang #define regGRTAVFS_SOFT_RESET 0x4b0c 9633f33ac92fSHawking Zhang #define regGRTAVFS_SOFT_RESET_BASE_IDX 1 9634f33ac92fSHawking Zhang #define regGRTAVFS_PSM_CNTL 0x4b0d 9635f33ac92fSHawking Zhang #define regGRTAVFS_PSM_CNTL_BASE_IDX 1 9636f33ac92fSHawking Zhang #define regGRTAVFS_CLK_CNTL 0x4b0e 9637f33ac92fSHawking Zhang #define regGRTAVFS_CLK_CNTL_BASE_IDX 1 9638f33ac92fSHawking Zhang 9639f33ac92fSHawking Zhang 9640f33ac92fSHawking Zhang // addressBlock: gc_grtavfs_se_grtavfs_dec 9641f33ac92fSHawking Zhang // base address: 0x3ad00 9642f33ac92fSHawking Zhang #define regGRTAVFS_SE_RTAVFS_REG_ADDR 0x4b40 9643f33ac92fSHawking Zhang #define regGRTAVFS_SE_RTAVFS_REG_ADDR_BASE_IDX 1 9644f33ac92fSHawking Zhang #define regGRTAVFS_SE_RTAVFS_WR_DATA 0x4b41 9645f33ac92fSHawking Zhang #define regGRTAVFS_SE_RTAVFS_WR_DATA_BASE_IDX 1 9646f33ac92fSHawking Zhang #define regGRTAVFS_SE_GENERAL_0 0x4b42 9647f33ac92fSHawking Zhang #define regGRTAVFS_SE_GENERAL_0_BASE_IDX 1 9648f33ac92fSHawking Zhang #define regGRTAVFS_SE_RTAVFS_RD_DATA 0x4b43 9649f33ac92fSHawking Zhang #define regGRTAVFS_SE_RTAVFS_RD_DATA_BASE_IDX 1 9650f33ac92fSHawking Zhang #define regGRTAVFS_SE_RTAVFS_REG_CTRL 0x4b44 9651f33ac92fSHawking Zhang #define regGRTAVFS_SE_RTAVFS_REG_CTRL_BASE_IDX 1 9652f33ac92fSHawking Zhang #define regGRTAVFS_SE_RTAVFS_REG_STATUS 0x4b45 9653f33ac92fSHawking Zhang #define regGRTAVFS_SE_RTAVFS_REG_STATUS_BASE_IDX 1 9654f33ac92fSHawking Zhang #define regGRTAVFS_SE_TARG_FREQ 0x4b46 9655f33ac92fSHawking Zhang #define regGRTAVFS_SE_TARG_FREQ_BASE_IDX 1 9656f33ac92fSHawking Zhang #define regGRTAVFS_SE_TARG_VOLT 0x4b47 9657f33ac92fSHawking Zhang #define regGRTAVFS_SE_TARG_VOLT_BASE_IDX 1 9658f33ac92fSHawking Zhang #define regGRTAVFS_SE_SOFT_RESET 0x4b4c 9659f33ac92fSHawking Zhang #define regGRTAVFS_SE_SOFT_RESET_BASE_IDX 1 9660f33ac92fSHawking Zhang #define regGRTAVFS_SE_PSM_CNTL 0x4b4d 9661f33ac92fSHawking Zhang #define regGRTAVFS_SE_PSM_CNTL_BASE_IDX 1 9662f33ac92fSHawking Zhang #define regGRTAVFS_SE_CLK_CNTL 0x4b4e 9663f33ac92fSHawking Zhang #define regGRTAVFS_SE_CLK_CNTL_BASE_IDX 1 9664f33ac92fSHawking Zhang 9665f33ac92fSHawking Zhang 9666f33ac92fSHawking Zhang // addressBlock: gc_grtavfsdec 9667f33ac92fSHawking Zhang // base address: 0x3ac00 9668f33ac92fSHawking Zhang #define regRTAVFS_RTAVFS_REG_ADDR 0x4b00 9669f33ac92fSHawking Zhang #define regRTAVFS_RTAVFS_REG_ADDR_BASE_IDX 1 9670f33ac92fSHawking Zhang #define regRTAVFS_RTAVFS_WR_DATA 0x4b01 9671f33ac92fSHawking Zhang #define regRTAVFS_RTAVFS_WR_DATA_BASE_IDX 1 9672f33ac92fSHawking Zhang 9673f33ac92fSHawking Zhang 9674f33ac92fSHawking Zhang // addressBlock: gc_cphypdec 9675f33ac92fSHawking Zhang // base address: 0x3e000 9676f33ac92fSHawking Zhang #define regCP_HYP_PFP_UCODE_ADDR 0x5814 9677f33ac92fSHawking Zhang #define regCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 9678f33ac92fSHawking Zhang #define regCP_PFP_UCODE_ADDR 0x5814 9679f33ac92fSHawking Zhang #define regCP_PFP_UCODE_ADDR_BASE_IDX 1 9680f33ac92fSHawking Zhang #define regCP_HYP_PFP_UCODE_DATA 0x5815 9681f33ac92fSHawking Zhang #define regCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 9682f33ac92fSHawking Zhang #define regCP_PFP_UCODE_DATA 0x5815 9683f33ac92fSHawking Zhang #define regCP_PFP_UCODE_DATA_BASE_IDX 1 9684f33ac92fSHawking Zhang #define regCP_HYP_ME_UCODE_ADDR 0x5816 9685f33ac92fSHawking Zhang #define regCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 9686f33ac92fSHawking Zhang #define regCP_ME_RAM_RADDR 0x5816 9687f33ac92fSHawking Zhang #define regCP_ME_RAM_RADDR_BASE_IDX 1 9688f33ac92fSHawking Zhang #define regCP_ME_RAM_WADDR 0x5816 9689f33ac92fSHawking Zhang #define regCP_ME_RAM_WADDR_BASE_IDX 1 9690f33ac92fSHawking Zhang #define regCP_HYP_ME_UCODE_DATA 0x5817 9691f33ac92fSHawking Zhang #define regCP_HYP_ME_UCODE_DATA_BASE_IDX 1 9692f33ac92fSHawking Zhang #define regCP_ME_RAM_DATA 0x5817 9693f33ac92fSHawking Zhang #define regCP_ME_RAM_DATA_BASE_IDX 1 9694f33ac92fSHawking Zhang #define regCP_HYP_MEC1_UCODE_ADDR 0x581a 9695f33ac92fSHawking Zhang #define regCP_HYP_MEC1_UCODE_ADDR_BASE_IDX 1 9696f33ac92fSHawking Zhang #define regCP_MEC_ME1_UCODE_ADDR 0x581a 9697f33ac92fSHawking Zhang #define regCP_MEC_ME1_UCODE_ADDR_BASE_IDX 1 9698f33ac92fSHawking Zhang #define regCP_HYP_MEC1_UCODE_DATA 0x581b 9699f33ac92fSHawking Zhang #define regCP_HYP_MEC1_UCODE_DATA_BASE_IDX 1 9700f33ac92fSHawking Zhang #define regCP_MEC_ME1_UCODE_DATA 0x581b 9701f33ac92fSHawking Zhang #define regCP_MEC_ME1_UCODE_DATA_BASE_IDX 1 9702f33ac92fSHawking Zhang #define regCP_HYP_MEC2_UCODE_ADDR 0x581c 9703f33ac92fSHawking Zhang #define regCP_HYP_MEC2_UCODE_ADDR_BASE_IDX 1 9704f33ac92fSHawking Zhang #define regCP_MEC_ME2_UCODE_ADDR 0x581c 9705f33ac92fSHawking Zhang #define regCP_MEC_ME2_UCODE_ADDR_BASE_IDX 1 9706f33ac92fSHawking Zhang #define regCP_HYP_MEC2_UCODE_DATA 0x581d 9707f33ac92fSHawking Zhang #define regCP_HYP_MEC2_UCODE_DATA_BASE_IDX 1 9708f33ac92fSHawking Zhang #define regCP_MEC_ME2_UCODE_DATA 0x581d 9709f33ac92fSHawking Zhang #define regCP_MEC_ME2_UCODE_DATA_BASE_IDX 1 9710f33ac92fSHawking Zhang #define regCP_PFP_IC_BASE_LO 0x5840 9711f33ac92fSHawking Zhang #define regCP_PFP_IC_BASE_LO_BASE_IDX 1 9712f33ac92fSHawking Zhang #define regCP_PFP_IC_BASE_HI 0x5841 9713f33ac92fSHawking Zhang #define regCP_PFP_IC_BASE_HI_BASE_IDX 1 9714f33ac92fSHawking Zhang #define regCP_PFP_IC_BASE_CNTL 0x5842 9715f33ac92fSHawking Zhang #define regCP_PFP_IC_BASE_CNTL_BASE_IDX 1 9716f33ac92fSHawking Zhang #define regCP_PFP_IC_OP_CNTL 0x5843 9717f33ac92fSHawking Zhang #define regCP_PFP_IC_OP_CNTL_BASE_IDX 1 9718f33ac92fSHawking Zhang #define regCP_ME_IC_BASE_LO 0x5844 9719f33ac92fSHawking Zhang #define regCP_ME_IC_BASE_LO_BASE_IDX 1 9720f33ac92fSHawking Zhang #define regCP_ME_IC_BASE_HI 0x5845 9721f33ac92fSHawking Zhang #define regCP_ME_IC_BASE_HI_BASE_IDX 1 9722f33ac92fSHawking Zhang #define regCP_ME_IC_BASE_CNTL 0x5846 9723f33ac92fSHawking Zhang #define regCP_ME_IC_BASE_CNTL_BASE_IDX 1 9724f33ac92fSHawking Zhang #define regCP_ME_IC_OP_CNTL 0x5847 9725f33ac92fSHawking Zhang #define regCP_ME_IC_OP_CNTL_BASE_IDX 1 9726f33ac92fSHawking Zhang #define regCP_CPC_IC_BASE_LO 0x584c 9727f33ac92fSHawking Zhang #define regCP_CPC_IC_BASE_LO_BASE_IDX 1 9728f33ac92fSHawking Zhang #define regCP_CPC_IC_BASE_HI 0x584d 9729f33ac92fSHawking Zhang #define regCP_CPC_IC_BASE_HI_BASE_IDX 1 9730f33ac92fSHawking Zhang #define regCP_CPC_IC_BASE_CNTL 0x584e 9731f33ac92fSHawking Zhang #define regCP_CPC_IC_BASE_CNTL_BASE_IDX 1 9732f33ac92fSHawking Zhang #define regCP_MES_IC_BASE_LO 0x5850 9733f33ac92fSHawking Zhang #define regCP_MES_IC_BASE_LO_BASE_IDX 1 9734f33ac92fSHawking Zhang #define regCP_MES_MIBASE_LO 0x5850 9735f33ac92fSHawking Zhang #define regCP_MES_MIBASE_LO_BASE_IDX 1 9736f33ac92fSHawking Zhang #define regCP_MES_IC_BASE_HI 0x5851 9737f33ac92fSHawking Zhang #define regCP_MES_IC_BASE_HI_BASE_IDX 1 9738f33ac92fSHawking Zhang #define regCP_MES_MIBASE_HI 0x5851 9739f33ac92fSHawking Zhang #define regCP_MES_MIBASE_HI_BASE_IDX 1 9740f33ac92fSHawking Zhang #define regCP_MES_IC_BASE_CNTL 0x5852 9741f33ac92fSHawking Zhang #define regCP_MES_IC_BASE_CNTL_BASE_IDX 1 9742f33ac92fSHawking Zhang #define regCP_MES_DC_BASE_LO 0x5854 9743f33ac92fSHawking Zhang #define regCP_MES_DC_BASE_LO_BASE_IDX 1 9744f33ac92fSHawking Zhang #define regCP_MES_MDBASE_LO 0x5854 9745f33ac92fSHawking Zhang #define regCP_MES_MDBASE_LO_BASE_IDX 1 9746f33ac92fSHawking Zhang #define regCP_MES_DC_BASE_HI 0x5855 9747f33ac92fSHawking Zhang #define regCP_MES_DC_BASE_HI_BASE_IDX 1 9748f33ac92fSHawking Zhang #define regCP_MES_MDBASE_HI 0x5855 9749f33ac92fSHawking Zhang #define regCP_MES_MDBASE_HI_BASE_IDX 1 9750f33ac92fSHawking Zhang #define regCP_MES_MIBOUND_LO 0x585b 9751f33ac92fSHawking Zhang #define regCP_MES_MIBOUND_LO_BASE_IDX 1 9752f33ac92fSHawking Zhang #define regCP_MES_MIBOUND_HI 0x585c 9753f33ac92fSHawking Zhang #define regCP_MES_MIBOUND_HI_BASE_IDX 1 9754f33ac92fSHawking Zhang #define regCP_MES_MDBOUND_LO 0x585d 9755f33ac92fSHawking Zhang #define regCP_MES_MDBOUND_LO_BASE_IDX 1 9756f33ac92fSHawking Zhang #define regCP_MES_MDBOUND_HI 0x585e 9757f33ac92fSHawking Zhang #define regCP_MES_MDBOUND_HI_BASE_IDX 1 9758f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_BASE0_LO 0x5863 9759f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_BASE0_LO_BASE_IDX 1 9760f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_BASE1_LO 0x5864 9761f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_BASE1_LO_BASE_IDX 1 9762f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_BASE0_HI 0x5865 9763f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_BASE0_HI_BASE_IDX 1 9764f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_BASE1_HI 0x5866 9765f33ac92fSHawking Zhang #define regCP_GFX_RS64_DC_BASE1_HI_BASE_IDX 1 9766f33ac92fSHawking Zhang #define regCP_GFX_RS64_MIBOUND_LO 0x586c 9767f33ac92fSHawking Zhang #define regCP_GFX_RS64_MIBOUND_LO_BASE_IDX 1 9768f33ac92fSHawking Zhang #define regCP_GFX_RS64_MIBOUND_HI 0x586d 9769f33ac92fSHawking Zhang #define regCP_GFX_RS64_MIBOUND_HI_BASE_IDX 1 9770f33ac92fSHawking Zhang #define regCP_MEC_DC_BASE_LO 0x5870 9771f33ac92fSHawking Zhang #define regCP_MEC_DC_BASE_LO_BASE_IDX 1 9772f33ac92fSHawking Zhang #define regCP_MEC_MDBASE_LO 0x5870 9773f33ac92fSHawking Zhang #define regCP_MEC_MDBASE_LO_BASE_IDX 1 9774f33ac92fSHawking Zhang #define regCP_MEC_DC_BASE_HI 0x5871 9775f33ac92fSHawking Zhang #define regCP_MEC_DC_BASE_HI_BASE_IDX 1 9776f33ac92fSHawking Zhang #define regCP_MEC_MDBASE_HI 0x5871 9777f33ac92fSHawking Zhang #define regCP_MEC_MDBASE_HI_BASE_IDX 1 9778f33ac92fSHawking Zhang #define regCP_MEC_MIBOUND_LO 0x5872 9779f33ac92fSHawking Zhang #define regCP_MEC_MIBOUND_LO_BASE_IDX 1 9780f33ac92fSHawking Zhang #define regCP_MEC_MIBOUND_HI 0x5873 9781f33ac92fSHawking Zhang #define regCP_MEC_MIBOUND_HI_BASE_IDX 1 9782f33ac92fSHawking Zhang #define regCP_MEC_MDBOUND_LO 0x5874 9783f33ac92fSHawking Zhang #define regCP_MEC_MDBOUND_LO_BASE_IDX 1 9784f33ac92fSHawking Zhang #define regCP_MEC_MDBOUND_HI 0x5875 9785f33ac92fSHawking Zhang #define regCP_MEC_MDBOUND_HI_BASE_IDX 1 9786f33ac92fSHawking Zhang 9787f33ac92fSHawking Zhang 9788f33ac92fSHawking Zhang // addressBlock: gc_rlcdec 9789f33ac92fSHawking Zhang // base address: 0x3b000 9790f33ac92fSHawking Zhang #define regRLC_CNTL 0x4c00 9791f33ac92fSHawking Zhang #define regRLC_CNTL_BASE_IDX 1 9792f33ac92fSHawking Zhang #define regRLC_F32_UCODE_VERSION 0x4c03 9793f33ac92fSHawking Zhang #define regRLC_F32_UCODE_VERSION_BASE_IDX 1 9794f33ac92fSHawking Zhang #define regRLC_STAT 0x4c04 9795f33ac92fSHawking Zhang #define regRLC_STAT_BASE_IDX 1 9796f33ac92fSHawking Zhang #define regRLC_REFCLOCK_TIMESTAMP_LSB 0x4c0c 9797f33ac92fSHawking Zhang #define regRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX 1 9798f33ac92fSHawking Zhang #define regRLC_REFCLOCK_TIMESTAMP_MSB 0x4c0d 9799f33ac92fSHawking Zhang #define regRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX 1 9800f33ac92fSHawking Zhang #define regRLC_GPM_TIMER_INT_0 0x4c0e 9801f33ac92fSHawking Zhang #define regRLC_GPM_TIMER_INT_0_BASE_IDX 1 9802f33ac92fSHawking Zhang #define regRLC_GPM_TIMER_INT_1 0x4c0f 9803f33ac92fSHawking Zhang #define regRLC_GPM_TIMER_INT_1_BASE_IDX 1 9804f33ac92fSHawking Zhang #define regRLC_GPM_TIMER_INT_2 0x4c10 9805f33ac92fSHawking Zhang #define regRLC_GPM_TIMER_INT_2_BASE_IDX 1 9806f33ac92fSHawking Zhang #define regRLC_GPM_TIMER_INT_3 0x4c11 9807f33ac92fSHawking Zhang #define regRLC_GPM_TIMER_INT_3_BASE_IDX 1 9808f33ac92fSHawking Zhang #define regRLC_GPM_TIMER_INT_4 0x4c12 9809f33ac92fSHawking Zhang #define regRLC_GPM_TIMER_INT_4_BASE_IDX 1 9810f33ac92fSHawking Zhang #define regRLC_GPM_TIMER_CTRL 0x4c13 9811f33ac92fSHawking Zhang #define regRLC_GPM_TIMER_CTRL_BASE_IDX 1 9812f33ac92fSHawking Zhang #define regRLC_GPM_TIMER_STAT 0x4c14 9813f33ac92fSHawking Zhang #define regRLC_GPM_TIMER_STAT_BASE_IDX 1 9814f33ac92fSHawking Zhang #define regRLC_GPM_LEGACY_INT_STAT 0x4c16 9815f33ac92fSHawking Zhang #define regRLC_GPM_LEGACY_INT_STAT_BASE_IDX 1 9816f33ac92fSHawking Zhang #define regRLC_GPM_LEGACY_INT_CLEAR 0x4c17 9817f33ac92fSHawking Zhang #define regRLC_GPM_LEGACY_INT_CLEAR_BASE_IDX 1 9818f33ac92fSHawking Zhang #define regRLC_INT_STAT 0x4c18 9819f33ac92fSHawking Zhang #define regRLC_INT_STAT_BASE_IDX 1 9820f33ac92fSHawking Zhang #define regRLC_MGCG_CTRL 0x4c1a 9821f33ac92fSHawking Zhang #define regRLC_MGCG_CTRL_BASE_IDX 1 9822f33ac92fSHawking Zhang #define regRLC_JUMP_TABLE_RESTORE 0x4c1e 9823f33ac92fSHawking Zhang #define regRLC_JUMP_TABLE_RESTORE_BASE_IDX 1 9824f33ac92fSHawking Zhang #define regRLC_PG_DELAY_2 0x4c1f 9825f33ac92fSHawking Zhang #define regRLC_PG_DELAY_2_BASE_IDX 1 9826f33ac92fSHawking Zhang #define regRLC_GPU_CLOCK_COUNT_LSB 0x4c24 9827f33ac92fSHawking Zhang #define regRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1 9828f33ac92fSHawking Zhang #define regRLC_GPU_CLOCK_COUNT_MSB 0x4c25 9829f33ac92fSHawking Zhang #define regRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX 1 9830f33ac92fSHawking Zhang #define regRLC_CAPTURE_GPU_CLOCK_COUNT 0x4c26 9831f33ac92fSHawking Zhang #define regRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX 1 9832f33ac92fSHawking Zhang #define regRLC_UCODE_CNTL 0x4c27 9833f33ac92fSHawking Zhang #define regRLC_UCODE_CNTL_BASE_IDX 1 9834f33ac92fSHawking Zhang #define regRLC_GPM_THREAD_RESET 0x4c28 9835f33ac92fSHawking Zhang #define regRLC_GPM_THREAD_RESET_BASE_IDX 1 9836f33ac92fSHawking Zhang #define regRLC_GPM_CP_DMA_COMPLETE_T0 0x4c29 9837f33ac92fSHawking Zhang #define regRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX 1 9838f33ac92fSHawking Zhang #define regRLC_GPM_CP_DMA_COMPLETE_T1 0x4c2a 9839f33ac92fSHawking Zhang #define regRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX 1 9840f33ac92fSHawking Zhang #define regRLC_GPM_THREAD_INVALIDATE_CACHE 0x4c2b 9841f33ac92fSHawking Zhang #define regRLC_GPM_THREAD_INVALIDATE_CACHE_BASE_IDX 1 9842f33ac92fSHawking Zhang #define regRLC_CLK_COUNT_GFXCLK_LSB 0x4c30 9843f33ac92fSHawking Zhang #define regRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX 1 9844f33ac92fSHawking Zhang #define regRLC_CLK_COUNT_GFXCLK_MSB 0x4c31 9845f33ac92fSHawking Zhang #define regRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX 1 9846f33ac92fSHawking Zhang #define regRLC_CLK_COUNT_REFCLK_LSB 0x4c32 9847f33ac92fSHawking Zhang #define regRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX 1 9848f33ac92fSHawking Zhang #define regRLC_CLK_COUNT_REFCLK_MSB 0x4c33 9849f33ac92fSHawking Zhang #define regRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX 1 9850f33ac92fSHawking Zhang #define regRLC_CLK_COUNT_CTRL 0x4c34 9851f33ac92fSHawking Zhang #define regRLC_CLK_COUNT_CTRL_BASE_IDX 1 9852f33ac92fSHawking Zhang #define regRLC_CLK_COUNT_STAT 0x4c35 9853f33ac92fSHawking Zhang #define regRLC_CLK_COUNT_STAT_BASE_IDX 1 9854f33ac92fSHawking Zhang #define regRLC_RLCG_DOORBELL_CNTL 0x4c36 9855f33ac92fSHawking Zhang #define regRLC_RLCG_DOORBELL_CNTL_BASE_IDX 1 9856f33ac92fSHawking Zhang #define regRLC_RLCG_DOORBELL_STAT 0x4c37 9857f33ac92fSHawking Zhang #define regRLC_RLCG_DOORBELL_STAT_BASE_IDX 1 9858f33ac92fSHawking Zhang #define regRLC_RLCG_DOORBELL_0_DATA_LO 0x4c38 9859f33ac92fSHawking Zhang #define regRLC_RLCG_DOORBELL_0_DATA_LO_BASE_IDX 1 9860f33ac92fSHawking Zhang #define regRLC_RLCG_DOORBELL_0_DATA_HI 0x4c39 9861f33ac92fSHawking Zhang #define regRLC_RLCG_DOORBELL_0_DATA_HI_BASE_IDX 1 9862f33ac92fSHawking Zhang #define regRLC_RLCG_DOORBELL_1_DATA_LO 0x4c3a 9863f33ac92fSHawking Zhang #define regRLC_RLCG_DOORBELL_1_DATA_LO_BASE_IDX 1 9864f33ac92fSHawking Zhang #define regRLC_RLCG_DOORBELL_1_DATA_HI 0x4c3b 9865f33ac92fSHawking Zhang #define regRLC_RLCG_DOORBELL_1_DATA_HI_BASE_IDX 1 9866f33ac92fSHawking Zhang #define regRLC_RLCG_DOORBELL_2_DATA_LO 0x4c3c 9867f33ac92fSHawking Zhang #define regRLC_RLCG_DOORBELL_2_DATA_LO_BASE_IDX 1 9868f33ac92fSHawking Zhang #define regRLC_RLCG_DOORBELL_2_DATA_HI 0x4c3d 9869f33ac92fSHawking Zhang #define regRLC_RLCG_DOORBELL_2_DATA_HI_BASE_IDX 1 9870f33ac92fSHawking Zhang #define regRLC_RLCG_DOORBELL_3_DATA_LO 0x4c3e 9871f33ac92fSHawking Zhang #define regRLC_RLCG_DOORBELL_3_DATA_LO_BASE_IDX 1 9872f33ac92fSHawking Zhang #define regRLC_RLCG_DOORBELL_3_DATA_HI 0x4c3f 9873f33ac92fSHawking Zhang #define regRLC_RLCG_DOORBELL_3_DATA_HI_BASE_IDX 1 9874f33ac92fSHawking Zhang #define regRLC_GPU_CLOCK_32_RES_SEL 0x4c41 9875f33ac92fSHawking Zhang #define regRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX 1 9876f33ac92fSHawking Zhang #define regRLC_GPU_CLOCK_32 0x4c42 9877f33ac92fSHawking Zhang #define regRLC_GPU_CLOCK_32_BASE_IDX 1 9878f33ac92fSHawking Zhang #define regRLC_PG_CNTL 0x4c43 9879f33ac92fSHawking Zhang #define regRLC_PG_CNTL_BASE_IDX 1 9880f33ac92fSHawking Zhang #define regRLC_GPM_THREAD_PRIORITY 0x4c44 9881f33ac92fSHawking Zhang #define regRLC_GPM_THREAD_PRIORITY_BASE_IDX 1 9882f33ac92fSHawking Zhang #define regRLC_GPM_THREAD_ENABLE 0x4c45 9883f33ac92fSHawking Zhang #define regRLC_GPM_THREAD_ENABLE_BASE_IDX 1 9884f33ac92fSHawking Zhang #define regRLC_RLCG_DOORBELL_RANGE 0x4c47 9885f33ac92fSHawking Zhang #define regRLC_RLCG_DOORBELL_RANGE_BASE_IDX 1 9886f33ac92fSHawking Zhang #define regRLC_CGTT_MGCG_OVERRIDE 0x4c48 9887f33ac92fSHawking Zhang #define regRLC_CGTT_MGCG_OVERRIDE_BASE_IDX 1 9888f33ac92fSHawking Zhang #define regRLC_CGCG_CGLS_CTRL 0x4c49 9889f33ac92fSHawking Zhang #define regRLC_CGCG_CGLS_CTRL_BASE_IDX 1 9890f33ac92fSHawking Zhang #define regRLC_CGCG_RAMP_CTRL 0x4c4a 9891f33ac92fSHawking Zhang #define regRLC_CGCG_RAMP_CTRL_BASE_IDX 1 9892f33ac92fSHawking Zhang #define regRLC_DYN_PG_STATUS 0x4c4b 9893f33ac92fSHawking Zhang #define regRLC_DYN_PG_STATUS_BASE_IDX 1 9894f33ac92fSHawking Zhang #define regRLC_DYN_PG_REQUEST 0x4c4c 9895f33ac92fSHawking Zhang #define regRLC_DYN_PG_REQUEST_BASE_IDX 1 9896f33ac92fSHawking Zhang #define regRLC_PG_DELAY 0x4c4d 9897f33ac92fSHawking Zhang #define regRLC_PG_DELAY_BASE_IDX 1 9898f33ac92fSHawking Zhang #define regRLC_WGP_STATUS 0x4c4e 9899f33ac92fSHawking Zhang #define regRLC_WGP_STATUS_BASE_IDX 1 9900f33ac92fSHawking Zhang #define regRLC_PG_ALWAYS_ON_WGP_MASK 0x4c53 9901f33ac92fSHawking Zhang #define regRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX 1 9902f33ac92fSHawking Zhang #define regRLC_MAX_PG_WGP 0x4c54 9903f33ac92fSHawking Zhang #define regRLC_MAX_PG_WGP_BASE_IDX 1 9904f33ac92fSHawking Zhang #define regRLC_AUTO_PG_CTRL 0x4c55 9905f33ac92fSHawking Zhang #define regRLC_AUTO_PG_CTRL_BASE_IDX 1 9906f33ac92fSHawking Zhang #define regRLC_SERDES_RD_INDEX 0x4c59 9907f33ac92fSHawking Zhang #define regRLC_SERDES_RD_INDEX_BASE_IDX 1 9908f33ac92fSHawking Zhang #define regRLC_SERDES_RD_DATA_0 0x4c5a 9909f33ac92fSHawking Zhang #define regRLC_SERDES_RD_DATA_0_BASE_IDX 1 9910f33ac92fSHawking Zhang #define regRLC_SERDES_RD_DATA_1 0x4c5b 9911f33ac92fSHawking Zhang #define regRLC_SERDES_RD_DATA_1_BASE_IDX 1 9912f33ac92fSHawking Zhang #define regRLC_SERDES_RD_DATA_2 0x4c5c 9913f33ac92fSHawking Zhang #define regRLC_SERDES_RD_DATA_2_BASE_IDX 1 9914f33ac92fSHawking Zhang #define regRLC_SERDES_RD_DATA_3 0x4c5d 9915f33ac92fSHawking Zhang #define regRLC_SERDES_RD_DATA_3_BASE_IDX 1 9916f33ac92fSHawking Zhang #define regRLC_SERDES_MASK 0x4c5e 9917f33ac92fSHawking Zhang #define regRLC_SERDES_MASK_BASE_IDX 1 9918f33ac92fSHawking Zhang #define regRLC_SERDES_CTRL 0x4c5f 9919f33ac92fSHawking Zhang #define regRLC_SERDES_CTRL_BASE_IDX 1 9920f33ac92fSHawking Zhang #define regRLC_SERDES_DATA 0x4c60 9921f33ac92fSHawking Zhang #define regRLC_SERDES_DATA_BASE_IDX 1 9922f33ac92fSHawking Zhang #define regRLC_SERDES_BUSY 0x4c61 9923f33ac92fSHawking Zhang #define regRLC_SERDES_BUSY_BASE_IDX 1 9924f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_0 0x4c63 9925f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_0_BASE_IDX 1 9926f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_1 0x4c64 9927f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_1_BASE_IDX 1 9928f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_2 0x4c65 9929f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_2_BASE_IDX 1 9930f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_3 0x4c66 9931f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_3_BASE_IDX 1 9932f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_4 0x4c67 9933f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_4_BASE_IDX 1 9934f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_5 0x4c68 9935f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_5_BASE_IDX 1 9936f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_6 0x4c69 9937f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_6_BASE_IDX 1 9938f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_7 0x4c6a 9939f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_7_BASE_IDX 1 9940f33ac92fSHawking Zhang #define regRLC_STATIC_PG_STATUS 0x4c6e 9941f33ac92fSHawking Zhang #define regRLC_STATIC_PG_STATUS_BASE_IDX 1 9942f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_16 0x4c76 9943f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_16_BASE_IDX 1 9944f33ac92fSHawking Zhang #define regRLC_PG_DELAY_3 0x4c78 9945f33ac92fSHawking Zhang #define regRLC_PG_DELAY_3_BASE_IDX 1 9946f33ac92fSHawking Zhang #define regRLC_GPR_REG1 0x4c79 9947f33ac92fSHawking Zhang #define regRLC_GPR_REG1_BASE_IDX 1 9948f33ac92fSHawking Zhang #define regRLC_GPR_REG2 0x4c7a 9949f33ac92fSHawking Zhang #define regRLC_GPR_REG2_BASE_IDX 1 9950f33ac92fSHawking Zhang #define regRLC_GPM_INT_DISABLE_TH0 0x4c7c 9951f33ac92fSHawking Zhang #define regRLC_GPM_INT_DISABLE_TH0_BASE_IDX 1 9952f33ac92fSHawking Zhang #define regRLC_GPM_LEGACY_INT_DISABLE 0x4c7d 9953f33ac92fSHawking Zhang #define regRLC_GPM_LEGACY_INT_DISABLE_BASE_IDX 1 9954f33ac92fSHawking Zhang #define regRLC_GPM_INT_FORCE_TH0 0x4c7e 9955f33ac92fSHawking Zhang #define regRLC_GPM_INT_FORCE_TH0_BASE_IDX 1 9956f33ac92fSHawking Zhang #define regRLC_SRM_CNTL 0x4c80 9957f33ac92fSHawking Zhang #define regRLC_SRM_CNTL_BASE_IDX 1 9958f33ac92fSHawking Zhang #define regRLC_SRM_GPM_COMMAND_STATUS 0x4c88 9959f33ac92fSHawking Zhang #define regRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX 1 9960f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_ADDR_0 0x4c8b 9961f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX 1 9962f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_ADDR_1 0x4c8c 9963f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX 1 9964f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_ADDR_2 0x4c8d 9965f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX 1 9966f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_ADDR_3 0x4c8e 9967f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX 1 9968f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_ADDR_4 0x4c8f 9969f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX 1 9970f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_ADDR_5 0x4c90 9971f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX 1 9972f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_ADDR_6 0x4c91 9973f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX 1 9974f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_ADDR_7 0x4c92 9975f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX 1 9976f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_DATA_0 0x4c93 9977f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX 1 9978f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_DATA_1 0x4c94 9979f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX 1 9980f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_DATA_2 0x4c95 9981f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX 1 9982f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_DATA_3 0x4c96 9983f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX 1 9984f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_DATA_4 0x4c97 9985f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX 1 9986f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_DATA_5 0x4c98 9987f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX 1 9988f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_DATA_6 0x4c99 9989f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX 1 9990f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_DATA_7 0x4c9a 9991f33ac92fSHawking Zhang #define regRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX 1 9992f33ac92fSHawking Zhang #define regRLC_SRM_STAT 0x4c9b 9993f33ac92fSHawking Zhang #define regRLC_SRM_STAT_BASE_IDX 1 9994f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_8 0x4cad 9995f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_8_BASE_IDX 1 9996f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_9 0x4cae 9997f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_9_BASE_IDX 1 9998f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_10 0x4caf 9999f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_10_BASE_IDX 1 10000f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_11 0x4cb0 10001f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_11_BASE_IDX 1 10002f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_12 0x4cb1 10003f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_12_BASE_IDX 1 10004f33ac92fSHawking Zhang #define regRLC_GPM_UTCL1_CNTL_0 0x4cb2 10005f33ac92fSHawking Zhang #define regRLC_GPM_UTCL1_CNTL_0_BASE_IDX 1 10006f33ac92fSHawking Zhang #define regRLC_GPM_UTCL1_CNTL_1 0x4cb3 10007f33ac92fSHawking Zhang #define regRLC_GPM_UTCL1_CNTL_1_BASE_IDX 1 10008f33ac92fSHawking Zhang #define regRLC_GPM_UTCL1_CNTL_2 0x4cb4 10009f33ac92fSHawking Zhang #define regRLC_GPM_UTCL1_CNTL_2_BASE_IDX 1 10010f33ac92fSHawking Zhang #define regRLC_SPM_UTCL1_CNTL 0x4cb5 10011f33ac92fSHawking Zhang #define regRLC_SPM_UTCL1_CNTL_BASE_IDX 1 10012f33ac92fSHawking Zhang #define regRLC_UTCL1_STATUS_2 0x4cb6 10013f33ac92fSHawking Zhang #define regRLC_UTCL1_STATUS_2_BASE_IDX 1 10014f33ac92fSHawking Zhang #define regRLC_SPM_UTCL1_ERROR_1 0x4cbc 10015f33ac92fSHawking Zhang #define regRLC_SPM_UTCL1_ERROR_1_BASE_IDX 1 10016f33ac92fSHawking Zhang #define regRLC_SPM_UTCL1_ERROR_2 0x4cbd 10017f33ac92fSHawking Zhang #define regRLC_SPM_UTCL1_ERROR_2_BASE_IDX 1 10018f33ac92fSHawking Zhang #define regRLC_GPM_UTCL1_TH0_ERROR_1 0x4cbe 10019f33ac92fSHawking Zhang #define regRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX 1 10020f33ac92fSHawking Zhang #define regRLC_GPM_UTCL1_TH0_ERROR_2 0x4cc0 10021f33ac92fSHawking Zhang #define regRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX 1 10022f33ac92fSHawking Zhang #define regRLC_GPM_UTCL1_TH1_ERROR_1 0x4cc1 10023f33ac92fSHawking Zhang #define regRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX 1 10024f33ac92fSHawking Zhang #define regRLC_GPM_UTCL1_TH1_ERROR_2 0x4cc2 10025f33ac92fSHawking Zhang #define regRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX 1 10026f33ac92fSHawking Zhang #define regRLC_GPM_UTCL1_TH2_ERROR_1 0x4cc3 10027f33ac92fSHawking Zhang #define regRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX 1 10028f33ac92fSHawking Zhang #define regRLC_GPM_UTCL1_TH2_ERROR_2 0x4cc4 10029f33ac92fSHawking Zhang #define regRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX 1 10030f33ac92fSHawking Zhang #define regRLC_CGCG_CGLS_CTRL_3D 0x4cc5 10031f33ac92fSHawking Zhang #define regRLC_CGCG_CGLS_CTRL_3D_BASE_IDX 1 10032f33ac92fSHawking Zhang #define regRLC_CGCG_RAMP_CTRL_3D 0x4cc6 10033f33ac92fSHawking Zhang #define regRLC_CGCG_RAMP_CTRL_3D_BASE_IDX 1 10034f33ac92fSHawking Zhang #define regRLC_SEMAPHORE_0 0x4cc7 10035f33ac92fSHawking Zhang #define regRLC_SEMAPHORE_0_BASE_IDX 1 10036f33ac92fSHawking Zhang #define regRLC_SEMAPHORE_1 0x4cc8 10037f33ac92fSHawking Zhang #define regRLC_SEMAPHORE_1_BASE_IDX 1 10038f33ac92fSHawking Zhang #define regRLC_SEMAPHORE_2 0x4cc9 10039f33ac92fSHawking Zhang #define regRLC_SEMAPHORE_2_BASE_IDX 1 10040f33ac92fSHawking Zhang #define regRLC_SEMAPHORE_3 0x4cca 10041f33ac92fSHawking Zhang #define regRLC_SEMAPHORE_3_BASE_IDX 1 10042f33ac92fSHawking Zhang #define regRLC_PACE_INT_STAT 0x4ccc 10043f33ac92fSHawking Zhang #define regRLC_PACE_INT_STAT_BASE_IDX 1 10044f33ac92fSHawking Zhang #define regRLC_UTCL1_STATUS 0x4cd4 10045f33ac92fSHawking Zhang #define regRLC_UTCL1_STATUS_BASE_IDX 1 10046f33ac92fSHawking Zhang #define regRLC_R2I_CNTL_0 0x4cd5 10047f33ac92fSHawking Zhang #define regRLC_R2I_CNTL_0_BASE_IDX 1 10048f33ac92fSHawking Zhang #define regRLC_R2I_CNTL_1 0x4cd6 10049f33ac92fSHawking Zhang #define regRLC_R2I_CNTL_1_BASE_IDX 1 10050f33ac92fSHawking Zhang #define regRLC_R2I_CNTL_2 0x4cd7 10051f33ac92fSHawking Zhang #define regRLC_R2I_CNTL_2_BASE_IDX 1 10052f33ac92fSHawking Zhang #define regRLC_R2I_CNTL_3 0x4cd8 10053f33ac92fSHawking Zhang #define regRLC_R2I_CNTL_3_BASE_IDX 1 10054f33ac92fSHawking Zhang #define regRLC_GPM_INT_STAT_TH0 0x4cdc 10055f33ac92fSHawking Zhang #define regRLC_GPM_INT_STAT_TH0_BASE_IDX 1 10056f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_13 0x4cdd 10057f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_13_BASE_IDX 1 10058f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_14 0x4cde 10059f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_14_BASE_IDX 1 10060f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_15 0x4cdf 10061f33ac92fSHawking Zhang #define regRLC_GPM_GENERAL_15_BASE_IDX 1 10062f33ac92fSHawking Zhang #define regRLC_CAPTURE_GPU_CLOCK_COUNT_1 0x4cea 10063f33ac92fSHawking Zhang #define regRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX 1 10064f33ac92fSHawking Zhang #define regRLC_GPU_CLOCK_COUNT_LSB_2 0x4ceb 10065f33ac92fSHawking Zhang #define regRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX 1 10066f33ac92fSHawking Zhang #define regRLC_GPU_CLOCK_COUNT_MSB_2 0x4cec 10067f33ac92fSHawking Zhang #define regRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX 1 10068f33ac92fSHawking Zhang #define regRLC_PACE_INT_DISABLE 0x4ced 10069f33ac92fSHawking Zhang #define regRLC_PACE_INT_DISABLE_BASE_IDX 1 10070f33ac92fSHawking Zhang #define regRLC_CAPTURE_GPU_CLOCK_COUNT_2 0x4cef 10071f33ac92fSHawking Zhang #define regRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX 1 10072f33ac92fSHawking Zhang #define regRLC_RLCV_DOORBELL_RANGE 0x4cf0 10073f33ac92fSHawking Zhang #define regRLC_RLCV_DOORBELL_RANGE_BASE_IDX 1 10074f33ac92fSHawking Zhang #define regRLC_RLCV_DOORBELL_CNTL 0x4cf1 10075f33ac92fSHawking Zhang #define regRLC_RLCV_DOORBELL_CNTL_BASE_IDX 1 10076f33ac92fSHawking Zhang #define regRLC_RLCV_DOORBELL_STAT 0x4cf2 10077f33ac92fSHawking Zhang #define regRLC_RLCV_DOORBELL_STAT_BASE_IDX 1 10078f33ac92fSHawking Zhang #define regRLC_RLCV_DOORBELL_0_DATA_LO 0x4cf3 10079f33ac92fSHawking Zhang #define regRLC_RLCV_DOORBELL_0_DATA_LO_BASE_IDX 1 10080f33ac92fSHawking Zhang #define regRLC_RLCV_DOORBELL_0_DATA_HI 0x4cf4 10081f33ac92fSHawking Zhang #define regRLC_RLCV_DOORBELL_0_DATA_HI_BASE_IDX 1 10082f33ac92fSHawking Zhang #define regRLC_RLCV_DOORBELL_1_DATA_LO 0x4cf5 10083f33ac92fSHawking Zhang #define regRLC_RLCV_DOORBELL_1_DATA_LO_BASE_IDX 1 10084f33ac92fSHawking Zhang #define regRLC_RLCV_DOORBELL_1_DATA_HI 0x4cf6 10085f33ac92fSHawking Zhang #define regRLC_RLCV_DOORBELL_1_DATA_HI_BASE_IDX 1 10086f33ac92fSHawking Zhang #define regRLC_RLCV_DOORBELL_2_DATA_LO 0x4cf7 10087f33ac92fSHawking Zhang #define regRLC_RLCV_DOORBELL_2_DATA_LO_BASE_IDX 1 10088f33ac92fSHawking Zhang #define regRLC_RLCV_DOORBELL_2_DATA_HI 0x4cf8 10089f33ac92fSHawking Zhang #define regRLC_RLCV_DOORBELL_2_DATA_HI_BASE_IDX 1 10090f33ac92fSHawking Zhang #define regRLC_RLCV_DOORBELL_3_DATA_LO 0x4cf9 10091f33ac92fSHawking Zhang #define regRLC_RLCV_DOORBELL_3_DATA_LO_BASE_IDX 1 10092f33ac92fSHawking Zhang #define regRLC_RLCV_DOORBELL_3_DATA_HI 0x4cfa 10093f33ac92fSHawking Zhang #define regRLC_RLCV_DOORBELL_3_DATA_HI_BASE_IDX 1 10094f33ac92fSHawking Zhang #define regRLC_GPU_CLOCK_COUNT_LSB_1 0x4cfb 10095f33ac92fSHawking Zhang #define regRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX 1 10096f33ac92fSHawking Zhang #define regRLC_GPU_CLOCK_COUNT_MSB_1 0x4cfc 10097f33ac92fSHawking Zhang #define regRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX 1 10098f33ac92fSHawking Zhang #define regRLC_RLCV_SPARE_INT 0x4d00 10099f33ac92fSHawking Zhang #define regRLC_RLCV_SPARE_INT_BASE_IDX 1 10100f33ac92fSHawking Zhang #define regRLC_PACE_TIMER_INT_0 0x4d04 10101f33ac92fSHawking Zhang #define regRLC_PACE_TIMER_INT_0_BASE_IDX 1 10102f33ac92fSHawking Zhang #define regRLC_PACE_TIMER_INT_1 0x4d05 10103f33ac92fSHawking Zhang #define regRLC_PACE_TIMER_INT_1_BASE_IDX 1 10104f33ac92fSHawking Zhang #define regRLC_PACE_TIMER_CTRL 0x4d06 10105f33ac92fSHawking Zhang #define regRLC_PACE_TIMER_CTRL_BASE_IDX 1 10106f33ac92fSHawking Zhang #define regRLC_SMU_CLK_REQ 0x4d08 10107f33ac92fSHawking Zhang #define regRLC_SMU_CLK_REQ_BASE_IDX 1 10108f33ac92fSHawking Zhang #define regRLC_CP_STAT_INVAL_STAT 0x4d09 10109f33ac92fSHawking Zhang #define regRLC_CP_STAT_INVAL_STAT_BASE_IDX 1 10110f33ac92fSHawking Zhang #define regRLC_CP_STAT_INVAL_CTRL 0x4d0a 10111f33ac92fSHawking Zhang #define regRLC_CP_STAT_INVAL_CTRL_BASE_IDX 1 10112f33ac92fSHawking Zhang #define regRLC_SPARE 0x4d0b 10113f33ac92fSHawking Zhang #define regRLC_SPARE_BASE_IDX 1 10114f33ac92fSHawking Zhang #define regRLC_SPP_CTRL 0x4d0c 10115f33ac92fSHawking Zhang #define regRLC_SPP_CTRL_BASE_IDX 1 10116f33ac92fSHawking Zhang #define regRLC_SPP_SHADER_PROFILE_EN 0x4d0d 10117f33ac92fSHawking Zhang #define regRLC_SPP_SHADER_PROFILE_EN_BASE_IDX 1 10118f33ac92fSHawking Zhang #define regRLC_SPP_SSF_CAPTURE_EN 0x4d0e 10119f33ac92fSHawking Zhang #define regRLC_SPP_SSF_CAPTURE_EN_BASE_IDX 1 10120f33ac92fSHawking Zhang #define regRLC_SPP_SSF_THRESHOLD_0 0x4d0f 10121f33ac92fSHawking Zhang #define regRLC_SPP_SSF_THRESHOLD_0_BASE_IDX 1 10122f33ac92fSHawking Zhang #define regRLC_SPP_SSF_THRESHOLD_1 0x4d10 10123f33ac92fSHawking Zhang #define regRLC_SPP_SSF_THRESHOLD_1_BASE_IDX 1 10124f33ac92fSHawking Zhang #define regRLC_SPP_SSF_THRESHOLD_2 0x4d11 10125f33ac92fSHawking Zhang #define regRLC_SPP_SSF_THRESHOLD_2_BASE_IDX 1 10126f33ac92fSHawking Zhang #define regRLC_SPP_INFLIGHT_RD_ADDR 0x4d12 10127f33ac92fSHawking Zhang #define regRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX 1 10128f33ac92fSHawking Zhang #define regRLC_SPP_INFLIGHT_RD_DATA 0x4d13 10129f33ac92fSHawking Zhang #define regRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX 1 10130f33ac92fSHawking Zhang #define regRLC_SPP_PROF_INFO_1 0x4d18 10131f33ac92fSHawking Zhang #define regRLC_SPP_PROF_INFO_1_BASE_IDX 1 10132f33ac92fSHawking Zhang #define regRLC_SPP_PROF_INFO_2 0x4d19 10133f33ac92fSHawking Zhang #define regRLC_SPP_PROF_INFO_2_BASE_IDX 1 10134f33ac92fSHawking Zhang #define regRLC_SPP_GLOBAL_SH_ID 0x4d1a 10135f33ac92fSHawking Zhang #define regRLC_SPP_GLOBAL_SH_ID_BASE_IDX 1 10136f33ac92fSHawking Zhang #define regRLC_SPP_GLOBAL_SH_ID_VALID 0x4d1b 10137f33ac92fSHawking Zhang #define regRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX 1 10138f33ac92fSHawking Zhang #define regRLC_SPP_STATUS 0x4d1c 10139f33ac92fSHawking Zhang #define regRLC_SPP_STATUS_BASE_IDX 1 10140f33ac92fSHawking Zhang #define regRLC_SPP_PVT_STAT_0 0x4d1d 10141f33ac92fSHawking Zhang #define regRLC_SPP_PVT_STAT_0_BASE_IDX 1 10142f33ac92fSHawking Zhang #define regRLC_SPP_PVT_STAT_1 0x4d1e 10143f33ac92fSHawking Zhang #define regRLC_SPP_PVT_STAT_1_BASE_IDX 1 10144f33ac92fSHawking Zhang #define regRLC_SPP_PVT_STAT_2 0x4d1f 10145f33ac92fSHawking Zhang #define regRLC_SPP_PVT_STAT_2_BASE_IDX 1 10146f33ac92fSHawking Zhang #define regRLC_SPP_PVT_STAT_3 0x4d20 10147f33ac92fSHawking Zhang #define regRLC_SPP_PVT_STAT_3_BASE_IDX 1 10148f33ac92fSHawking Zhang #define regRLC_SPP_PVT_LEVEL_MAX 0x4d21 10149f33ac92fSHawking Zhang #define regRLC_SPP_PVT_LEVEL_MAX_BASE_IDX 1 10150f33ac92fSHawking Zhang #define regRLC_SPP_STALL_STATE_UPDATE 0x4d22 10151f33ac92fSHawking Zhang #define regRLC_SPP_STALL_STATE_UPDATE_BASE_IDX 1 10152f33ac92fSHawking Zhang #define regRLC_SPP_PBB_INFO 0x4d23 10153f33ac92fSHawking Zhang #define regRLC_SPP_PBB_INFO_BASE_IDX 1 10154f33ac92fSHawking Zhang #define regRLC_SPP_RESET 0x4d24 10155f33ac92fSHawking Zhang #define regRLC_SPP_RESET_BASE_IDX 1 10156f33ac92fSHawking Zhang #define regRLC_RLCP_DOORBELL_RANGE 0x4d26 10157f33ac92fSHawking Zhang #define regRLC_RLCP_DOORBELL_RANGE_BASE_IDX 1 10158f33ac92fSHawking Zhang #define regRLC_RLCP_DOORBELL_CNTL 0x4d27 10159f33ac92fSHawking Zhang #define regRLC_RLCP_DOORBELL_CNTL_BASE_IDX 1 10160f33ac92fSHawking Zhang #define regRLC_RLCP_DOORBELL_STAT 0x4d28 10161f33ac92fSHawking Zhang #define regRLC_RLCP_DOORBELL_STAT_BASE_IDX 1 10162f33ac92fSHawking Zhang #define regRLC_RLCP_DOORBELL_0_DATA_LO 0x4d29 10163f33ac92fSHawking Zhang #define regRLC_RLCP_DOORBELL_0_DATA_LO_BASE_IDX 1 10164f33ac92fSHawking Zhang #define regRLC_RLCP_DOORBELL_0_DATA_HI 0x4d2a 10165f33ac92fSHawking Zhang #define regRLC_RLCP_DOORBELL_0_DATA_HI_BASE_IDX 1 10166f33ac92fSHawking Zhang #define regRLC_RLCP_DOORBELL_1_DATA_LO 0x4d2b 10167f33ac92fSHawking Zhang #define regRLC_RLCP_DOORBELL_1_DATA_LO_BASE_IDX 1 10168f33ac92fSHawking Zhang #define regRLC_RLCP_DOORBELL_1_DATA_HI 0x4d2c 10169f33ac92fSHawking Zhang #define regRLC_RLCP_DOORBELL_1_DATA_HI_BASE_IDX 1 10170f33ac92fSHawking Zhang #define regRLC_RLCP_DOORBELL_2_DATA_LO 0x4d2d 10171f33ac92fSHawking Zhang #define regRLC_RLCP_DOORBELL_2_DATA_LO_BASE_IDX 1 10172f33ac92fSHawking Zhang #define regRLC_RLCP_DOORBELL_2_DATA_HI 0x4d2e 10173f33ac92fSHawking Zhang #define regRLC_RLCP_DOORBELL_2_DATA_HI_BASE_IDX 1 10174f33ac92fSHawking Zhang #define regRLC_RLCP_DOORBELL_3_DATA_LO 0x4d2f 10175f33ac92fSHawking Zhang #define regRLC_RLCP_DOORBELL_3_DATA_LO_BASE_IDX 1 10176f33ac92fSHawking Zhang #define regRLC_RLCP_DOORBELL_3_DATA_HI 0x4d30 10177f33ac92fSHawking Zhang #define regRLC_RLCP_DOORBELL_3_DATA_HI_BASE_IDX 1 10178f33ac92fSHawking Zhang #define regRLC_CAC_MASK_CNTL 0x4d45 10179f33ac92fSHawking Zhang #define regRLC_CAC_MASK_CNTL_BASE_IDX 1 10180f33ac92fSHawking Zhang #define regRLC_POWER_RESIDENCY_CNTR_CTRL 0x4d48 10181f33ac92fSHawking Zhang #define regRLC_POWER_RESIDENCY_CNTR_CTRL_BASE_IDX 1 10182f33ac92fSHawking Zhang #define regRLC_CLK_RESIDENCY_CNTR_CTRL 0x4d49 10183f33ac92fSHawking Zhang #define regRLC_CLK_RESIDENCY_CNTR_CTRL_BASE_IDX 1 10184f33ac92fSHawking Zhang #define regRLC_DS_RESIDENCY_CNTR_CTRL 0x4d4a 10185f33ac92fSHawking Zhang #define regRLC_DS_RESIDENCY_CNTR_CTRL_BASE_IDX 1 10186f33ac92fSHawking Zhang #define regRLC_ULV_RESIDENCY_CNTR_CTRL 0x4d4b 10187f33ac92fSHawking Zhang #define regRLC_ULV_RESIDENCY_CNTR_CTRL_BASE_IDX 1 10188f33ac92fSHawking Zhang #define regRLC_PCC_RESIDENCY_CNTR_CTRL 0x4d4c 10189f33ac92fSHawking Zhang #define regRLC_PCC_RESIDENCY_CNTR_CTRL_BASE_IDX 1 10190f33ac92fSHawking Zhang #define regRLC_GENERAL_RESIDENCY_CNTR_CTRL 0x4d4d 10191f33ac92fSHawking Zhang #define regRLC_GENERAL_RESIDENCY_CNTR_CTRL_BASE_IDX 1 10192f33ac92fSHawking Zhang #define regRLC_POWER_RESIDENCY_EVENT_CNTR 0x4d50 10193f33ac92fSHawking Zhang #define regRLC_POWER_RESIDENCY_EVENT_CNTR_BASE_IDX 1 10194f33ac92fSHawking Zhang #define regRLC_CLK_RESIDENCY_EVENT_CNTR 0x4d51 10195f33ac92fSHawking Zhang #define regRLC_CLK_RESIDENCY_EVENT_CNTR_BASE_IDX 1 10196f33ac92fSHawking Zhang #define regRLC_DS_RESIDENCY_EVENT_CNTR 0x4d52 10197f33ac92fSHawking Zhang #define regRLC_DS_RESIDENCY_EVENT_CNTR_BASE_IDX 1 10198f33ac92fSHawking Zhang #define regRLC_ULV_RESIDENCY_EVENT_CNTR 0x4d53 10199f33ac92fSHawking Zhang #define regRLC_ULV_RESIDENCY_EVENT_CNTR_BASE_IDX 1 10200f33ac92fSHawking Zhang #define regRLC_PCC_RESIDENCY_EVENT_CNTR 0x4d54 10201f33ac92fSHawking Zhang #define regRLC_PCC_RESIDENCY_EVENT_CNTR_BASE_IDX 1 10202f33ac92fSHawking Zhang #define regRLC_GENERAL_RESIDENCY_EVENT_CNTR 0x4d55 10203f33ac92fSHawking Zhang #define regRLC_GENERAL_RESIDENCY_EVENT_CNTR_BASE_IDX 1 10204f33ac92fSHawking Zhang #define regRLC_POWER_RESIDENCY_REF_CNTR 0x4d58 10205f33ac92fSHawking Zhang #define regRLC_POWER_RESIDENCY_REF_CNTR_BASE_IDX 1 10206f33ac92fSHawking Zhang #define regRLC_CLK_RESIDENCY_REF_CNTR 0x4d59 10207f33ac92fSHawking Zhang #define regRLC_CLK_RESIDENCY_REF_CNTR_BASE_IDX 1 10208f33ac92fSHawking Zhang #define regRLC_DS_RESIDENCY_REF_CNTR 0x4d5a 10209f33ac92fSHawking Zhang #define regRLC_DS_RESIDENCY_REF_CNTR_BASE_IDX 1 10210f33ac92fSHawking Zhang #define regRLC_ULV_RESIDENCY_REF_CNTR 0x4d5b 10211f33ac92fSHawking Zhang #define regRLC_ULV_RESIDENCY_REF_CNTR_BASE_IDX 1 10212f33ac92fSHawking Zhang #define regRLC_PCC_RESIDENCY_REF_CNTR 0x4d5c 10213f33ac92fSHawking Zhang #define regRLC_PCC_RESIDENCY_REF_CNTR_BASE_IDX 1 10214f33ac92fSHawking Zhang #define regRLC_GENERAL_RESIDENCY_REF_CNTR 0x4d5d 10215f33ac92fSHawking Zhang #define regRLC_GENERAL_RESIDENCY_REF_CNTR_BASE_IDX 1 10216f33ac92fSHawking Zhang #define regRLC_GFX_IH_CLIENT_CTRL 0x4d5e 10217f33ac92fSHawking Zhang #define regRLC_GFX_IH_CLIENT_CTRL_BASE_IDX 1 10218f33ac92fSHawking Zhang #define regRLC_GFX_IH_ARBITER_STAT 0x4d5f 10219f33ac92fSHawking Zhang #define regRLC_GFX_IH_ARBITER_STAT_BASE_IDX 1 10220f33ac92fSHawking Zhang #define regRLC_GFX_IH_CLIENT_SE_STAT_L 0x4d60 10221f33ac92fSHawking Zhang #define regRLC_GFX_IH_CLIENT_SE_STAT_L_BASE_IDX 1 10222f33ac92fSHawking Zhang #define regRLC_GFX_IH_CLIENT_SE_STAT_H 0x4d61 10223f33ac92fSHawking Zhang #define regRLC_GFX_IH_CLIENT_SE_STAT_H_BASE_IDX 1 10224f33ac92fSHawking Zhang #define regRLC_GFX_IH_CLIENT_SDMA_STAT 0x4d62 10225f33ac92fSHawking Zhang #define regRLC_GFX_IH_CLIENT_SDMA_STAT_BASE_IDX 1 10226f33ac92fSHawking Zhang #define regRLC_GFX_IH_CLIENT_OTHER_STAT 0x4d63 10227f33ac92fSHawking Zhang #define regRLC_GFX_IH_CLIENT_OTHER_STAT_BASE_IDX 1 10228f33ac92fSHawking Zhang #define regRLC_SPM_GLOBAL_DELAY_IND_ADDR 0x4d64 10229f33ac92fSHawking Zhang #define regRLC_SPM_GLOBAL_DELAY_IND_ADDR_BASE_IDX 1 10230f33ac92fSHawking Zhang #define regRLC_SPM_GLOBAL_DELAY_IND_DATA 0x4d65 10231f33ac92fSHawking Zhang #define regRLC_SPM_GLOBAL_DELAY_IND_DATA_BASE_IDX 1 10232f33ac92fSHawking Zhang #define regRLC_SPM_SE_DELAY_IND_ADDR 0x4d66 10233f33ac92fSHawking Zhang #define regRLC_SPM_SE_DELAY_IND_ADDR_BASE_IDX 1 10234f33ac92fSHawking Zhang #define regRLC_SPM_SE_DELAY_IND_DATA 0x4d67 10235f33ac92fSHawking Zhang #define regRLC_SPM_SE_DELAY_IND_DATA_BASE_IDX 1 10236f33ac92fSHawking Zhang #define regRLC_LX6_CNTL 0x4d80 10237f33ac92fSHawking Zhang #define regRLC_LX6_CNTL_BASE_IDX 1 10238f33ac92fSHawking Zhang #define regRLC_XT_CORE_STATUS 0x4dd4 10239f33ac92fSHawking Zhang #define regRLC_XT_CORE_STATUS_BASE_IDX 1 10240f33ac92fSHawking Zhang #define regRLC_XT_CORE_INTERRUPT 0x4dd5 10241f33ac92fSHawking Zhang #define regRLC_XT_CORE_INTERRUPT_BASE_IDX 1 10242f33ac92fSHawking Zhang #define regRLC_XT_CORE_FAULT_INFO 0x4dd6 10243f33ac92fSHawking Zhang #define regRLC_XT_CORE_FAULT_INFO_BASE_IDX 1 10244f33ac92fSHawking Zhang #define regRLC_XT_CORE_ALT_RESET_VEC 0x4dd7 10245f33ac92fSHawking Zhang #define regRLC_XT_CORE_ALT_RESET_VEC_BASE_IDX 1 10246f33ac92fSHawking Zhang #define regRLC_XT_CORE_RESERVED 0x4dd8 10247f33ac92fSHawking Zhang #define regRLC_XT_CORE_RESERVED_BASE_IDX 1 10248f33ac92fSHawking Zhang #define regRLC_XT_INT_VEC_FORCE 0x4dd9 10249f33ac92fSHawking Zhang #define regRLC_XT_INT_VEC_FORCE_BASE_IDX 1 10250f33ac92fSHawking Zhang #define regRLC_XT_INT_VEC_CLEAR 0x4dda 10251f33ac92fSHawking Zhang #define regRLC_XT_INT_VEC_CLEAR_BASE_IDX 1 10252f33ac92fSHawking Zhang #define regRLC_XT_INT_VEC_MUX_SEL 0x4ddb 10253f33ac92fSHawking Zhang #define regRLC_XT_INT_VEC_MUX_SEL_BASE_IDX 1 10254f33ac92fSHawking Zhang #define regRLC_XT_INT_VEC_MUX_INT_SEL 0x4ddc 10255f33ac92fSHawking Zhang #define regRLC_XT_INT_VEC_MUX_INT_SEL_BASE_IDX 1 10256f33ac92fSHawking Zhang #define regRLC_GPU_CLOCK_COUNT_SPM_LSB 0x4de4 10257f33ac92fSHawking Zhang #define regRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX 1 10258f33ac92fSHawking Zhang #define regRLC_GPU_CLOCK_COUNT_SPM_MSB 0x4de5 10259f33ac92fSHawking Zhang #define regRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX 1 10260f33ac92fSHawking Zhang #define regRLC_SPM_THREAD_TRACE_CTRL 0x4de6 10261f33ac92fSHawking Zhang #define regRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX 1 10262f33ac92fSHawking Zhang #define regRLC_SPP_CAM_ADDR 0x4de8 10263f33ac92fSHawking Zhang #define regRLC_SPP_CAM_ADDR_BASE_IDX 1 10264f33ac92fSHawking Zhang #define regRLC_SPP_CAM_DATA 0x4de9 10265f33ac92fSHawking Zhang #define regRLC_SPP_CAM_DATA_BASE_IDX 1 10266f33ac92fSHawking Zhang #define regRLC_SPP_CAM_EXT_ADDR 0x4dea 10267f33ac92fSHawking Zhang #define regRLC_SPP_CAM_EXT_ADDR_BASE_IDX 1 10268f33ac92fSHawking Zhang #define regRLC_SPP_CAM_EXT_DATA 0x4deb 10269f33ac92fSHawking Zhang #define regRLC_SPP_CAM_EXT_DATA_BASE_IDX 1 10270f33ac92fSHawking Zhang #define regRLC_XT_DOORBELL_RANGE 0x4df5 10271f33ac92fSHawking Zhang #define regRLC_XT_DOORBELL_RANGE_BASE_IDX 1 10272f33ac92fSHawking Zhang #define regRLC_XT_DOORBELL_CNTL 0x4df6 10273f33ac92fSHawking Zhang #define regRLC_XT_DOORBELL_CNTL_BASE_IDX 1 10274f33ac92fSHawking Zhang #define regRLC_XT_DOORBELL_STAT 0x4df7 10275f33ac92fSHawking Zhang #define regRLC_XT_DOORBELL_STAT_BASE_IDX 1 10276f33ac92fSHawking Zhang #define regRLC_XT_DOORBELL_0_DATA_LO 0x4df8 10277f33ac92fSHawking Zhang #define regRLC_XT_DOORBELL_0_DATA_LO_BASE_IDX 1 10278f33ac92fSHawking Zhang #define regRLC_XT_DOORBELL_0_DATA_HI 0x4df9 10279f33ac92fSHawking Zhang #define regRLC_XT_DOORBELL_0_DATA_HI_BASE_IDX 1 10280f33ac92fSHawking Zhang #define regRLC_XT_DOORBELL_1_DATA_LO 0x4dfa 10281f33ac92fSHawking Zhang #define regRLC_XT_DOORBELL_1_DATA_LO_BASE_IDX 1 10282f33ac92fSHawking Zhang #define regRLC_XT_DOORBELL_1_DATA_HI 0x4dfb 10283f33ac92fSHawking Zhang #define regRLC_XT_DOORBELL_1_DATA_HI_BASE_IDX 1 10284f33ac92fSHawking Zhang #define regRLC_XT_DOORBELL_2_DATA_LO 0x4dfc 10285f33ac92fSHawking Zhang #define regRLC_XT_DOORBELL_2_DATA_LO_BASE_IDX 1 10286f33ac92fSHawking Zhang #define regRLC_XT_DOORBELL_2_DATA_HI 0x4dfd 10287f33ac92fSHawking Zhang #define regRLC_XT_DOORBELL_2_DATA_HI_BASE_IDX 1 10288f33ac92fSHawking Zhang #define regRLC_XT_DOORBELL_3_DATA_LO 0x4dfe 10289f33ac92fSHawking Zhang #define regRLC_XT_DOORBELL_3_DATA_LO_BASE_IDX 1 10290f33ac92fSHawking Zhang #define regRLC_XT_DOORBELL_3_DATA_HI 0x4dff 10291f33ac92fSHawking Zhang #define regRLC_XT_DOORBELL_3_DATA_HI_BASE_IDX 1 10292f33ac92fSHawking Zhang #define regRLC_MEM_SLP_CNTL 0x4e00 10293f33ac92fSHawking Zhang #define regRLC_MEM_SLP_CNTL_BASE_IDX 1 10294f33ac92fSHawking Zhang #define regSMU_RLC_RESPONSE 0x4e01 10295f33ac92fSHawking Zhang #define regSMU_RLC_RESPONSE_BASE_IDX 1 10296f33ac92fSHawking Zhang #define regRLC_RLCV_SAFE_MODE 0x4e02 10297f33ac92fSHawking Zhang #define regRLC_RLCV_SAFE_MODE_BASE_IDX 1 10298f33ac92fSHawking Zhang #define regRLC_SMU_SAFE_MODE 0x4e03 10299f33ac92fSHawking Zhang #define regRLC_SMU_SAFE_MODE_BASE_IDX 1 10300f33ac92fSHawking Zhang #define regRLC_RLCV_COMMAND 0x4e04 10301f33ac92fSHawking Zhang #define regRLC_RLCV_COMMAND_BASE_IDX 1 10302f33ac92fSHawking Zhang #define regRLC_SMU_MESSAGE 0x4e05 10303f33ac92fSHawking Zhang #define regRLC_SMU_MESSAGE_BASE_IDX 1 10304f33ac92fSHawking Zhang #define regRLC_SMU_MESSAGE_1 0x4e06 10305f33ac92fSHawking Zhang #define regRLC_SMU_MESSAGE_1_BASE_IDX 1 10306f33ac92fSHawking Zhang #define regRLC_SMU_MESSAGE_2 0x4e07 10307f33ac92fSHawking Zhang #define regRLC_SMU_MESSAGE_2_BASE_IDX 1 10308f33ac92fSHawking Zhang #define regRLC_SRM_GPM_COMMAND 0x4e08 10309f33ac92fSHawking Zhang #define regRLC_SRM_GPM_COMMAND_BASE_IDX 1 10310f33ac92fSHawking Zhang #define regRLC_SRM_GPM_ABORT 0x4e09 10311f33ac92fSHawking Zhang #define regRLC_SRM_GPM_ABORT_BASE_IDX 1 10312f33ac92fSHawking Zhang #define regRLC_SMU_COMMAND 0x4e0a 10313f33ac92fSHawking Zhang #define regRLC_SMU_COMMAND_BASE_IDX 1 10314f33ac92fSHawking Zhang #define regRLC_SMU_ARGUMENT_1 0x4e0b 10315f33ac92fSHawking Zhang #define regRLC_SMU_ARGUMENT_1_BASE_IDX 1 10316f33ac92fSHawking Zhang #define regRLC_SMU_ARGUMENT_2 0x4e0c 10317f33ac92fSHawking Zhang #define regRLC_SMU_ARGUMENT_2_BASE_IDX 1 10318f33ac92fSHawking Zhang #define regRLC_SMU_ARGUMENT_3 0x4e0d 10319f33ac92fSHawking Zhang #define regRLC_SMU_ARGUMENT_3_BASE_IDX 1 10320f33ac92fSHawking Zhang #define regRLC_SMU_ARGUMENT_4 0x4e0e 10321f33ac92fSHawking Zhang #define regRLC_SMU_ARGUMENT_4_BASE_IDX 1 10322f33ac92fSHawking Zhang #define regRLC_SMU_ARGUMENT_5 0x4e0f 10323f33ac92fSHawking Zhang #define regRLC_SMU_ARGUMENT_5_BASE_IDX 1 10324f33ac92fSHawking Zhang #define regRLC_IMU_BOOTLOAD_ADDR_HI 0x4e10 10325f33ac92fSHawking Zhang #define regRLC_IMU_BOOTLOAD_ADDR_HI_BASE_IDX 1 10326f33ac92fSHawking Zhang #define regRLC_IMU_BOOTLOAD_ADDR_LO 0x4e11 10327f33ac92fSHawking Zhang #define regRLC_IMU_BOOTLOAD_ADDR_LO_BASE_IDX 1 10328f33ac92fSHawking Zhang #define regRLC_IMU_BOOTLOAD_SIZE 0x4e12 10329f33ac92fSHawking Zhang #define regRLC_IMU_BOOTLOAD_SIZE_BASE_IDX 1 10330f33ac92fSHawking Zhang #define regRLC_IMU_MISC 0x4e16 10331f33ac92fSHawking Zhang #define regRLC_IMU_MISC_BASE_IDX 1 10332f33ac92fSHawking Zhang #define regRLC_IMU_RESET_VECTOR 0x4e17 10333f33ac92fSHawking Zhang #define regRLC_IMU_RESET_VECTOR_BASE_IDX 1 10334f33ac92fSHawking Zhang 10335f33ac92fSHawking Zhang 10336f33ac92fSHawking Zhang // addressBlock: gc_rlcsdec 10337f33ac92fSHawking Zhang // base address: 0x3b980 10338f33ac92fSHawking Zhang #define regRLC_RLCS_DEC_START 0x4e60 10339f33ac92fSHawking Zhang #define regRLC_RLCS_DEC_START_BASE_IDX 1 10340f33ac92fSHawking Zhang #define regRLC_RLCS_DEC_DUMP_ADDR 0x4e61 10341f33ac92fSHawking Zhang #define regRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX 1 10342f33ac92fSHawking Zhang #define regRLC_RLCS_EXCEPTION_REG_1 0x4e62 10343f33ac92fSHawking Zhang #define regRLC_RLCS_EXCEPTION_REG_1_BASE_IDX 1 10344f33ac92fSHawking Zhang #define regRLC_RLCS_EXCEPTION_REG_2 0x4e63 10345f33ac92fSHawking Zhang #define regRLC_RLCS_EXCEPTION_REG_2_BASE_IDX 1 10346f33ac92fSHawking Zhang #define regRLC_RLCS_EXCEPTION_REG_3 0x4e64 10347f33ac92fSHawking Zhang #define regRLC_RLCS_EXCEPTION_REG_3_BASE_IDX 1 10348f33ac92fSHawking Zhang #define regRLC_RLCS_EXCEPTION_REG_4 0x4e65 10349f33ac92fSHawking Zhang #define regRLC_RLCS_EXCEPTION_REG_4_BASE_IDX 1 10350f33ac92fSHawking Zhang #define regRLC_RLCS_CGCG_REQUEST 0x4e66 10351f33ac92fSHawking Zhang #define regRLC_RLCS_CGCG_REQUEST_BASE_IDX 1 10352f33ac92fSHawking Zhang #define regRLC_RLCS_CGCG_STATUS 0x4e67 10353f33ac92fSHawking Zhang #define regRLC_RLCS_CGCG_STATUS_BASE_IDX 1 10354f33ac92fSHawking Zhang #define regRLC_RLCS_SOC_DS_CNTL 0x4e68 10355f33ac92fSHawking Zhang #define regRLC_RLCS_SOC_DS_CNTL_BASE_IDX 1 10356f33ac92fSHawking Zhang #define regRLC_RLCS_GFX_DS_CNTL 0x4e69 10357f33ac92fSHawking Zhang #define regRLC_RLCS_GFX_DS_CNTL_BASE_IDX 1 10358f33ac92fSHawking Zhang #define regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL 0x4e6a 10359f33ac92fSHawking Zhang #define regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL_BASE_IDX 1 10360f33ac92fSHawking Zhang #define regRLC_GPM_STAT 0x4e6b 10361f33ac92fSHawking Zhang #define regRLC_GPM_STAT_BASE_IDX 1 10362f33ac92fSHawking Zhang #define regRLC_RLCS_GPM_STAT 0x4e6b 10363f33ac92fSHawking Zhang #define regRLC_RLCS_GPM_STAT_BASE_IDX 1 10364f33ac92fSHawking Zhang #define regRLC_RLCS_ABORTED_PD_SEQUENCE 0x4e6c 10365f33ac92fSHawking Zhang #define regRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX 1 10366f33ac92fSHawking Zhang #define regRLC_RLCS_DIDT_FORCE_STALL 0x4e6d 10367f33ac92fSHawking Zhang #define regRLC_RLCS_DIDT_FORCE_STALL_BASE_IDX 1 10368f33ac92fSHawking Zhang #define regRLC_RLCS_IOV_CMD_STATUS 0x4e6e 10369f33ac92fSHawking Zhang #define regRLC_RLCS_IOV_CMD_STATUS_BASE_IDX 1 10370f33ac92fSHawking Zhang #define regRLC_RLCS_IOV_CNTX_LOC_SIZE 0x4e6f 10371f33ac92fSHawking Zhang #define regRLC_RLCS_IOV_CNTX_LOC_SIZE_BASE_IDX 1 10372f33ac92fSHawking Zhang #define regRLC_RLCS_IOV_SCH_BLOCK 0x4e70 10373f33ac92fSHawking Zhang #define regRLC_RLCS_IOV_SCH_BLOCK_BASE_IDX 1 10374f33ac92fSHawking Zhang #define regRLC_RLCS_IOV_VM_BUSY_STATUS 0x4e71 10375f33ac92fSHawking Zhang #define regRLC_RLCS_IOV_VM_BUSY_STATUS_BASE_IDX 1 10376f33ac92fSHawking Zhang #define regRLC_RLCS_GPM_STAT_2 0x4e72 10377f33ac92fSHawking Zhang #define regRLC_RLCS_GPM_STAT_2_BASE_IDX 1 10378f33ac92fSHawking Zhang #define regRLC_RLCS_GRBM_SOFT_RESET 0x4e73 10379f33ac92fSHawking Zhang #define regRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX 1 10380f33ac92fSHawking Zhang #define regRLC_RLCS_PG_CHANGE_STATUS 0x4e74 10381f33ac92fSHawking Zhang #define regRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX 1 10382f33ac92fSHawking Zhang #define regRLC_RLCS_PG_CHANGE_READ 0x4e75 10383f33ac92fSHawking Zhang #define regRLC_RLCS_PG_CHANGE_READ_BASE_IDX 1 10384f33ac92fSHawking Zhang #define regRLC_RLCS_IH_SEMAPHORE 0x4e76 10385f33ac92fSHawking Zhang #define regRLC_RLCS_IH_SEMAPHORE_BASE_IDX 1 10386f33ac92fSHawking Zhang #define regRLC_RLCS_IH_COOKIE_SEMAPHORE 0x4e77 10387f33ac92fSHawking Zhang #define regRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX 1 10388f33ac92fSHawking Zhang #define regRLC_RLCS_WGP_STATUS 0x4e78 10389f33ac92fSHawking Zhang #define regRLC_RLCS_WGP_STATUS_BASE_IDX 1 10390f33ac92fSHawking Zhang #define regRLC_RLCS_WGP_READ 0x4e79 10391f33ac92fSHawking Zhang #define regRLC_RLCS_WGP_READ_BASE_IDX 1 10392f33ac92fSHawking Zhang #define regRLC_RLCS_CP_INT_CTRL_1 0x4e7a 10393f33ac92fSHawking Zhang #define regRLC_RLCS_CP_INT_CTRL_1_BASE_IDX 1 10394f33ac92fSHawking Zhang #define regRLC_RLCS_CP_INT_CTRL_2 0x4e7b 10395f33ac92fSHawking Zhang #define regRLC_RLCS_CP_INT_CTRL_2_BASE_IDX 1 10396f33ac92fSHawking Zhang #define regRLC_RLCS_CP_INT_INFO_1 0x4e7c 10397f33ac92fSHawking Zhang #define regRLC_RLCS_CP_INT_INFO_1_BASE_IDX 1 10398f33ac92fSHawking Zhang #define regRLC_RLCS_CP_INT_INFO_2 0x4e7d 10399f33ac92fSHawking Zhang #define regRLC_RLCS_CP_INT_INFO_2_BASE_IDX 1 10400f33ac92fSHawking Zhang #define regRLC_RLCS_SPM_INT_CTRL 0x4e7e 10401f33ac92fSHawking Zhang #define regRLC_RLCS_SPM_INT_CTRL_BASE_IDX 1 10402f33ac92fSHawking Zhang #define regRLC_RLCS_SPM_INT_INFO_1 0x4e7f 10403f33ac92fSHawking Zhang #define regRLC_RLCS_SPM_INT_INFO_1_BASE_IDX 1 10404f33ac92fSHawking Zhang #define regRLC_RLCS_SPM_INT_INFO_2 0x4e80 10405f33ac92fSHawking Zhang #define regRLC_RLCS_SPM_INT_INFO_2_BASE_IDX 1 10406f33ac92fSHawking Zhang #define regRLC_RLCS_DSM_TRIG 0x4e81 10407f33ac92fSHawking Zhang #define regRLC_RLCS_DSM_TRIG_BASE_IDX 1 10408f33ac92fSHawking Zhang #define regRLC_RLCS_BOOTLOAD_STATUS 0x4e82 10409f33ac92fSHawking Zhang #define regRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX 1 10410f33ac92fSHawking Zhang #define regRLC_RLCS_POWER_BRAKE_CNTL 0x4e83 10411f33ac92fSHawking Zhang #define regRLC_RLCS_POWER_BRAKE_CNTL_BASE_IDX 1 10412f33ac92fSHawking Zhang #define regRLC_RLCS_POWER_BRAKE_CNTL_TH1 0x4e84 10413f33ac92fSHawking Zhang #define regRLC_RLCS_POWER_BRAKE_CNTL_TH1_BASE_IDX 1 10414f33ac92fSHawking Zhang #define regRLC_RLCS_GRBM_IDLE_BUSY_STAT 0x4e85 10415f33ac92fSHawking Zhang #define regRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX 1 10416f33ac92fSHawking Zhang #define regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL 0x4e86 10417f33ac92fSHawking Zhang #define regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX 1 10418f33ac92fSHawking Zhang #define regRLC_RLCS_CMP_IDLE_CNTL 0x4e87 10419f33ac92fSHawking Zhang #define regRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX 1 10420f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_0 0x4e88 10421f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_0_BASE_IDX 1 10422f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_1 0x4e89 10423f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_1_BASE_IDX 1 10424f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_2 0x4e8a 10425f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_2_BASE_IDX 1 10426f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_3 0x4e8b 10427f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_3_BASE_IDX 1 10428f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_4 0x4e8c 10429f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_4_BASE_IDX 1 10430f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_5 0x4e8d 10431f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_5_BASE_IDX 1 10432f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_6 0x4e8e 10433f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_6_BASE_IDX 1 10434f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_7 0x4e8f 10435f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_7_BASE_IDX 1 10436f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_8 0x4e90 10437f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_8_BASE_IDX 1 10438f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_9 0x4e91 10439f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_9_BASE_IDX 1 10440f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_10 0x4e92 10441f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_10_BASE_IDX 1 10442f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_11 0x4e93 10443f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_11_BASE_IDX 1 10444f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_12 0x4e94 10445f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_12_BASE_IDX 1 10446f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_13 0x4e95 10447f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_13_BASE_IDX 1 10448f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_14 0x4e96 10449f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_14_BASE_IDX 1 10450f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_15 0x4e97 10451f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_15_BASE_IDX 1 10452f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_16 0x4e98 10453f33ac92fSHawking Zhang #define regRLC_RLCS_GENERAL_16_BASE_IDX 1 10454f33ac92fSHawking Zhang #define regRLC_RLCS_AUXILIARY_REG_1 0x4ec5 10455f33ac92fSHawking Zhang #define regRLC_RLCS_AUXILIARY_REG_1_BASE_IDX 1 10456f33ac92fSHawking Zhang #define regRLC_RLCS_AUXILIARY_REG_2 0x4ec6 10457f33ac92fSHawking Zhang #define regRLC_RLCS_AUXILIARY_REG_2_BASE_IDX 1 10458f33ac92fSHawking Zhang #define regRLC_RLCS_AUXILIARY_REG_3 0x4ec7 10459f33ac92fSHawking Zhang #define regRLC_RLCS_AUXILIARY_REG_3_BASE_IDX 1 10460f33ac92fSHawking Zhang #define regRLC_RLCS_AUXILIARY_REG_4 0x4ec8 10461f33ac92fSHawking Zhang #define regRLC_RLCS_AUXILIARY_REG_4_BASE_IDX 1 10462f33ac92fSHawking Zhang #define regRLC_RLCS_SPM_SQTT_MODE 0x4ec9 10463f33ac92fSHawking Zhang #define regRLC_RLCS_SPM_SQTT_MODE_BASE_IDX 1 10464f33ac92fSHawking Zhang #define regRLC_RLCS_CP_DMA_SRCID_OVER 0x4eca 10465f33ac92fSHawking Zhang #define regRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX 1 10466f33ac92fSHawking Zhang #define regRLC_RLCS_BOOTLOAD_ID_STATUS1 0x4ecb 10467f33ac92fSHawking Zhang #define regRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX 1 10468f33ac92fSHawking Zhang #define regRLC_RLCS_BOOTLOAD_ID_STATUS2 0x4ecc 10469f33ac92fSHawking Zhang #define regRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX 1 10470f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_VIDCHG_CNTL 0x4ecd 10471f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_VIDCHG_CNTL_BASE_IDX 1 10472f33ac92fSHawking Zhang #define regRLC_RLCS_EDC_INT_CNTL 0x4ece 10473f33ac92fSHawking Zhang #define regRLC_RLCS_EDC_INT_CNTL_BASE_IDX 1 10474f33ac92fSHawking Zhang #define regRLC_RLCS_KMD_LOG_CNTL1 0x4ecf 10475f33ac92fSHawking Zhang #define regRLC_RLCS_KMD_LOG_CNTL1_BASE_IDX 1 10476f33ac92fSHawking Zhang #define regRLC_RLCS_KMD_LOG_CNTL2 0x4ed0 10477f33ac92fSHawking Zhang #define regRLC_RLCS_KMD_LOG_CNTL2_BASE_IDX 1 10478f33ac92fSHawking Zhang #define regRLC_RLCS_GPM_LEGACY_INT_STAT 0x4ed1 10479f33ac92fSHawking Zhang #define regRLC_RLCS_GPM_LEGACY_INT_STAT_BASE_IDX 1 10480f33ac92fSHawking Zhang #define regRLC_RLCS_GPM_LEGACY_INT_DISABLE 0x4ed2 10481f33ac92fSHawking Zhang #define regRLC_RLCS_GPM_LEGACY_INT_DISABLE_BASE_IDX 1 10482f33ac92fSHawking Zhang #define regRLC_RLCS_SRM_SRCID_CNTL 0x4ed3 10483f33ac92fSHawking Zhang #define regRLC_RLCS_SRM_SRCID_CNTL_BASE_IDX 1 10484f33ac92fSHawking Zhang #define regRLC_RLCS_GCR_DATA_0 0x4ed4 10485f33ac92fSHawking Zhang #define regRLC_RLCS_GCR_DATA_0_BASE_IDX 1 10486f33ac92fSHawking Zhang #define regRLC_RLCS_GCR_DATA_1 0x4ed5 10487f33ac92fSHawking Zhang #define regRLC_RLCS_GCR_DATA_1_BASE_IDX 1 10488f33ac92fSHawking Zhang #define regRLC_RLCS_GCR_DATA_2 0x4ed6 10489f33ac92fSHawking Zhang #define regRLC_RLCS_GCR_DATA_2_BASE_IDX 1 10490f33ac92fSHawking Zhang #define regRLC_RLCS_GCR_DATA_3 0x4ed7 10491f33ac92fSHawking Zhang #define regRLC_RLCS_GCR_DATA_3_BASE_IDX 1 10492f33ac92fSHawking Zhang #define regRLC_RLCS_GCR_STATUS 0x4ed8 10493f33ac92fSHawking Zhang #define regRLC_RLCS_GCR_STATUS_BASE_IDX 1 10494f33ac92fSHawking Zhang #define regRLC_RLCS_PERFMON_CLK_CNTL_UCODE 0x4ed9 10495f33ac92fSHawking Zhang #define regRLC_RLCS_PERFMON_CLK_CNTL_UCODE_BASE_IDX 1 10496f33ac92fSHawking Zhang #define regRLC_RLCS_UTCL2_CNTL 0x4eda 10497f33ac92fSHawking Zhang #define regRLC_RLCS_UTCL2_CNTL_BASE_IDX 1 10498f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RLC_MSG_DATA0 0x4edb 10499f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RLC_MSG_DATA0_BASE_IDX 1 10500f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RLC_MSG_DATA1 0x4edc 10501f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RLC_MSG_DATA1_BASE_IDX 1 10502f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RLC_MSG_DATA2 0x4edd 10503f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RLC_MSG_DATA2_BASE_IDX 1 10504f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RLC_MSG_DATA3 0x4ede 10505f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RLC_MSG_DATA3_BASE_IDX 1 10506f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RLC_MSG_DATA4 0x4edf 10507f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RLC_MSG_DATA4_BASE_IDX 1 10508f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RLC_MSG_CONTROL 0x4ee0 10509f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RLC_MSG_CONTROL_BASE_IDX 1 10510f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RLC_MSG_CNTL 0x4ee1 10511f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RLC_MSG_CNTL_BASE_IDX 1 10512f33ac92fSHawking Zhang #define regRLC_RLCS_RLC_IMU_MSG_DATA0 0x4ee2 10513f33ac92fSHawking Zhang #define regRLC_RLCS_RLC_IMU_MSG_DATA0_BASE_IDX 1 10514f33ac92fSHawking Zhang #define regRLC_RLCS_RLC_IMU_MSG_CONTROL 0x4ee3 10515f33ac92fSHawking Zhang #define regRLC_RLCS_RLC_IMU_MSG_CONTROL_BASE_IDX 1 10516f33ac92fSHawking Zhang #define regRLC_RLCS_RLC_IMU_MSG_CNTL 0x4ee4 10517f33ac92fSHawking Zhang #define regRLC_RLCS_RLC_IMU_MSG_CNTL_BASE_IDX 1 10518f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0 0x4ee5 10519f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0_BASE_IDX 1 10520f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1 0x4ee6 10521f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1_BASE_IDX 1 10522f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RLC_MUTEX_CNTL 0x4ee7 10523f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RLC_MUTEX_CNTL_BASE_IDX 1 10524f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RLC_STATUS 0x4ee8 10525f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RLC_STATUS_BASE_IDX 1 10526f33ac92fSHawking Zhang #define regRLC_RLCS_RLC_IMU_STATUS 0x4ee9 10527f33ac92fSHawking Zhang #define regRLC_RLCS_RLC_IMU_STATUS_BASE_IDX 1 10528f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RAM_DATA_1 0x4eea 10529f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RAM_DATA_1_BASE_IDX 1 10530f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RAM_ADDR_1_LSB 0x4eeb 10531f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RAM_ADDR_1_LSB_BASE_IDX 1 10532f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RAM_ADDR_1_MSB 0x4eec 10533f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RAM_ADDR_1_MSB_BASE_IDX 1 10534f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RAM_DATA_0 0x4eed 10535f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RAM_DATA_0_BASE_IDX 1 10536f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RAM_ADDR_0_LSB 0x4eee 10537f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RAM_ADDR_0_LSB_BASE_IDX 1 10538f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RAM_ADDR_0_MSB 0x4eef 10539f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RAM_ADDR_0_MSB_BASE_IDX 1 10540f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RAM_CNTL 0x4ef0 10541f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_RAM_CNTL_BASE_IDX 1 10542f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_GFX_DOORBELL_FENCE 0x4ef1 10543f33ac92fSHawking Zhang #define regRLC_RLCS_IMU_GFX_DOORBELL_FENCE_BASE_IDX 1 10544f33ac92fSHawking Zhang #define regRLC_RLCS_SDMA_INT_CNTL_1 0x4ef3 10545f33ac92fSHawking Zhang #define regRLC_RLCS_SDMA_INT_CNTL_1_BASE_IDX 1 10546f33ac92fSHawking Zhang #define regRLC_RLCS_SDMA_INT_CNTL_2 0x4ef4 10547f33ac92fSHawking Zhang #define regRLC_RLCS_SDMA_INT_CNTL_2_BASE_IDX 1 10548f33ac92fSHawking Zhang #define regRLC_RLCS_SDMA_INT_STAT 0x4ef5 10549f33ac92fSHawking Zhang #define regRLC_RLCS_SDMA_INT_STAT_BASE_IDX 1 10550f33ac92fSHawking Zhang #define regRLC_RLCS_SDMA_INT_INFO 0x4ef6 10551f33ac92fSHawking Zhang #define regRLC_RLCS_SDMA_INT_INFO_BASE_IDX 1 10552f33ac92fSHawking Zhang #define regRLC_RLCS_PMM_CGCG_CNTL 0x4ef7 10553f33ac92fSHawking Zhang #define regRLC_RLCS_PMM_CGCG_CNTL_BASE_IDX 1 10554f33ac92fSHawking Zhang #define regRLC_RLCS_GFX_MEM_POWER_CTRL_LO 0x4ef8 10555f33ac92fSHawking Zhang #define regRLC_RLCS_GFX_MEM_POWER_CTRL_LO_BASE_IDX 1 10556f33ac92fSHawking Zhang #define regRLC_RLCS_GFX_RM_CNTL 0x4efa 10557f33ac92fSHawking Zhang #define regRLC_RLCS_GFX_RM_CNTL_BASE_IDX 1 10558f33ac92fSHawking Zhang #define regRLC_RLCS_DEC_END 0x4fff 10559f33ac92fSHawking Zhang #define regRLC_RLCS_DEC_END_BASE_IDX 1 10560f33ac92fSHawking Zhang 10561f33ac92fSHawking Zhang 10562f33ac92fSHawking Zhang // addressBlock: gc_pfvfdec_rlc 10563f33ac92fSHawking Zhang // base address: 0x2a600 10564f33ac92fSHawking Zhang #define regRLC_SAFE_MODE 0x0980 10565f33ac92fSHawking Zhang #define regRLC_SAFE_MODE_BASE_IDX 1 10566f33ac92fSHawking Zhang #define regRLC_SPM_SAMPLE_CNT 0x0981 10567f33ac92fSHawking Zhang #define regRLC_SPM_SAMPLE_CNT_BASE_IDX 1 10568f33ac92fSHawking Zhang #define regRLC_SPM_MC_CNTL 0x0982 10569f33ac92fSHawking Zhang #define regRLC_SPM_MC_CNTL_BASE_IDX 1 10570f33ac92fSHawking Zhang #define regRLC_SPM_INT_CNTL 0x0983 10571f33ac92fSHawking Zhang #define regRLC_SPM_INT_CNTL_BASE_IDX 1 10572f33ac92fSHawking Zhang #define regRLC_SPM_INT_STATUS 0x0984 10573f33ac92fSHawking Zhang #define regRLC_SPM_INT_STATUS_BASE_IDX 1 10574f33ac92fSHawking Zhang #define regRLC_SPM_INT_INFO_1 0x0985 10575f33ac92fSHawking Zhang #define regRLC_SPM_INT_INFO_1_BASE_IDX 1 10576f33ac92fSHawking Zhang #define regRLC_SPM_INT_INFO_2 0x0986 10577f33ac92fSHawking Zhang #define regRLC_SPM_INT_INFO_2_BASE_IDX 1 10578f33ac92fSHawking Zhang #define regRLC_CSIB_ADDR_LO 0x0987 10579f33ac92fSHawking Zhang #define regRLC_CSIB_ADDR_LO_BASE_IDX 1 10580f33ac92fSHawking Zhang #define regRLC_CSIB_ADDR_HI 0x0988 10581f33ac92fSHawking Zhang #define regRLC_CSIB_ADDR_HI_BASE_IDX 1 10582f33ac92fSHawking Zhang #define regRLC_CSIB_LENGTH 0x0989 10583f33ac92fSHawking Zhang #define regRLC_CSIB_LENGTH_BASE_IDX 1 10584f33ac92fSHawking Zhang #define regRLC_CP_SCHEDULERS 0x098a 10585f33ac92fSHawking Zhang #define regRLC_CP_SCHEDULERS_BASE_IDX 1 10586f33ac92fSHawking Zhang #define regRLC_CP_EOF_INT 0x098b 10587f33ac92fSHawking Zhang #define regRLC_CP_EOF_INT_BASE_IDX 1 10588f33ac92fSHawking Zhang #define regRLC_CP_EOF_INT_CNT 0x098c 10589f33ac92fSHawking Zhang #define regRLC_CP_EOF_INT_CNT_BASE_IDX 1 10590f33ac92fSHawking Zhang #define regRLC_SPARE_INT_0 0x098d 10591f33ac92fSHawking Zhang #define regRLC_SPARE_INT_0_BASE_IDX 1 10592f33ac92fSHawking Zhang #define regRLC_SPARE_INT_1 0x098e 10593f33ac92fSHawking Zhang #define regRLC_SPARE_INT_1_BASE_IDX 1 10594f33ac92fSHawking Zhang #define regRLC_SPARE_INT_2 0x098f 10595f33ac92fSHawking Zhang #define regRLC_SPARE_INT_2_BASE_IDX 1 10596f33ac92fSHawking Zhang #define regRLC_PACE_SPARE_INT 0x0990 10597f33ac92fSHawking Zhang #define regRLC_PACE_SPARE_INT_BASE_IDX 1 10598f33ac92fSHawking Zhang #define regRLC_PACE_SPARE_INT_1 0x0991 10599f33ac92fSHawking Zhang #define regRLC_PACE_SPARE_INT_1_BASE_IDX 1 10600f33ac92fSHawking Zhang #define regRLC_RLCV_SPARE_INT_1 0x0992 10601f33ac92fSHawking Zhang #define regRLC_RLCV_SPARE_INT_1_BASE_IDX 1 10602f33ac92fSHawking Zhang 10603f33ac92fSHawking Zhang 10604f33ac92fSHawking Zhang // addressBlock: gc_pwrdec 10605f33ac92fSHawking Zhang // base address: 0x3c000 10606f33ac92fSHawking Zhang #define regCGTS_TCC_DISABLE 0x5006 10607f33ac92fSHawking Zhang #define regCGTS_TCC_DISABLE_BASE_IDX 1 10608f33ac92fSHawking Zhang #define regCGTT_GS_NGG_CLK_CTRL 0x5087 10609f33ac92fSHawking Zhang #define regCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 10610f33ac92fSHawking Zhang #define regCGTT_PA_CLK_CTRL 0x5088 10611f33ac92fSHawking Zhang #define regCGTT_PA_CLK_CTRL_BASE_IDX 1 10612f33ac92fSHawking Zhang #define regCGTT_SC_CLK_CTRL0 0x5089 10613f33ac92fSHawking Zhang #define regCGTT_SC_CLK_CTRL0_BASE_IDX 1 10614f33ac92fSHawking Zhang #define regCGTT_SC_CLK_CTRL1 0x508a 10615f33ac92fSHawking Zhang #define regCGTT_SC_CLK_CTRL1_BASE_IDX 1 10616f33ac92fSHawking Zhang #define regCGTT_SC_CLK_CTRL2 0x508b 10617f33ac92fSHawking Zhang #define regCGTT_SC_CLK_CTRL2_BASE_IDX 1 10618f33ac92fSHawking Zhang #define regCGTT_SQG_CLK_CTRL 0x508d 10619f33ac92fSHawking Zhang #define regCGTT_SQG_CLK_CTRL_BASE_IDX 1 10620f33ac92fSHawking Zhang #define regSQ_ALU_CLK_CTRL 0x508e 10621f33ac92fSHawking Zhang #define regSQ_ALU_CLK_CTRL_BASE_IDX 1 10622f33ac92fSHawking Zhang #define regSQ_TEX_CLK_CTRL 0x508f 10623f33ac92fSHawking Zhang #define regSQ_TEX_CLK_CTRL_BASE_IDX 1 10624f33ac92fSHawking Zhang #define regSQ_LDS_CLK_CTRL 0x5090 10625f33ac92fSHawking Zhang #define regSQ_LDS_CLK_CTRL_BASE_IDX 1 10626f33ac92fSHawking Zhang #define regICG_SP_CLK_CTRL 0x5093 10627f33ac92fSHawking Zhang #define regICG_SP_CLK_CTRL_BASE_IDX 1 10628f33ac92fSHawking Zhang #define regTA_CGTT_CTRL 0x509d 10629f33ac92fSHawking Zhang #define regTA_CGTT_CTRL_BASE_IDX 1 10630f33ac92fSHawking Zhang #define regDB_CGTT_CLK_CTRL_0 0x50a4 10631f33ac92fSHawking Zhang #define regDB_CGTT_CLK_CTRL_0_BASE_IDX 1 10632f33ac92fSHawking Zhang #define regCB_CGTT_SCLK_CTRL 0x50a8 10633f33ac92fSHawking Zhang #define regCB_CGTT_SCLK_CTRL_BASE_IDX 1 10634f33ac92fSHawking Zhang #define regCGTT_CP_CLK_CTRL 0x50b0 10635f33ac92fSHawking Zhang #define regCGTT_CP_CLK_CTRL_BASE_IDX 1 10636f33ac92fSHawking Zhang #define regCGTT_CPF_CLK_CTRL 0x50b1 10637f33ac92fSHawking Zhang #define regCGTT_CPF_CLK_CTRL_BASE_IDX 1 10638f33ac92fSHawking Zhang #define regCGTT_CPC_CLK_CTRL 0x50b2 10639f33ac92fSHawking Zhang #define regCGTT_CPC_CLK_CTRL_BASE_IDX 1 10640f33ac92fSHawking Zhang #define regCGTT_RLC_CLK_CTRL 0x50b5 10641f33ac92fSHawking Zhang #define regCGTT_RLC_CLK_CTRL_BASE_IDX 1 10642f33ac92fSHawking Zhang #define regCGTT_SC_CLK_CTRL3 0x50bc 10643f33ac92fSHawking Zhang #define regCGTT_SC_CLK_CTRL3_BASE_IDX 1 10644f33ac92fSHawking Zhang #define regCGTT_SC_CLK_CTRL4 0x50bd 10645f33ac92fSHawking Zhang #define regCGTT_SC_CLK_CTRL4_BASE_IDX 1 10646f33ac92fSHawking Zhang #define regGCEA_ICG_CTRL 0x50c4 10647f33ac92fSHawking Zhang #define regGCEA_ICG_CTRL_BASE_IDX 1 10648f33ac92fSHawking Zhang #define regGL1I_GL1R_MGCG_OVERRIDE 0x50e4 10649f33ac92fSHawking Zhang #define regGL1I_GL1R_MGCG_OVERRIDE_BASE_IDX 1 10650f33ac92fSHawking Zhang #define regGL1H_ICG_CTRL 0x50e8 10651f33ac92fSHawking Zhang #define regGL1H_ICG_CTRL_BASE_IDX 1 10652f33ac92fSHawking Zhang #define regCHI_CHR_MGCG_OVERRIDE 0x50e9 10653f33ac92fSHawking Zhang #define regCHI_CHR_MGCG_OVERRIDE_BASE_IDX 1 10654f33ac92fSHawking Zhang #define regICG_GL1C_CLK_CTRL 0x50ec 10655f33ac92fSHawking Zhang #define regICG_GL1C_CLK_CTRL_BASE_IDX 1 10656f33ac92fSHawking Zhang #define regICG_GL1A_CTRL 0x50f0 10657f33ac92fSHawking Zhang #define regICG_GL1A_CTRL_BASE_IDX 1 10658f33ac92fSHawking Zhang #define regICG_CHA_CTRL 0x50f1 10659f33ac92fSHawking Zhang #define regICG_CHA_CTRL_BASE_IDX 1 10660f33ac92fSHawking Zhang #define regGUS_ICG_CTRL 0x50f4 10661f33ac92fSHawking Zhang #define regGUS_ICG_CTRL_BASE_IDX 1 10662f33ac92fSHawking Zhang #define regCGTT_PH_CLK_CTRL0 0x50f8 10663f33ac92fSHawking Zhang #define regCGTT_PH_CLK_CTRL0_BASE_IDX 1 10664f33ac92fSHawking Zhang #define regCGTT_PH_CLK_CTRL1 0x50f9 10665f33ac92fSHawking Zhang #define regCGTT_PH_CLK_CTRL1_BASE_IDX 1 10666f33ac92fSHawking Zhang #define regCGTT_PH_CLK_CTRL2 0x50fa 10667f33ac92fSHawking Zhang #define regCGTT_PH_CLK_CTRL2_BASE_IDX 1 10668f33ac92fSHawking Zhang #define regCGTT_PH_CLK_CTRL3 0x50fb 10669f33ac92fSHawking Zhang #define regCGTT_PH_CLK_CTRL3_BASE_IDX 1 10670f33ac92fSHawking Zhang #define regGFX_ICG_GL2C_CTRL 0x50fc 10671f33ac92fSHawking Zhang #define regGFX_ICG_GL2C_CTRL_BASE_IDX 1 10672f33ac92fSHawking Zhang #define regGFX_ICG_GL2C_CTRL1 0x50fd 10673f33ac92fSHawking Zhang #define regGFX_ICG_GL2C_CTRL1_BASE_IDX 1 10674f33ac92fSHawking Zhang #define regICG_LDS_CLK_CTRL 0x5114 10675f33ac92fSHawking Zhang #define regICG_LDS_CLK_CTRL_BASE_IDX 1 10676f33ac92fSHawking Zhang #define regICG_CHC_CLK_CTRL 0x5140 10677f33ac92fSHawking Zhang #define regICG_CHC_CLK_CTRL_BASE_IDX 1 10678f33ac92fSHawking Zhang #define regICG_CHCG_CLK_CTRL 0x5144 10679f33ac92fSHawking Zhang #define regICG_CHCG_CLK_CTRL_BASE_IDX 1 10680f33ac92fSHawking Zhang 10681f33ac92fSHawking Zhang 10682f33ac92fSHawking Zhang // addressBlock: gc_hypdec 10683f33ac92fSHawking Zhang // base address: 0x3e000 10684f33ac92fSHawking Zhang #define regGFX_PIPE_PRIORITY 0x587f 10685f33ac92fSHawking Zhang #define regGFX_PIPE_PRIORITY_BASE_IDX 1 10686f33ac92fSHawking Zhang #define regGRBM_GFX_INDEX_SR_SELECT 0x5a00 10687f33ac92fSHawking Zhang #define regGRBM_GFX_INDEX_SR_SELECT_BASE_IDX 1 10688f33ac92fSHawking Zhang #define regGRBM_GFX_INDEX_SR_DATA 0x5a01 10689f33ac92fSHawking Zhang #define regGRBM_GFX_INDEX_SR_DATA_BASE_IDX 1 10690f33ac92fSHawking Zhang #define regGRBM_GFX_CNTL_SR_SELECT 0x5a02 10691f33ac92fSHawking Zhang #define regGRBM_GFX_CNTL_SR_SELECT_BASE_IDX 1 10692f33ac92fSHawking Zhang #define regGRBM_GFX_CNTL_SR_DATA 0x5a03 10693f33ac92fSHawking Zhang #define regGRBM_GFX_CNTL_SR_DATA_BASE_IDX 1 10694f33ac92fSHawking Zhang #define regGC_IH_COOKIE_0_PTR 0x5a07 10695f33ac92fSHawking Zhang #define regGC_IH_COOKIE_0_PTR_BASE_IDX 1 10696f33ac92fSHawking Zhang #define regGRBM_SE_REMAP_CNTL 0x5a08 10697f33ac92fSHawking Zhang #define regGRBM_SE_REMAP_CNTL_BASE_IDX 1 10698f33ac92fSHawking Zhang #define regRLC_GPU_IOV_VF_ENABLE 0x5b00 10699f33ac92fSHawking Zhang #define regRLC_GPU_IOV_VF_ENABLE_BASE_IDX 1 10700f33ac92fSHawking Zhang #define regRLC_GPU_IOV_CFG_REG6 0x5b06 10701f33ac92fSHawking Zhang #define regRLC_GPU_IOV_CFG_REG6_BASE_IDX 1 10702f33ac92fSHawking Zhang #define regRLC_SDMA0_STATUS 0x5b18 10703f33ac92fSHawking Zhang #define regRLC_SDMA0_STATUS_BASE_IDX 1 10704f33ac92fSHawking Zhang #define regRLC_SDMA1_STATUS 0x5b19 10705f33ac92fSHawking Zhang #define regRLC_SDMA1_STATUS_BASE_IDX 1 10706f33ac92fSHawking Zhang #define regRLC_SDMA2_STATUS 0x5b1a 10707f33ac92fSHawking Zhang #define regRLC_SDMA2_STATUS_BASE_IDX 1 10708f33ac92fSHawking Zhang #define regRLC_SDMA3_STATUS 0x5b1b 10709f33ac92fSHawking Zhang #define regRLC_SDMA3_STATUS_BASE_IDX 1 10710f33ac92fSHawking Zhang #define regRLC_SDMA0_BUSY_STATUS 0x5b1c 10711f33ac92fSHawking Zhang #define regRLC_SDMA0_BUSY_STATUS_BASE_IDX 1 10712f33ac92fSHawking Zhang #define regRLC_SDMA1_BUSY_STATUS 0x5b1d 10713f33ac92fSHawking Zhang #define regRLC_SDMA1_BUSY_STATUS_BASE_IDX 1 10714f33ac92fSHawking Zhang #define regRLC_SDMA2_BUSY_STATUS 0x5b1e 10715f33ac92fSHawking Zhang #define regRLC_SDMA2_BUSY_STATUS_BASE_IDX 1 10716f33ac92fSHawking Zhang #define regRLC_SDMA3_BUSY_STATUS 0x5b1f 10717f33ac92fSHawking Zhang #define regRLC_SDMA3_BUSY_STATUS_BASE_IDX 1 10718f33ac92fSHawking Zhang #define regRLC_GPU_IOV_CFG_REG8 0x5b20 10719f33ac92fSHawking Zhang #define regRLC_GPU_IOV_CFG_REG8_BASE_IDX 1 10720f33ac92fSHawking Zhang #define regRLC_RLCV_TIMER_INT_0 0x5b25 10721f33ac92fSHawking Zhang #define regRLC_RLCV_TIMER_INT_0_BASE_IDX 1 10722f33ac92fSHawking Zhang #define regRLC_RLCV_TIMER_INT_1 0x5b26 10723f33ac92fSHawking Zhang #define regRLC_RLCV_TIMER_INT_1_BASE_IDX 1 10724f33ac92fSHawking Zhang #define regRLC_RLCV_TIMER_CTRL 0x5b27 10725f33ac92fSHawking Zhang #define regRLC_RLCV_TIMER_CTRL_BASE_IDX 1 10726f33ac92fSHawking Zhang #define regRLC_RLCV_TIMER_STAT 0x5b28 10727f33ac92fSHawking Zhang #define regRLC_RLCV_TIMER_STAT_BASE_IDX 1 10728f33ac92fSHawking Zhang #define regRLC_GPU_IOV_VF_DOORBELL_STATUS 0x5b2a 10729f33ac92fSHawking Zhang #define regRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX 1 10730f33ac92fSHawking Zhang #define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET 0x5b2b 10731f33ac92fSHawking Zhang #define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX 1 10732f33ac92fSHawking Zhang #define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR 0x5b2c 10733f33ac92fSHawking Zhang #define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX 1 10734f33ac92fSHawking Zhang #define regRLC_GPU_IOV_VF_MASK 0x5b2d 10735f33ac92fSHawking Zhang #define regRLC_GPU_IOV_VF_MASK_BASE_IDX 1 10736f33ac92fSHawking Zhang #define regRLC_HYP_SEMAPHORE_0 0x5b2e 10737f33ac92fSHawking Zhang #define regRLC_HYP_SEMAPHORE_0_BASE_IDX 1 10738f33ac92fSHawking Zhang #define regRLC_HYP_SEMAPHORE_1 0x5b2f 10739f33ac92fSHawking Zhang #define regRLC_HYP_SEMAPHORE_1_BASE_IDX 1 10740f33ac92fSHawking Zhang #define regRLC_BUSY_CLK_CNTL 0x5b30 10741f33ac92fSHawking Zhang #define regRLC_BUSY_CLK_CNTL_BASE_IDX 1 10742f33ac92fSHawking Zhang #define regRLC_CLK_CNTL 0x5b31 10743f33ac92fSHawking Zhang #define regRLC_CLK_CNTL_BASE_IDX 1 10744f33ac92fSHawking Zhang #define regRLC_PACE_TIMER_STAT 0x5b33 10745f33ac92fSHawking Zhang #define regRLC_PACE_TIMER_STAT_BASE_IDX 1 10746f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SCH_BLOCK 0x5b34 10747f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SCH_BLOCK_BASE_IDX 1 10748f33ac92fSHawking Zhang #define regRLC_GPU_IOV_CFG_REG1 0x5b35 10749f33ac92fSHawking Zhang #define regRLC_GPU_IOV_CFG_REG1_BASE_IDX 1 10750f33ac92fSHawking Zhang #define regRLC_GPU_IOV_CFG_REG2 0x5b36 10751f33ac92fSHawking Zhang #define regRLC_GPU_IOV_CFG_REG2_BASE_IDX 1 10752f33ac92fSHawking Zhang #define regRLC_GPU_IOV_VM_BUSY_STATUS 0x5b37 10753f33ac92fSHawking Zhang #define regRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX 1 10754f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SCH_0 0x5b38 10755f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SCH_0_BASE_IDX 1 10756f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SCH_3 0x5b3a 10757f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SCH_3_BASE_IDX 1 10758f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SCH_1 0x5b3b 10759f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SCH_1_BASE_IDX 1 10760f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SCH_2 0x5b3c 10761f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SCH_2_BASE_IDX 1 10762f33ac92fSHawking Zhang #define regRLC_PACE_INT_FORCE 0x5b3d 10763f33ac92fSHawking Zhang #define regRLC_PACE_INT_FORCE_BASE_IDX 1 10764f33ac92fSHawking Zhang #define regRLC_PACE_INT_CLEAR 0x5b3e 10765f33ac92fSHawking Zhang #define regRLC_PACE_INT_CLEAR_BASE_IDX 1 10766f33ac92fSHawking Zhang #define regRLC_GPU_IOV_INT_STAT 0x5b3f 10767f33ac92fSHawking Zhang #define regRLC_GPU_IOV_INT_STAT_BASE_IDX 1 10768f33ac92fSHawking Zhang #define regRLC_IH_COOKIE 0x5b41 10769f33ac92fSHawking Zhang #define regRLC_IH_COOKIE_BASE_IDX 1 10770f33ac92fSHawking Zhang #define regRLC_IH_COOKIE_CNTL 0x5b42 10771f33ac92fSHawking Zhang #define regRLC_IH_COOKIE_CNTL_BASE_IDX 1 10772f33ac92fSHawking Zhang #define regRLC_HYP_RLCG_UCODE_CHKSUM 0x5b43 10773f33ac92fSHawking Zhang #define regRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX 1 10774f33ac92fSHawking Zhang #define regRLC_HYP_RLCP_UCODE_CHKSUM 0x5b44 10775f33ac92fSHawking Zhang #define regRLC_HYP_RLCP_UCODE_CHKSUM_BASE_IDX 1 10776f33ac92fSHawking Zhang #define regRLC_HYP_RLCV_UCODE_CHKSUM 0x5b45 10777f33ac92fSHawking Zhang #define regRLC_HYP_RLCV_UCODE_CHKSUM_BASE_IDX 1 10778f33ac92fSHawking Zhang #define regRLC_GPU_IOV_F32_CNTL 0x5b46 10779f33ac92fSHawking Zhang #define regRLC_GPU_IOV_F32_CNTL_BASE_IDX 1 10780f33ac92fSHawking Zhang #define regRLC_GPU_IOV_F32_RESET 0x5b47 10781f33ac92fSHawking Zhang #define regRLC_GPU_IOV_F32_RESET_BASE_IDX 1 10782f33ac92fSHawking Zhang #define regRLC_GPU_IOV_UCODE_ADDR 0x5b48 10783f33ac92fSHawking Zhang #define regRLC_GPU_IOV_UCODE_ADDR_BASE_IDX 1 10784f33ac92fSHawking Zhang #define regRLC_GPU_IOV_UCODE_DATA 0x5b49 10785f33ac92fSHawking Zhang #define regRLC_GPU_IOV_UCODE_DATA_BASE_IDX 1 10786f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SMU_RESPONSE 0x5b4a 10787f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX 1 10788f33ac92fSHawking Zhang #define regRLC_GPU_IOV_F32_INVALIDATE_CACHE 0x5b4b 10789f33ac92fSHawking Zhang #define regRLC_GPU_IOV_F32_INVALIDATE_CACHE_BASE_IDX 1 10790f33ac92fSHawking Zhang #define regRLC_GPU_IOV_RLC_RESPONSE 0x5b4d 10791f33ac92fSHawking Zhang #define regRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX 1 10792f33ac92fSHawking Zhang #define regRLC_GPU_IOV_INT_DISABLE 0x5b4e 10793f33ac92fSHawking Zhang #define regRLC_GPU_IOV_INT_DISABLE_BASE_IDX 1 10794f33ac92fSHawking Zhang #define regRLC_GPU_IOV_INT_FORCE 0x5b4f 10795f33ac92fSHawking Zhang #define regRLC_GPU_IOV_INT_FORCE_BASE_IDX 1 10796f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SCRATCH_ADDR 0x5b50 10797f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX 1 10798f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SCRATCH_DATA 0x5b51 10799f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX 1 10800f33ac92fSHawking Zhang #define regRLC_HYP_SEMAPHORE_2 0x5b52 10801f33ac92fSHawking Zhang #define regRLC_HYP_SEMAPHORE_2_BASE_IDX 1 10802f33ac92fSHawking Zhang #define regRLC_HYP_SEMAPHORE_3 0x5b53 10803f33ac92fSHawking Zhang #define regRLC_HYP_SEMAPHORE_3_BASE_IDX 1 10804f33ac92fSHawking Zhang #define regRLC_GPM_UCODE_ADDR 0x5b60 10805f33ac92fSHawking Zhang #define regRLC_GPM_UCODE_ADDR_BASE_IDX 1 10806f33ac92fSHawking Zhang #define regRLC_GPM_UCODE_DATA 0x5b61 10807f33ac92fSHawking Zhang #define regRLC_GPM_UCODE_DATA_BASE_IDX 1 10808f33ac92fSHawking Zhang #define regRLC_GPM_IRAM_ADDR 0x5b62 10809f33ac92fSHawking Zhang #define regRLC_GPM_IRAM_ADDR_BASE_IDX 1 10810f33ac92fSHawking Zhang #define regRLC_GPM_IRAM_DATA 0x5b63 10811f33ac92fSHawking Zhang #define regRLC_GPM_IRAM_DATA_BASE_IDX 1 10812f33ac92fSHawking Zhang #define regRLC_RLCP_IRAM_ADDR 0x5b64 10813f33ac92fSHawking Zhang #define regRLC_RLCP_IRAM_ADDR_BASE_IDX 1 10814f33ac92fSHawking Zhang #define regRLC_RLCP_IRAM_DATA 0x5b65 10815f33ac92fSHawking Zhang #define regRLC_RLCP_IRAM_DATA_BASE_IDX 1 10816f33ac92fSHawking Zhang #define regRLC_RLCV_IRAM_ADDR 0x5b66 10817f33ac92fSHawking Zhang #define regRLC_RLCV_IRAM_ADDR_BASE_IDX 1 10818f33ac92fSHawking Zhang #define regRLC_RLCV_IRAM_DATA 0x5b67 10819f33ac92fSHawking Zhang #define regRLC_RLCV_IRAM_DATA_BASE_IDX 1 10820f33ac92fSHawking Zhang #define regRLC_LX6_DRAM_ADDR 0x5b68 10821f33ac92fSHawking Zhang #define regRLC_LX6_DRAM_ADDR_BASE_IDX 1 10822f33ac92fSHawking Zhang #define regRLC_LX6_DRAM_DATA 0x5b69 10823f33ac92fSHawking Zhang #define regRLC_LX6_DRAM_DATA_BASE_IDX 1 10824f33ac92fSHawking Zhang #define regRLC_LX6_IRAM_ADDR 0x5b6a 10825f33ac92fSHawking Zhang #define regRLC_LX6_IRAM_ADDR_BASE_IDX 1 10826f33ac92fSHawking Zhang #define regRLC_LX6_IRAM_DATA 0x5b6b 10827f33ac92fSHawking Zhang #define regRLC_LX6_IRAM_DATA_BASE_IDX 1 10828f33ac92fSHawking Zhang #define regRLC_PACE_UCODE_ADDR 0x5b6c 10829f33ac92fSHawking Zhang #define regRLC_PACE_UCODE_ADDR_BASE_IDX 1 10830f33ac92fSHawking Zhang #define regRLC_PACE_UCODE_DATA 0x5b6d 10831f33ac92fSHawking Zhang #define regRLC_PACE_UCODE_DATA_BASE_IDX 1 10832f33ac92fSHawking Zhang #define regRLC_GPM_SCRATCH_ADDR 0x5b6e 10833f33ac92fSHawking Zhang #define regRLC_GPM_SCRATCH_ADDR_BASE_IDX 1 10834f33ac92fSHawking Zhang #define regRLC_GPM_SCRATCH_DATA 0x5b6f 10835f33ac92fSHawking Zhang #define regRLC_GPM_SCRATCH_DATA_BASE_IDX 1 10836f33ac92fSHawking Zhang #define regRLC_SRM_DRAM_ADDR 0x5b71 10837f33ac92fSHawking Zhang #define regRLC_SRM_DRAM_ADDR_BASE_IDX 1 10838f33ac92fSHawking Zhang #define regRLC_SRM_DRAM_DATA 0x5b72 10839f33ac92fSHawking Zhang #define regRLC_SRM_DRAM_DATA_BASE_IDX 1 10840f33ac92fSHawking Zhang #define regRLC_SRM_ARAM_ADDR 0x5b73 10841f33ac92fSHawking Zhang #define regRLC_SRM_ARAM_ADDR_BASE_IDX 1 10842f33ac92fSHawking Zhang #define regRLC_SRM_ARAM_DATA 0x5b74 10843f33ac92fSHawking Zhang #define regRLC_SRM_ARAM_DATA_BASE_IDX 1 10844f33ac92fSHawking Zhang #define regRLC_PACE_SCRATCH_ADDR 0x5b77 10845f33ac92fSHawking Zhang #define regRLC_PACE_SCRATCH_ADDR_BASE_IDX 1 10846f33ac92fSHawking Zhang #define regRLC_PACE_SCRATCH_DATA 0x5b78 10847f33ac92fSHawking Zhang #define regRLC_PACE_SCRATCH_DATA_BASE_IDX 1 10848f33ac92fSHawking Zhang #define regRLC_GTS_OFFSET_LSB 0x5b79 10849f33ac92fSHawking Zhang #define regRLC_GTS_OFFSET_LSB_BASE_IDX 1 10850f33ac92fSHawking Zhang #define regRLC_GTS_OFFSET_MSB 0x5b7a 10851f33ac92fSHawking Zhang #define regRLC_GTS_OFFSET_MSB_BASE_IDX 1 10852f33ac92fSHawking Zhang #define regGL2_PIPE_STEER_0 0x5b80 10853f33ac92fSHawking Zhang #define regGL2_PIPE_STEER_0_BASE_IDX 1 10854f33ac92fSHawking Zhang #define regGL2_PIPE_STEER_1 0x5b81 10855f33ac92fSHawking Zhang #define regGL2_PIPE_STEER_1_BASE_IDX 1 10856f33ac92fSHawking Zhang #define regGL2_PIPE_STEER_2 0x5b82 10857f33ac92fSHawking Zhang #define regGL2_PIPE_STEER_2_BASE_IDX 1 10858f33ac92fSHawking Zhang #define regGL2_PIPE_STEER_3 0x5b83 10859f33ac92fSHawking Zhang #define regGL2_PIPE_STEER_3_BASE_IDX 1 10860f33ac92fSHawking Zhang #define regGL1_PIPE_STEER 0x5b84 10861f33ac92fSHawking Zhang #define regGL1_PIPE_STEER_BASE_IDX 1 10862f33ac92fSHawking Zhang #define regCH_PIPE_STEER 0x5b88 10863f33ac92fSHawking Zhang #define regCH_PIPE_STEER_BASE_IDX 1 10864f33ac92fSHawking Zhang #define regGC_USER_SHADER_ARRAY_CONFIG 0x5b90 10865f33ac92fSHawking Zhang #define regGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX 1 10866f33ac92fSHawking Zhang #define regGC_USER_PRIM_CONFIG 0x5b91 10867f33ac92fSHawking Zhang #define regGC_USER_PRIM_CONFIG_BASE_IDX 1 10868f33ac92fSHawking Zhang #define regGC_USER_SA_UNIT_DISABLE 0x5b92 10869f33ac92fSHawking Zhang #define regGC_USER_SA_UNIT_DISABLE_BASE_IDX 1 10870f33ac92fSHawking Zhang #define regGC_USER_RB_REDUNDANCY 0x5b93 10871f33ac92fSHawking Zhang #define regGC_USER_RB_REDUNDANCY_BASE_IDX 1 10872f33ac92fSHawking Zhang #define regGC_USER_RB_BACKEND_DISABLE 0x5b94 10873f33ac92fSHawking Zhang #define regGC_USER_RB_BACKEND_DISABLE_BASE_IDX 1 10874f33ac92fSHawking Zhang #define regGC_USER_RMI_REDUNDANCY 0x5b95 10875f33ac92fSHawking Zhang #define regGC_USER_RMI_REDUNDANCY_BASE_IDX 1 10876f33ac92fSHawking Zhang #define regCGTS_USER_TCC_DISABLE 0x5b96 10877f33ac92fSHawking Zhang #define regCGTS_USER_TCC_DISABLE_BASE_IDX 1 10878f33ac92fSHawking Zhang #define regGC_USER_SHADER_RATE_CONFIG 0x5b97 10879f33ac92fSHawking Zhang #define regGC_USER_SHADER_RATE_CONFIG_BASE_IDX 1 10880f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA0_STATUS 0x5bc0 10881f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX 1 10882f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA1_STATUS 0x5bc1 10883f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX 1 10884f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA2_STATUS 0x5bc2 10885f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX 1 10886f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA3_STATUS 0x5bc3 10887f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX 1 10888f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA4_STATUS 0x5bc4 10889f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX 1 10890f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA5_STATUS 0x5bc5 10891f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX 1 10892f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA6_STATUS 0x5bc6 10893f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX 1 10894f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA7_STATUS 0x5bc7 10895f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX 1 10896f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA0_BUSY_STATUS 0x5bc8 10897f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX 1 10898f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA1_BUSY_STATUS 0x5bc9 10899f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX 1 10900f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA2_BUSY_STATUS 0x5bca 10901f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX 1 10902f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA3_BUSY_STATUS 0x5bcb 10903f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX 1 10904f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA4_BUSY_STATUS 0x5bcc 10905f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX 1 10906f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA5_BUSY_STATUS 0x5bcd 10907f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX 1 10908f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA6_BUSY_STATUS 0x5bce 10909f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX 1 10910f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA7_BUSY_STATUS 0x5bcf 10911f33ac92fSHawking Zhang #define regRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX 1 10912f33ac92fSHawking Zhang 10913f33ac92fSHawking Zhang 10914f33ac92fSHawking Zhang // addressBlock: gc_pspdec 10915f33ac92fSHawking Zhang // base address: 0x3f000 10916f33ac92fSHawking Zhang #define regCP_MES_DM_INDEX_ADDR 0x5c00 10917f33ac92fSHawking Zhang #define regCP_MES_DM_INDEX_ADDR_BASE_IDX 1 10918f33ac92fSHawking Zhang #define regCP_MES_DM_INDEX_DATA 0x5c01 10919f33ac92fSHawking Zhang #define regCP_MES_DM_INDEX_DATA_BASE_IDX 1 10920f33ac92fSHawking Zhang #define regCP_MEC_DM_INDEX_ADDR 0x5c02 10921f33ac92fSHawking Zhang #define regCP_MEC_DM_INDEX_ADDR_BASE_IDX 1 10922f33ac92fSHawking Zhang #define regCP_MEC_DM_INDEX_DATA 0x5c03 10923f33ac92fSHawking Zhang #define regCP_MEC_DM_INDEX_DATA_BASE_IDX 1 10924f33ac92fSHawking Zhang #define regCP_GFX_RS64_DM_INDEX_ADDR 0x5c04 10925f33ac92fSHawking Zhang #define regCP_GFX_RS64_DM_INDEX_ADDR_BASE_IDX 1 10926f33ac92fSHawking Zhang #define regCP_GFX_RS64_DM_INDEX_DATA 0x5c05 10927f33ac92fSHawking Zhang #define regCP_GFX_RS64_DM_INDEX_DATA_BASE_IDX 1 10928f33ac92fSHawking Zhang #define regCPG_PSP_DEBUG 0x5c10 10929f33ac92fSHawking Zhang #define regCPG_PSP_DEBUG_BASE_IDX 1 10930f33ac92fSHawking Zhang #define regCPC_PSP_DEBUG 0x5c11 10931f33ac92fSHawking Zhang #define regCPC_PSP_DEBUG_BASE_IDX 1 10932f33ac92fSHawking Zhang #define regGRBM_SEC_CNTL 0x5e0d 10933f33ac92fSHawking Zhang #define regGRBM_SEC_CNTL_BASE_IDX 1 10934f33ac92fSHawking Zhang #define regGRBM_CAM_INDEX 0x5e10 10935f33ac92fSHawking Zhang #define regGRBM_CAM_INDEX_BASE_IDX 1 10936f33ac92fSHawking Zhang #define regGRBM_HYP_CAM_INDEX 0x5e10 10937f33ac92fSHawking Zhang #define regGRBM_HYP_CAM_INDEX_BASE_IDX 1 10938f33ac92fSHawking Zhang #define regGRBM_CAM_DATA 0x5e11 10939f33ac92fSHawking Zhang #define regGRBM_CAM_DATA_BASE_IDX 1 10940f33ac92fSHawking Zhang #define regGRBM_HYP_CAM_DATA 0x5e11 10941f33ac92fSHawking Zhang #define regGRBM_HYP_CAM_DATA_BASE_IDX 1 10942f33ac92fSHawking Zhang #define regGRBM_CAM_DATA_UPPER 0x5e12 10943f33ac92fSHawking Zhang #define regGRBM_CAM_DATA_UPPER_BASE_IDX 1 10944f33ac92fSHawking Zhang #define regGRBM_HYP_CAM_DATA_UPPER 0x5e12 10945f33ac92fSHawking Zhang #define regGRBM_HYP_CAM_DATA_UPPER_BASE_IDX 1 10946f33ac92fSHawking Zhang #define regRLC_FWL_FIRST_VIOL_ADDR 0x5f26 10947f33ac92fSHawking Zhang #define regRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX 1 10948f33ac92fSHawking Zhang 10949f33ac92fSHawking Zhang 10950f33ac92fSHawking Zhang // addressBlock: gc_gfx_imu_gfx_imudec 10951f33ac92fSHawking Zhang // base address: 0x38000 10952f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_0 0x4000 10953f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_0_BASE_IDX 1 10954f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_1 0x4001 10955f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_1_BASE_IDX 1 10956f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_2 0x4002 10957f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_2_BASE_IDX 1 10958f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_3 0x4003 10959f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_3_BASE_IDX 1 10960f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_4 0x4004 10961f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_4_BASE_IDX 1 10962f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_5 0x4005 10963f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_5_BASE_IDX 1 10964f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_6 0x4006 10965f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_6_BASE_IDX 1 10966f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_7 0x4007 10967f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_7_BASE_IDX 1 10968f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_8 0x4008 10969f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_8_BASE_IDX 1 10970f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_9 0x4009 10971f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_9_BASE_IDX 1 10972f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_10 0x400a 10973f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_10_BASE_IDX 1 10974f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_11 0x400b 10975f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_11_BASE_IDX 1 10976f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_12 0x400c 10977f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_12_BASE_IDX 1 10978f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_13 0x400d 10979f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_13_BASE_IDX 1 10980f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_14 0x400e 10981f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_14_BASE_IDX 1 10982f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_15 0x400f 10983f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_15_BASE_IDX 1 10984f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_16 0x4010 10985f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_16_BASE_IDX 1 10986f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_17 0x4011 10987f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_17_BASE_IDX 1 10988f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_18 0x4012 10989f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_18_BASE_IDX 1 10990f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_19 0x4013 10991f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_19_BASE_IDX 1 10992f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_20 0x4014 10993f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_20_BASE_IDX 1 10994f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_21 0x4015 10995f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_21_BASE_IDX 1 10996f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_22 0x4016 10997f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_22_BASE_IDX 1 10998f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_23 0x4017 10999f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_23_BASE_IDX 1 11000f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_24 0x4018 11001f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_24_BASE_IDX 1 11002f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_25 0x4019 11003f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_25_BASE_IDX 1 11004f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_26 0x401a 11005f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_26_BASE_IDX 1 11006f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_27 0x401b 11007f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_27_BASE_IDX 1 11008f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_28 0x401c 11009f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_28_BASE_IDX 1 11010f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_29 0x401d 11011f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_29_BASE_IDX 1 11012f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_30 0x401e 11013f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_30_BASE_IDX 1 11014f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_31 0x401f 11015f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_31_BASE_IDX 1 11016f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_32 0x4020 11017f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_32_BASE_IDX 1 11018f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_33 0x4021 11019f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_33_BASE_IDX 1 11020f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_34 0x4022 11021f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_34_BASE_IDX 1 11022f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_35 0x4023 11023f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_35_BASE_IDX 1 11024f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_36 0x4024 11025f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_36_BASE_IDX 1 11026f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_37 0x4025 11027f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_37_BASE_IDX 1 11028f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_38 0x4026 11029f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_38_BASE_IDX 1 11030f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_39 0x4027 11031f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_39_BASE_IDX 1 11032f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_40 0x4028 11033f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_40_BASE_IDX 1 11034f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_41 0x4029 11035f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_41_BASE_IDX 1 11036f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_42 0x402a 11037f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_42_BASE_IDX 1 11038f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_43 0x402b 11039f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_43_BASE_IDX 1 11040f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_44 0x402c 11041f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_44_BASE_IDX 1 11042f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_45 0x402d 11043f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_45_BASE_IDX 1 11044f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_46 0x402e 11045f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_46_BASE_IDX 1 11046f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_47 0x402f 11047f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_47_BASE_IDX 1 11048f33ac92fSHawking Zhang #define regGFX_IMU_MSG_FLAGS 0x403f 11049f33ac92fSHawking Zhang #define regGFX_IMU_MSG_FLAGS_BASE_IDX 1 11050f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_ACCESS_CTRL0 0x4040 11051f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_ACCESS_CTRL0_BASE_IDX 1 11052f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_ACCESS_CTRL1 0x4041 11053f33ac92fSHawking Zhang #define regGFX_IMU_C2PMSG_ACCESS_CTRL1_BASE_IDX 1 11054f33ac92fSHawking Zhang #define regGFX_IMU_PWRMGT_IRQ_CTRL 0x4042 11055f33ac92fSHawking Zhang #define regGFX_IMU_PWRMGT_IRQ_CTRL_BASE_IDX 1 11056f33ac92fSHawking Zhang #define regGFX_IMU_MP1_MUTEX 0x4043 11057f33ac92fSHawking Zhang #define regGFX_IMU_MP1_MUTEX_BASE_IDX 1 11058f33ac92fSHawking Zhang #define regGFX_IMU_RLC_DATA_4 0x4046 11059f33ac92fSHawking Zhang #define regGFX_IMU_RLC_DATA_4_BASE_IDX 1 11060f33ac92fSHawking Zhang #define regGFX_IMU_RLC_DATA_3 0x4047 11061f33ac92fSHawking Zhang #define regGFX_IMU_RLC_DATA_3_BASE_IDX 1 11062f33ac92fSHawking Zhang #define regGFX_IMU_RLC_DATA_2 0x4048 11063f33ac92fSHawking Zhang #define regGFX_IMU_RLC_DATA_2_BASE_IDX 1 11064f33ac92fSHawking Zhang #define regGFX_IMU_RLC_DATA_1 0x4049 11065f33ac92fSHawking Zhang #define regGFX_IMU_RLC_DATA_1_BASE_IDX 1 11066f33ac92fSHawking Zhang #define regGFX_IMU_RLC_DATA_0 0x404a 11067f33ac92fSHawking Zhang #define regGFX_IMU_RLC_DATA_0_BASE_IDX 1 11068f33ac92fSHawking Zhang #define regGFX_IMU_RLC_CMD 0x404b 11069f33ac92fSHawking Zhang #define regGFX_IMU_RLC_CMD_BASE_IDX 1 11070f33ac92fSHawking Zhang #define regGFX_IMU_RLC_MUTEX 0x404c 11071f33ac92fSHawking Zhang #define regGFX_IMU_RLC_MUTEX_BASE_IDX 1 11072f33ac92fSHawking Zhang #define regGFX_IMU_RLC_MSG_STATUS 0x404f 11073f33ac92fSHawking Zhang #define regGFX_IMU_RLC_MSG_STATUS_BASE_IDX 1 11074f33ac92fSHawking Zhang #define regRLC_GFX_IMU_DATA_0 0x4052 11075f33ac92fSHawking Zhang #define regRLC_GFX_IMU_DATA_0_BASE_IDX 1 11076f33ac92fSHawking Zhang #define regRLC_GFX_IMU_CMD 0x4053 11077f33ac92fSHawking Zhang #define regRLC_GFX_IMU_CMD_BASE_IDX 1 11078f33ac92fSHawking Zhang #define regGFX_IMU_RLC_STATUS 0x4054 11079f33ac92fSHawking Zhang #define regGFX_IMU_RLC_STATUS_BASE_IDX 1 11080f33ac92fSHawking Zhang #define regGFX_IMU_STATUS 0x4055 11081f33ac92fSHawking Zhang #define regGFX_IMU_STATUS_BASE_IDX 1 11082f33ac92fSHawking Zhang #define regGFX_IMU_SOC_DATA 0x4059 11083f33ac92fSHawking Zhang #define regGFX_IMU_SOC_DATA_BASE_IDX 1 11084f33ac92fSHawking Zhang #define regGFX_IMU_SOC_ADDR 0x405a 11085f33ac92fSHawking Zhang #define regGFX_IMU_SOC_ADDR_BASE_IDX 1 11086f33ac92fSHawking Zhang #define regGFX_IMU_SOC_REQ 0x405b 11087f33ac92fSHawking Zhang #define regGFX_IMU_SOC_REQ_BASE_IDX 1 11088f33ac92fSHawking Zhang #define regGFX_IMU_VF_CTRL 0x405c 11089f33ac92fSHawking Zhang #define regGFX_IMU_VF_CTRL_BASE_IDX 1 11090f33ac92fSHawking Zhang #define regGFX_IMU_TELEMETRY 0x4060 11091f33ac92fSHawking Zhang #define regGFX_IMU_TELEMETRY_BASE_IDX 1 11092f33ac92fSHawking Zhang #define regGFX_IMU_TELEMETRY_DATA 0x4061 11093f33ac92fSHawking Zhang #define regGFX_IMU_TELEMETRY_DATA_BASE_IDX 1 11094f33ac92fSHawking Zhang #define regGFX_IMU_TELEMETRY_TEMPERATURE 0x4062 11095f33ac92fSHawking Zhang #define regGFX_IMU_TELEMETRY_TEMPERATURE_BASE_IDX 1 11096f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_0 0x4068 11097f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_0_BASE_IDX 1 11098f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_1 0x4069 11099f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_1_BASE_IDX 1 11100f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_2 0x406a 11101f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_2_BASE_IDX 1 11102f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_3 0x406b 11103f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_3_BASE_IDX 1 11104f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_4 0x406c 11105f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_4_BASE_IDX 1 11106f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_5 0x406d 11107f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_5_BASE_IDX 1 11108f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_6 0x406e 11109f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_6_BASE_IDX 1 11110f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_7 0x406f 11111f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_7_BASE_IDX 1 11112f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_8 0x4070 11113f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_8_BASE_IDX 1 11114f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_9 0x4071 11115f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_9_BASE_IDX 1 11116f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_10 0x4072 11117f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_10_BASE_IDX 1 11118f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_11 0x4073 11119f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_11_BASE_IDX 1 11120f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_12 0x4074 11121f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_12_BASE_IDX 1 11122f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_13 0x4075 11123f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_13_BASE_IDX 1 11124f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_14 0x4076 11125f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_14_BASE_IDX 1 11126f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_15 0x4077 11127f33ac92fSHawking Zhang #define regGFX_IMU_SCRATCH_15_BASE_IDX 1 11128f33ac92fSHawking Zhang #define regGFX_IMU_FW_GTS_LO 0x4078 11129f33ac92fSHawking Zhang #define regGFX_IMU_FW_GTS_LO_BASE_IDX 1 11130f33ac92fSHawking Zhang #define regGFX_IMU_FW_GTS_HI 0x4079 11131f33ac92fSHawking Zhang #define regGFX_IMU_FW_GTS_HI_BASE_IDX 1 11132f33ac92fSHawking Zhang #define regGFX_IMU_GTS_OFFSET_LO 0x407a 11133f33ac92fSHawking Zhang #define regGFX_IMU_GTS_OFFSET_LO_BASE_IDX 1 11134f33ac92fSHawking Zhang #define regGFX_IMU_GTS_OFFSET_HI 0x407b 11135f33ac92fSHawking Zhang #define regGFX_IMU_GTS_OFFSET_HI_BASE_IDX 1 11136f33ac92fSHawking Zhang #define regGFX_IMU_RLC_GTS_OFFSET_LO 0x407c 11137f33ac92fSHawking Zhang #define regGFX_IMU_RLC_GTS_OFFSET_LO_BASE_IDX 1 11138f33ac92fSHawking Zhang #define regGFX_IMU_RLC_GTS_OFFSET_HI 0x407d 11139f33ac92fSHawking Zhang #define regGFX_IMU_RLC_GTS_OFFSET_HI_BASE_IDX 1 11140f33ac92fSHawking Zhang #define regGFX_IMU_CORE_INT_STATUS 0x407f 11141f33ac92fSHawking Zhang #define regGFX_IMU_CORE_INT_STATUS_BASE_IDX 1 11142f33ac92fSHawking Zhang #define regGFX_IMU_PIC_INT_MASK 0x4080 11143f33ac92fSHawking Zhang #define regGFX_IMU_PIC_INT_MASK_BASE_IDX 1 11144f33ac92fSHawking Zhang #define regGFX_IMU_PIC_INT_LVL 0x4081 11145f33ac92fSHawking Zhang #define regGFX_IMU_PIC_INT_LVL_BASE_IDX 1 11146f33ac92fSHawking Zhang #define regGFX_IMU_PIC_INT_EDGE 0x4082 11147f33ac92fSHawking Zhang #define regGFX_IMU_PIC_INT_EDGE_BASE_IDX 1 11148f33ac92fSHawking Zhang #define regGFX_IMU_PIC_INT_PRI_0 0x4083 11149f33ac92fSHawking Zhang #define regGFX_IMU_PIC_INT_PRI_0_BASE_IDX 1 11150f33ac92fSHawking Zhang #define regGFX_IMU_PIC_INT_PRI_1 0x4084 11151f33ac92fSHawking Zhang #define regGFX_IMU_PIC_INT_PRI_1_BASE_IDX 1 11152f33ac92fSHawking Zhang #define regGFX_IMU_PIC_INT_PRI_2 0x4085 11153f33ac92fSHawking Zhang #define regGFX_IMU_PIC_INT_PRI_2_BASE_IDX 1 11154f33ac92fSHawking Zhang #define regGFX_IMU_PIC_INT_PRI_3 0x4086 11155f33ac92fSHawking Zhang #define regGFX_IMU_PIC_INT_PRI_3_BASE_IDX 1 11156f33ac92fSHawking Zhang #define regGFX_IMU_PIC_INT_PRI_4 0x4087 11157f33ac92fSHawking Zhang #define regGFX_IMU_PIC_INT_PRI_4_BASE_IDX 1 11158f33ac92fSHawking Zhang #define regGFX_IMU_PIC_INT_PRI_5 0x4088 11159f33ac92fSHawking Zhang #define regGFX_IMU_PIC_INT_PRI_5_BASE_IDX 1 11160f33ac92fSHawking Zhang #define regGFX_IMU_PIC_INT_PRI_6 0x4089 11161f33ac92fSHawking Zhang #define regGFX_IMU_PIC_INT_PRI_6_BASE_IDX 1 11162f33ac92fSHawking Zhang #define regGFX_IMU_PIC_INT_PRI_7 0x408a 11163f33ac92fSHawking Zhang #define regGFX_IMU_PIC_INT_PRI_7_BASE_IDX 1 11164f33ac92fSHawking Zhang #define regGFX_IMU_PIC_INT_STATUS 0x408b 11165f33ac92fSHawking Zhang #define regGFX_IMU_PIC_INT_STATUS_BASE_IDX 1 11166f33ac92fSHawking Zhang #define regGFX_IMU_PIC_INTR 0x408c 11167f33ac92fSHawking Zhang #define regGFX_IMU_PIC_INTR_BASE_IDX 1 11168f33ac92fSHawking Zhang #define regGFX_IMU_PIC_INTR_ID 0x408d 11169f33ac92fSHawking Zhang #define regGFX_IMU_PIC_INTR_ID_BASE_IDX 1 11170f33ac92fSHawking Zhang #define regGFX_IMU_IH_CTRL_1 0x4090 11171f33ac92fSHawking Zhang #define regGFX_IMU_IH_CTRL_1_BASE_IDX 1 11172f33ac92fSHawking Zhang #define regGFX_IMU_IH_CTRL_2 0x4091 11173f33ac92fSHawking Zhang #define regGFX_IMU_IH_CTRL_2_BASE_IDX 1 11174f33ac92fSHawking Zhang #define regGFX_IMU_IH_CTRL_3 0x4092 11175f33ac92fSHawking Zhang #define regGFX_IMU_IH_CTRL_3_BASE_IDX 1 11176f33ac92fSHawking Zhang #define regGFX_IMU_IH_STATUS 0x4093 11177f33ac92fSHawking Zhang #define regGFX_IMU_IH_STATUS_BASE_IDX 1 11178f33ac92fSHawking Zhang #define regGFX_IMU_FUSESTRAP 0x4094 11179f33ac92fSHawking Zhang #define regGFX_IMU_SMUIO_VIDCHG_CTRL 0x4098 11180f33ac92fSHawking Zhang #define regGFX_IMU_SMUIO_VIDCHG_CTRL_BASE_IDX 1 11181f33ac92fSHawking Zhang #define regGFX_IMU_GFXCLK_BYPASS_CTRL 0x409c 11182f33ac92fSHawking Zhang #define regGFX_IMU_GFXCLK_BYPASS_CTRL_BASE_IDX 1 11183f33ac92fSHawking Zhang #define regGFX_IMU_CLK_CTRL 0x409d 11184f33ac92fSHawking Zhang #define regGFX_IMU_CLK_CTRL_BASE_IDX 1 11185f33ac92fSHawking Zhang #define regGFX_IMU_DOORBELL_CONTROL 0x409e 11186f33ac92fSHawking Zhang #define regGFX_IMU_DOORBELL_CONTROL_BASE_IDX 1 11187f33ac92fSHawking Zhang #define regGFX_IMU_RLC_CG_CTRL 0x40a0 11188f33ac92fSHawking Zhang #define regGFX_IMU_RLC_CG_CTRL_BASE_IDX 1 11189f33ac92fSHawking Zhang #define regGFX_IMU_RLC_THROTTLE_GFX 0x40a1 11190f33ac92fSHawking Zhang #define regGFX_IMU_RLC_THROTTLE_GFX_BASE_IDX 1 11191f33ac92fSHawking Zhang #define regGFX_IMU_RLC_RESET_VECTOR 0x40a2 11192f33ac92fSHawking Zhang #define regGFX_IMU_RLC_RESET_VECTOR_BASE_IDX 1 11193f33ac92fSHawking Zhang #define regGFX_IMU_RLC_OVERRIDE 0x40a3 11194f33ac92fSHawking Zhang #define regGFX_IMU_RLC_OVERRIDE_BASE_IDX 1 11195f33ac92fSHawking Zhang #define regGFX_IMU_DPM_CONTROL 0x40a8 11196f33ac92fSHawking Zhang #define regGFX_IMU_DPM_CONTROL_BASE_IDX 1 11197f33ac92fSHawking Zhang #define regGFX_IMU_DPM_ACC 0x40a9 11198f33ac92fSHawking Zhang #define regGFX_IMU_DPM_ACC_BASE_IDX 1 11199f33ac92fSHawking Zhang #define regGFX_IMU_DPM_REF_COUNTER 0x40aa 11200f33ac92fSHawking Zhang #define regGFX_IMU_DPM_REF_COUNTER_BASE_IDX 1 11201f33ac92fSHawking Zhang #define regGFX_IMU_RLC_RAM_INDEX 0x40ac 11202f33ac92fSHawking Zhang #define regGFX_IMU_RLC_RAM_INDEX_BASE_IDX 1 11203f33ac92fSHawking Zhang #define regGFX_IMU_RLC_RAM_ADDR_HIGH 0x40ad 11204f33ac92fSHawking Zhang #define regGFX_IMU_RLC_RAM_ADDR_HIGH_BASE_IDX 1 11205f33ac92fSHawking Zhang #define regGFX_IMU_RLC_RAM_ADDR_LOW 0x40ae 11206f33ac92fSHawking Zhang #define regGFX_IMU_RLC_RAM_ADDR_LOW_BASE_IDX 1 11207f33ac92fSHawking Zhang #define regGFX_IMU_RLC_RAM_DATA 0x40af 11208f33ac92fSHawking Zhang #define regGFX_IMU_RLC_RAM_DATA_BASE_IDX 1 11209f33ac92fSHawking Zhang #define regGFX_IMU_FENCE_CTRL 0x40b0 11210f33ac92fSHawking Zhang #define regGFX_IMU_FENCE_CTRL_BASE_IDX 1 11211f33ac92fSHawking Zhang #define regGFX_IMU_FENCE_LOG_INIT 0x40b1 11212f33ac92fSHawking Zhang #define regGFX_IMU_FENCE_LOG_INIT_BASE_IDX 1 11213f33ac92fSHawking Zhang #define regGFX_IMU_FENCE_LOG_ADDR 0x40b2 11214f33ac92fSHawking Zhang #define regGFX_IMU_FENCE_LOG_ADDR_BASE_IDX 1 11215f33ac92fSHawking Zhang #define regGFX_IMU_PROGRAM_CTR 0x40b5 11216f33ac92fSHawking Zhang #define regGFX_IMU_PROGRAM_CTR_BASE_IDX 1 11217f33ac92fSHawking Zhang #define regGFX_IMU_CORE_CTRL 0x40b6 11218f33ac92fSHawking Zhang #define regGFX_IMU_CORE_CTRL_BASE_IDX 1 11219f33ac92fSHawking Zhang #define regGFX_IMU_CORE_STATUS 0x40b7 11220f33ac92fSHawking Zhang #define regGFX_IMU_CORE_STATUS_BASE_IDX 1 11221f33ac92fSHawking Zhang #define regGFX_IMU_PWROKRAW 0x40b8 11222f33ac92fSHawking Zhang #define regGFX_IMU_PWROKRAW_BASE_IDX 1 11223f33ac92fSHawking Zhang #define regGFX_IMU_PWROK 0x40b9 11224f33ac92fSHawking Zhang #define regGFX_IMU_PWROK_BASE_IDX 1 11225f33ac92fSHawking Zhang #define regGFX_IMU_GAP_PWROK 0x40ba 11226f33ac92fSHawking Zhang #define regGFX_IMU_GAP_PWROK_BASE_IDX 1 11227f33ac92fSHawking Zhang #define regGFX_IMU_RESETn 0x40bb 11228f33ac92fSHawking Zhang #define regGFX_IMU_RESETn_BASE_IDX 1 11229f33ac92fSHawking Zhang #define regGFX_IMU_GFX_RESET_CTRL 0x40bc 11230f33ac92fSHawking Zhang #define regGFX_IMU_GFX_RESET_CTRL_BASE_IDX 1 11231f33ac92fSHawking Zhang #define regGFX_IMU_AEB_OVERRIDE 0x40bd 11232f33ac92fSHawking Zhang #define regGFX_IMU_AEB_OVERRIDE_BASE_IDX 1 11233f33ac92fSHawking Zhang #define regGFX_IMU_VDCI_RESET_CTRL 0x40be 11234f33ac92fSHawking Zhang #define regGFX_IMU_VDCI_RESET_CTRL_BASE_IDX 1 11235f33ac92fSHawking Zhang #define regGFX_IMU_GFX_ISO_CTRL 0x40bf 11236f33ac92fSHawking Zhang #define regGFX_IMU_GFX_ISO_CTRL_BASE_IDX 1 11237f33ac92fSHawking Zhang #define regGFX_IMU_TIMER0_CTRL0 0x40c0 11238f33ac92fSHawking Zhang #define regGFX_IMU_TIMER0_CTRL0_BASE_IDX 1 11239f33ac92fSHawking Zhang #define regGFX_IMU_TIMER0_CTRL1 0x40c1 11240f33ac92fSHawking Zhang #define regGFX_IMU_TIMER0_CTRL1_BASE_IDX 1 11241f33ac92fSHawking Zhang #define regGFX_IMU_TIMER0_CMP_AUTOINC 0x40c2 11242f33ac92fSHawking Zhang #define regGFX_IMU_TIMER0_CMP_AUTOINC_BASE_IDX 1 11243f33ac92fSHawking Zhang #define regGFX_IMU_TIMER0_CMP_INTEN 0x40c3 11244f33ac92fSHawking Zhang #define regGFX_IMU_TIMER0_CMP_INTEN_BASE_IDX 1 11245f33ac92fSHawking Zhang #define regGFX_IMU_TIMER0_CMP0 0x40c4 11246f33ac92fSHawking Zhang #define regGFX_IMU_TIMER0_CMP0_BASE_IDX 1 11247f33ac92fSHawking Zhang #define regGFX_IMU_TIMER0_CMP1 0x40c5 11248f33ac92fSHawking Zhang #define regGFX_IMU_TIMER0_CMP1_BASE_IDX 1 11249f33ac92fSHawking Zhang #define regGFX_IMU_TIMER0_CMP3 0x40c7 11250f33ac92fSHawking Zhang #define regGFX_IMU_TIMER0_CMP3_BASE_IDX 1 11251f33ac92fSHawking Zhang #define regGFX_IMU_TIMER0_VALUE 0x40c8 11252f33ac92fSHawking Zhang #define regGFX_IMU_TIMER0_VALUE_BASE_IDX 1 11253f33ac92fSHawking Zhang #define regGFX_IMU_TIMER1_CTRL0 0x40c9 11254f33ac92fSHawking Zhang #define regGFX_IMU_TIMER1_CTRL0_BASE_IDX 1 11255f33ac92fSHawking Zhang #define regGFX_IMU_TIMER1_CTRL1 0x40ca 11256f33ac92fSHawking Zhang #define regGFX_IMU_TIMER1_CTRL1_BASE_IDX 1 11257f33ac92fSHawking Zhang #define regGFX_IMU_TIMER1_CMP_AUTOINC 0x40cb 11258f33ac92fSHawking Zhang #define regGFX_IMU_TIMER1_CMP_AUTOINC_BASE_IDX 1 11259f33ac92fSHawking Zhang #define regGFX_IMU_TIMER1_CMP_INTEN 0x40cc 11260f33ac92fSHawking Zhang #define regGFX_IMU_TIMER1_CMP_INTEN_BASE_IDX 1 11261f33ac92fSHawking Zhang #define regGFX_IMU_TIMER1_CMP0 0x40cd 11262f33ac92fSHawking Zhang #define regGFX_IMU_TIMER1_CMP0_BASE_IDX 1 11263f33ac92fSHawking Zhang #define regGFX_IMU_TIMER1_CMP1 0x40ce 11264f33ac92fSHawking Zhang #define regGFX_IMU_TIMER1_CMP1_BASE_IDX 1 11265f33ac92fSHawking Zhang #define regGFX_IMU_TIMER1_CMP3 0x40d0 11266f33ac92fSHawking Zhang #define regGFX_IMU_TIMER1_CMP3_BASE_IDX 1 11267f33ac92fSHawking Zhang #define regGFX_IMU_TIMER1_VALUE 0x40d1 11268f33ac92fSHawking Zhang #define regGFX_IMU_TIMER1_VALUE_BASE_IDX 1 11269f33ac92fSHawking Zhang #define regGFX_IMU_TIMER2_CTRL0 0x40d2 11270f33ac92fSHawking Zhang #define regGFX_IMU_TIMER2_CTRL0_BASE_IDX 1 11271f33ac92fSHawking Zhang #define regGFX_IMU_TIMER2_CTRL1 0x40d3 11272f33ac92fSHawking Zhang #define regGFX_IMU_TIMER2_CTRL1_BASE_IDX 1 11273f33ac92fSHawking Zhang #define regGFX_IMU_TIMER2_CMP_AUTOINC 0x40d4 11274f33ac92fSHawking Zhang #define regGFX_IMU_TIMER2_CMP_AUTOINC_BASE_IDX 1 11275f33ac92fSHawking Zhang #define regGFX_IMU_TIMER2_CMP_INTEN 0x40d5 11276f33ac92fSHawking Zhang #define regGFX_IMU_TIMER2_CMP_INTEN_BASE_IDX 1 11277f33ac92fSHawking Zhang #define regGFX_IMU_TIMER2_CMP0 0x40d6 11278f33ac92fSHawking Zhang #define regGFX_IMU_TIMER2_CMP0_BASE_IDX 1 11279f33ac92fSHawking Zhang #define regGFX_IMU_TIMER2_CMP1 0x40d7 11280f33ac92fSHawking Zhang #define regGFX_IMU_TIMER2_CMP1_BASE_IDX 1 11281f33ac92fSHawking Zhang #define regGFX_IMU_TIMER2_CMP3 0x40d9 11282f33ac92fSHawking Zhang #define regGFX_IMU_TIMER2_CMP3_BASE_IDX 1 11283f33ac92fSHawking Zhang #define regGFX_IMU_TIMER2_VALUE 0x40da 11284f33ac92fSHawking Zhang #define regGFX_IMU_TIMER2_VALUE_BASE_IDX 1 11285f33ac92fSHawking Zhang #define regGFX_IMU_FUSE_CTRL 0x40e0 11286f33ac92fSHawking Zhang #define regGFX_IMU_FUSE_CTRL_BASE_IDX 1 11287f33ac92fSHawking Zhang #define regGFX_IMU_D_RAM_ADDR 0x40fc 11288f33ac92fSHawking Zhang #define regGFX_IMU_D_RAM_ADDR_BASE_IDX 1 11289f33ac92fSHawking Zhang #define regGFX_IMU_D_RAM_DATA 0x40fd 11290f33ac92fSHawking Zhang #define regGFX_IMU_D_RAM_DATA_BASE_IDX 1 11291f33ac92fSHawking Zhang #define regGFX_IMU_GFX_IH_GASKET_CTRL 0x40ff 11292f33ac92fSHawking Zhang #define regGFX_IMU_GFX_IH_GASKET_CTRL_BASE_IDX 1 11293f33ac92fSHawking Zhang 11294f33ac92fSHawking Zhang 11295f33ac92fSHawking Zhang // addressBlock: gc_gfx_imu_gfx_imu_pspdec 11296f33ac92fSHawking Zhang // base address: 0x3fe00 11297f33ac92fSHawking Zhang #define regGFX_IMU_RLC_BOOTLOADER_ADDR_HI 0x5f81 11298f33ac92fSHawking Zhang #define regGFX_IMU_RLC_BOOTLOADER_ADDR_HI_BASE_IDX 1 11299f33ac92fSHawking Zhang #define regGFX_IMU_RLC_BOOTLOADER_ADDR_LO 0x5f82 11300f33ac92fSHawking Zhang #define regGFX_IMU_RLC_BOOTLOADER_ADDR_LO_BASE_IDX 1 11301f33ac92fSHawking Zhang #define regGFX_IMU_RLC_BOOTLOADER_SIZE 0x5f83 11302f33ac92fSHawking Zhang #define regGFX_IMU_RLC_BOOTLOADER_SIZE_BASE_IDX 1 11303f33ac92fSHawking Zhang #define regGFX_IMU_I_RAM_ADDR 0x5f90 11304f33ac92fSHawking Zhang #define regGFX_IMU_I_RAM_ADDR_BASE_IDX 1 11305f33ac92fSHawking Zhang #define regGFX_IMU_I_RAM_DATA 0x5f91 11306f33ac92fSHawking Zhang #define regGFX_IMU_I_RAM_DATA_BASE_IDX 1 11307f33ac92fSHawking Zhang 11308f33ac92fSHawking Zhang 11309f33ac92fSHawking Zhang // addressBlock: gccacind 11310f33ac92fSHawking Zhang // base address: 0x0 11311f33ac92fSHawking Zhang #define ixGC_CAC_ID 0x0000 11312f33ac92fSHawking Zhang #define ixGC_CAC_CNTL 0x0001 11313f33ac92fSHawking Zhang #define ixGC_CAC_ACC_CP0 0x0010 11314f33ac92fSHawking Zhang #define ixGC_CAC_ACC_CP1 0x0011 11315f33ac92fSHawking Zhang #define ixGC_CAC_ACC_CP2 0x0012 11316f33ac92fSHawking Zhang #define ixGC_CAC_ACC_EA0 0x0013 11317f33ac92fSHawking Zhang #define ixGC_CAC_ACC_EA1 0x0014 11318f33ac92fSHawking Zhang #define ixGC_CAC_ACC_EA2 0x0015 11319f33ac92fSHawking Zhang #define ixGC_CAC_ACC_EA3 0x0016 11320f33ac92fSHawking Zhang #define ixGC_CAC_ACC_EA4 0x0017 11321f33ac92fSHawking Zhang #define ixGC_CAC_ACC_EA5 0x0018 11322f33ac92fSHawking Zhang #define ixGC_CAC_ACC_UTCL2_ROUTER0 0x0019 11323f33ac92fSHawking Zhang #define ixGC_CAC_ACC_UTCL2_ROUTER1 0x001a 11324f33ac92fSHawking Zhang #define ixGC_CAC_ACC_UTCL2_ROUTER2 0x001b 11325f33ac92fSHawking Zhang #define ixGC_CAC_ACC_UTCL2_ROUTER3 0x001c 11326f33ac92fSHawking Zhang #define ixGC_CAC_ACC_UTCL2_ROUTER4 0x001d 11327f33ac92fSHawking Zhang #define ixGC_CAC_ACC_UTCL2_ROUTER5 0x001e 11328f33ac92fSHawking Zhang #define ixGC_CAC_ACC_UTCL2_ROUTER6 0x001f 11329f33ac92fSHawking Zhang #define ixGC_CAC_ACC_UTCL2_ROUTER7 0x0020 11330f33ac92fSHawking Zhang #define ixGC_CAC_ACC_UTCL2_ROUTER8 0x0021 11331f33ac92fSHawking Zhang #define ixGC_CAC_ACC_UTCL2_ROUTER9 0x0022 11332f33ac92fSHawking Zhang #define ixGC_CAC_ACC_UTCL2_VML20 0x0023 11333f33ac92fSHawking Zhang #define ixGC_CAC_ACC_UTCL2_VML21 0x0024 11334f33ac92fSHawking Zhang #define ixGC_CAC_ACC_UTCL2_VML22 0x0025 11335f33ac92fSHawking Zhang #define ixGC_CAC_ACC_UTCL2_VML23 0x0026 11336f33ac92fSHawking Zhang #define ixGC_CAC_ACC_UTCL2_VML24 0x0027 11337f33ac92fSHawking Zhang #define ixGC_CAC_ACC_UTCL2_WALKER0 0x0028 11338f33ac92fSHawking Zhang #define ixGC_CAC_ACC_UTCL2_WALKER1 0x0029 11339f33ac92fSHawking Zhang #define ixGC_CAC_ACC_UTCL2_WALKER2 0x002a 11340f33ac92fSHawking Zhang #define ixGC_CAC_ACC_UTCL2_WALKER3 0x002b 11341f33ac92fSHawking Zhang #define ixGC_CAC_ACC_UTCL2_WALKER4 0x002c 11342f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GDS0 0x002d 11343f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GDS1 0x002e 11344f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GDS2 0x002f 11345f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GDS3 0x0030 11346f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GDS4 0x0031 11347f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GE0 0x0032 11348f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GE1 0x0033 11349f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GE2 0x0034 11350f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GE3 0x0035 11351f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GE4 0x0036 11352f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GE5 0x0037 11353f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GE6 0x0038 11354f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GE7 0x0039 11355f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GE8 0x003a 11356f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GE9 0x003b 11357f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GE10 0x003c 11358f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GE11 0x003d 11359f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GE12 0x003e 11360f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GE13 0x003f 11361f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GE14 0x0040 11362f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GE15 0x0041 11363f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GE16 0x0042 11364f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GE17 0x0043 11365f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GE18 0x0044 11366f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GE19 0x0045 11367f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GE20 0x0046 11368f33ac92fSHawking Zhang #define ixGC_CAC_ACC_PMM0 0x0047 11369f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GL2C0 0x0048 11370f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GL2C1 0x0049 11371f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GL2C2 0x004a 11372f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GL2C3 0x004b 11373f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GL2C4 0x004c 11374f33ac92fSHawking Zhang #define ixGC_CAC_ACC_PH0 0x004d 11375f33ac92fSHawking Zhang #define ixGC_CAC_ACC_PH1 0x004e 11376f33ac92fSHawking Zhang #define ixGC_CAC_ACC_PH2 0x004f 11377f33ac92fSHawking Zhang #define ixGC_CAC_ACC_PH3 0x0050 11378f33ac92fSHawking Zhang #define ixGC_CAC_ACC_PH4 0x0051 11379f33ac92fSHawking Zhang #define ixGC_CAC_ACC_PH5 0x0052 11380f33ac92fSHawking Zhang #define ixGC_CAC_ACC_PH6 0x0053 11381f33ac92fSHawking Zhang #define ixGC_CAC_ACC_PH7 0x0054 11382f33ac92fSHawking Zhang #define ixGC_CAC_ACC_SDMA0 0x0055 11383f33ac92fSHawking Zhang #define ixGC_CAC_ACC_SDMA1 0x0056 11384f33ac92fSHawking Zhang #define ixGC_CAC_ACC_SDMA2 0x0057 11385f33ac92fSHawking Zhang #define ixGC_CAC_ACC_SDMA3 0x0058 11386f33ac92fSHawking Zhang #define ixGC_CAC_ACC_SDMA4 0x0059 11387f33ac92fSHawking Zhang #define ixGC_CAC_ACC_SDMA5 0x005a 11388f33ac92fSHawking Zhang #define ixGC_CAC_ACC_SDMA6 0x005b 11389f33ac92fSHawking Zhang #define ixGC_CAC_ACC_SDMA7 0x005c 11390f33ac92fSHawking Zhang #define ixGC_CAC_ACC_SDMA8 0x005d 11391f33ac92fSHawking Zhang #define ixGC_CAC_ACC_SDMA9 0x005e 11392f33ac92fSHawking Zhang #define ixGC_CAC_ACC_SDMA10 0x005f 11393f33ac92fSHawking Zhang #define ixGC_CAC_ACC_SDMA11 0x0060 11394f33ac92fSHawking Zhang #define ixGC_CAC_ACC_CHC0 0x0061 11395f33ac92fSHawking Zhang #define ixGC_CAC_ACC_CHC1 0x0062 11396f33ac92fSHawking Zhang #define ixGC_CAC_ACC_CHC2 0x0063 11397f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GUS0 0x0064 11398f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GUS1 0x0065 11399f33ac92fSHawking Zhang #define ixGC_CAC_ACC_GUS2 0x0066 11400f33ac92fSHawking Zhang #define ixGC_CAC_ACC_RLC0 0x0067 11401f33ac92fSHawking Zhang #define ixRELEASE_TO_STALL_LUT_1_8 0x0100 11402f33ac92fSHawking Zhang #define ixRELEASE_TO_STALL_LUT_9_16 0x0101 11403f33ac92fSHawking Zhang #define ixRELEASE_TO_STALL_LUT_17_20 0x0102 11404f33ac92fSHawking Zhang #define ixSTALL_TO_RELEASE_LUT_1_4 0x0103 11405f33ac92fSHawking Zhang #define ixSTALL_TO_RELEASE_LUT_5_7 0x0104 11406f33ac92fSHawking Zhang #define ixSTALL_TO_PWRBRK_LUT_1_4 0x0105 11407f33ac92fSHawking Zhang #define ixSTALL_TO_PWRBRK_LUT_5_7 0x0106 11408f33ac92fSHawking Zhang #define ixPWRBRK_STALL_TO_RELEASE_LUT_1_4 0x0107 11409f33ac92fSHawking Zhang #define ixPWRBRK_STALL_TO_RELEASE_LUT_5_7 0x0108 11410f33ac92fSHawking Zhang #define ixPWRBRK_RELEASE_TO_STALL_LUT_1_8 0x0109 11411f33ac92fSHawking Zhang #define ixPWRBRK_RELEASE_TO_STALL_LUT_9_16 0x010a 11412f33ac92fSHawking Zhang #define ixPWRBRK_RELEASE_TO_STALL_LUT_17_20 0x010b 11413f33ac92fSHawking Zhang #define ixFIXED_PATTERN_PERF_COUNTER_1 0x010c 11414f33ac92fSHawking Zhang #define ixFIXED_PATTERN_PERF_COUNTER_2 0x010d 11415f33ac92fSHawking Zhang #define ixFIXED_PATTERN_PERF_COUNTER_3 0x010e 11416f33ac92fSHawking Zhang #define ixFIXED_PATTERN_PERF_COUNTER_4 0x010f 11417f33ac92fSHawking Zhang #define ixFIXED_PATTERN_PERF_COUNTER_5 0x0110 11418f33ac92fSHawking Zhang #define ixFIXED_PATTERN_PERF_COUNTER_6 0x0111 11419f33ac92fSHawking Zhang #define ixFIXED_PATTERN_PERF_COUNTER_7 0x0112 11420f33ac92fSHawking Zhang #define ixFIXED_PATTERN_PERF_COUNTER_8 0x0113 11421f33ac92fSHawking Zhang #define ixFIXED_PATTERN_PERF_COUNTER_9 0x0114 11422f33ac92fSHawking Zhang #define ixFIXED_PATTERN_PERF_COUNTER_10 0x0115 11423f33ac92fSHawking Zhang #define ixHW_LUT_UPDATE_STATUS 0x0116 11424f33ac92fSHawking Zhang 11425f33ac92fSHawking Zhang 11426f33ac92fSHawking Zhang // addressBlock: secacind 11427f33ac92fSHawking Zhang // base address: 0x0 11428f33ac92fSHawking Zhang #define ixSE_CAC_ID 0x0000 11429f33ac92fSHawking Zhang #define ixSE_CAC_CNTL 0x0001 11430f33ac92fSHawking Zhang 11431f33ac92fSHawking Zhang 11432f33ac92fSHawking Zhang // addressBlock: grtavfsind 11433f33ac92fSHawking Zhang // base address: 0x0 11434f33ac92fSHawking Zhang #define ixRTAVFS_REG0 0x0000 11435f33ac92fSHawking Zhang #define ixRTAVFS_REG1 0x0001 11436f33ac92fSHawking Zhang #define ixRTAVFS_REG2 0x0002 11437f33ac92fSHawking Zhang #define ixRTAVFS_REG3 0x0003 11438f33ac92fSHawking Zhang #define ixRTAVFS_REG4 0x0004 11439f33ac92fSHawking Zhang #define ixRTAVFS_REG5 0x0005 11440f33ac92fSHawking Zhang #define ixRTAVFS_REG6 0x0006 11441f33ac92fSHawking Zhang #define ixRTAVFS_REG7 0x0007 11442f33ac92fSHawking Zhang #define ixRTAVFS_REG8 0x0008 11443f33ac92fSHawking Zhang #define ixRTAVFS_REG9 0x0009 11444f33ac92fSHawking Zhang #define ixRTAVFS_REG10 0x000a 11445f33ac92fSHawking Zhang #define ixRTAVFS_REG11 0x000b 11446f33ac92fSHawking Zhang #define ixRTAVFS_REG12 0x000c 11447f33ac92fSHawking Zhang #define ixRTAVFS_REG13 0x000d 11448f33ac92fSHawking Zhang #define ixRTAVFS_REG14 0x000e 11449f33ac92fSHawking Zhang #define ixRTAVFS_REG15 0x000f 11450f33ac92fSHawking Zhang #define ixRTAVFS_REG16 0x0010 11451f33ac92fSHawking Zhang #define ixRTAVFS_REG17 0x0011 11452f33ac92fSHawking Zhang #define ixRTAVFS_REG18 0x0012 11453f33ac92fSHawking Zhang #define ixRTAVFS_REG19 0x0013 11454f33ac92fSHawking Zhang #define ixRTAVFS_REG20 0x0014 11455f33ac92fSHawking Zhang #define ixRTAVFS_REG21 0x0015 11456f33ac92fSHawking Zhang #define ixRTAVFS_REG22 0x0016 11457f33ac92fSHawking Zhang #define ixRTAVFS_REG23 0x0017 11458f33ac92fSHawking Zhang #define ixRTAVFS_REG24 0x0018 11459f33ac92fSHawking Zhang #define ixRTAVFS_REG25 0x0019 11460f33ac92fSHawking Zhang #define ixRTAVFS_REG26 0x001a 11461f33ac92fSHawking Zhang #define ixRTAVFS_REG27 0x001b 11462f33ac92fSHawking Zhang #define ixRTAVFS_REG28 0x001c 11463f33ac92fSHawking Zhang #define ixRTAVFS_REG29 0x001d 11464f33ac92fSHawking Zhang #define ixRTAVFS_REG30 0x001e 11465f33ac92fSHawking Zhang #define ixRTAVFS_REG31 0x001f 11466f33ac92fSHawking Zhang #define ixRTAVFS_REG32 0x0020 11467f33ac92fSHawking Zhang #define ixRTAVFS_REG33 0x0021 11468f33ac92fSHawking Zhang #define ixRTAVFS_REG34 0x0022 11469f33ac92fSHawking Zhang #define ixRTAVFS_REG35 0x0023 11470f33ac92fSHawking Zhang #define ixRTAVFS_REG36 0x0024 11471f33ac92fSHawking Zhang #define ixRTAVFS_REG37 0x0025 11472f33ac92fSHawking Zhang #define ixRTAVFS_REG38 0x0026 11473f33ac92fSHawking Zhang #define ixRTAVFS_REG39 0x0027 11474f33ac92fSHawking Zhang #define ixRTAVFS_REG40 0x0028 11475f33ac92fSHawking Zhang #define ixRTAVFS_REG41 0x0029 11476f33ac92fSHawking Zhang #define ixRTAVFS_REG42 0x002a 11477f33ac92fSHawking Zhang #define ixRTAVFS_REG43 0x002b 11478f33ac92fSHawking Zhang #define ixRTAVFS_REG44 0x002c 11479f33ac92fSHawking Zhang #define ixRTAVFS_REG45 0x002d 11480f33ac92fSHawking Zhang #define ixRTAVFS_REG46 0x002e 11481f33ac92fSHawking Zhang #define ixRTAVFS_REG47 0x002f 11482f33ac92fSHawking Zhang #define ixRTAVFS_REG48 0x0030 11483f33ac92fSHawking Zhang #define ixRTAVFS_REG49 0x0031 11484f33ac92fSHawking Zhang #define ixRTAVFS_REG50 0x0032 11485f33ac92fSHawking Zhang #define ixRTAVFS_REG51 0x0033 11486f33ac92fSHawking Zhang #define ixRTAVFS_REG52 0x0034 11487f33ac92fSHawking Zhang #define ixRTAVFS_REG53 0x0035 11488f33ac92fSHawking Zhang #define ixRTAVFS_REG54 0x0036 11489f33ac92fSHawking Zhang #define ixRTAVFS_REG55 0x0037 11490f33ac92fSHawking Zhang #define ixRTAVFS_REG56 0x0038 11491f33ac92fSHawking Zhang #define ixRTAVFS_REG57 0x0039 11492f33ac92fSHawking Zhang #define ixRTAVFS_REG58 0x003a 11493f33ac92fSHawking Zhang #define ixRTAVFS_REG59 0x003b 11494f33ac92fSHawking Zhang #define ixRTAVFS_REG60 0x003c 11495f33ac92fSHawking Zhang #define ixRTAVFS_REG61 0x003d 11496f33ac92fSHawking Zhang #define ixRTAVFS_REG62 0x003e 11497f33ac92fSHawking Zhang #define ixRTAVFS_REG63 0x003f 11498f33ac92fSHawking Zhang #define ixRTAVFS_REG64 0x0040 11499f33ac92fSHawking Zhang #define ixRTAVFS_REG65 0x0041 11500f33ac92fSHawking Zhang #define ixRTAVFS_REG66 0x0042 11501f33ac92fSHawking Zhang #define ixRTAVFS_REG67 0x0043 11502f33ac92fSHawking Zhang #define ixRTAVFS_REG68 0x0044 11503f33ac92fSHawking Zhang #define ixRTAVFS_REG69 0x0045 11504f33ac92fSHawking Zhang #define ixRTAVFS_REG70 0x0046 11505f33ac92fSHawking Zhang #define ixRTAVFS_REG71 0x0047 11506f33ac92fSHawking Zhang #define ixRTAVFS_REG72 0x0048 11507f33ac92fSHawking Zhang #define ixRTAVFS_REG73 0x0049 11508f33ac92fSHawking Zhang #define ixRTAVFS_REG74 0x004a 11509f33ac92fSHawking Zhang #define ixRTAVFS_REG75 0x004b 11510f33ac92fSHawking Zhang #define ixRTAVFS_REG76 0x004c 11511f33ac92fSHawking Zhang #define ixRTAVFS_REG77 0x004d 11512f33ac92fSHawking Zhang #define ixRTAVFS_REG78 0x004e 11513f33ac92fSHawking Zhang #define ixRTAVFS_REG79 0x004f 11514f33ac92fSHawking Zhang #define ixRTAVFS_REG80 0x0050 11515f33ac92fSHawking Zhang #define ixRTAVFS_REG81 0x0051 11516f33ac92fSHawking Zhang #define ixRTAVFS_REG82 0x0052 11517f33ac92fSHawking Zhang #define ixRTAVFS_REG83 0x0053 11518f33ac92fSHawking Zhang #define ixRTAVFS_REG84 0x0054 11519f33ac92fSHawking Zhang #define ixRTAVFS_REG85 0x0055 11520f33ac92fSHawking Zhang #define ixRTAVFS_REG86 0x0056 11521f33ac92fSHawking Zhang #define ixRTAVFS_REG87 0x0057 11522f33ac92fSHawking Zhang #define ixRTAVFS_REG88 0x0058 11523f33ac92fSHawking Zhang #define ixRTAVFS_REG89 0x0059 11524f33ac92fSHawking Zhang #define ixRTAVFS_REG90 0x005a 11525f33ac92fSHawking Zhang #define ixRTAVFS_REG91 0x005b 11526f33ac92fSHawking Zhang #define ixRTAVFS_REG92 0x005c 11527f33ac92fSHawking Zhang #define ixRTAVFS_REG93 0x005d 11528f33ac92fSHawking Zhang #define ixRTAVFS_REG94 0x005e 11529f33ac92fSHawking Zhang #define ixRTAVFS_REG95 0x005f 11530f33ac92fSHawking Zhang #define ixRTAVFS_REG96 0x0060 11531f33ac92fSHawking Zhang #define ixRTAVFS_REG97 0x0061 11532f33ac92fSHawking Zhang #define ixRTAVFS_REG98 0x0062 11533f33ac92fSHawking Zhang #define ixRTAVFS_REG99 0x0063 11534f33ac92fSHawking Zhang #define ixRTAVFS_REG100 0x0064 11535f33ac92fSHawking Zhang #define ixRTAVFS_REG101 0x0065 11536f33ac92fSHawking Zhang #define ixRTAVFS_REG102 0x0066 11537f33ac92fSHawking Zhang #define ixRTAVFS_REG103 0x0067 11538f33ac92fSHawking Zhang #define ixRTAVFS_REG104 0x0068 11539f33ac92fSHawking Zhang #define ixRTAVFS_REG105 0x0069 11540f33ac92fSHawking Zhang #define ixRTAVFS_REG106 0x006a 11541f33ac92fSHawking Zhang #define ixRTAVFS_REG107 0x006b 11542f33ac92fSHawking Zhang #define ixRTAVFS_REG108 0x006c 11543f33ac92fSHawking Zhang #define ixRTAVFS_REG109 0x006d 11544f33ac92fSHawking Zhang #define ixRTAVFS_REG110 0x006e 11545f33ac92fSHawking Zhang #define ixRTAVFS_REG111 0x006f 11546f33ac92fSHawking Zhang #define ixRTAVFS_REG112 0x0070 11547f33ac92fSHawking Zhang #define ixRTAVFS_REG113 0x0071 11548f33ac92fSHawking Zhang #define ixRTAVFS_REG114 0x0072 11549f33ac92fSHawking Zhang #define ixRTAVFS_REG115 0x0073 11550f33ac92fSHawking Zhang #define ixRTAVFS_REG116 0x0074 11551f33ac92fSHawking Zhang #define ixRTAVFS_REG117 0x0075 11552f33ac92fSHawking Zhang #define ixRTAVFS_REG118 0x0076 11553f33ac92fSHawking Zhang #define ixRTAVFS_REG119 0x0077 11554f33ac92fSHawking Zhang #define ixRTAVFS_REG120 0x0078 11555f33ac92fSHawking Zhang #define ixRTAVFS_REG121 0x0079 11556f33ac92fSHawking Zhang #define ixRTAVFS_REG122 0x007a 11557f33ac92fSHawking Zhang #define ixRTAVFS_REG123 0x007b 11558f33ac92fSHawking Zhang #define ixRTAVFS_REG124 0x007c 11559f33ac92fSHawking Zhang #define ixRTAVFS_REG125 0x007d 11560f33ac92fSHawking Zhang #define ixRTAVFS_REG126 0x007e 11561f33ac92fSHawking Zhang #define ixRTAVFS_REG127 0x007f 11562f33ac92fSHawking Zhang #define ixRTAVFS_REG128 0x0080 11563f33ac92fSHawking Zhang #define ixRTAVFS_REG129 0x0081 11564f33ac92fSHawking Zhang #define ixRTAVFS_REG130 0x0082 11565f33ac92fSHawking Zhang #define ixRTAVFS_REG131 0x0083 11566f33ac92fSHawking Zhang #define ixRTAVFS_REG132 0x0084 11567f33ac92fSHawking Zhang #define ixRTAVFS_REG133 0x0085 11568f33ac92fSHawking Zhang #define ixRTAVFS_REG134 0x0086 11569f33ac92fSHawking Zhang #define ixRTAVFS_REG135 0x0087 11570f33ac92fSHawking Zhang #define ixRTAVFS_REG136 0x0088 11571f33ac92fSHawking Zhang #define ixRTAVFS_REG137 0x0089 11572f33ac92fSHawking Zhang #define ixRTAVFS_REG138 0x008a 11573f33ac92fSHawking Zhang #define ixRTAVFS_REG139 0x008b 11574f33ac92fSHawking Zhang #define ixRTAVFS_REG140 0x008c 11575f33ac92fSHawking Zhang #define ixRTAVFS_REG141 0x008d 11576f33ac92fSHawking Zhang #define ixRTAVFS_REG142 0x008e 11577f33ac92fSHawking Zhang #define ixRTAVFS_REG143 0x008f 11578f33ac92fSHawking Zhang #define ixRTAVFS_REG144 0x0090 11579f33ac92fSHawking Zhang #define ixRTAVFS_REG145 0x0091 11580f33ac92fSHawking Zhang #define ixRTAVFS_REG146 0x0092 11581f33ac92fSHawking Zhang #define ixRTAVFS_REG147 0x0093 11582f33ac92fSHawking Zhang #define ixRTAVFS_REG148 0x0094 11583f33ac92fSHawking Zhang #define ixRTAVFS_REG149 0x0095 11584f33ac92fSHawking Zhang #define ixRTAVFS_REG150 0x0096 11585f33ac92fSHawking Zhang #define ixRTAVFS_REG151 0x0097 11586f33ac92fSHawking Zhang #define ixRTAVFS_REG152 0x0098 11587f33ac92fSHawking Zhang #define ixRTAVFS_REG153 0x0099 11588f33ac92fSHawking Zhang #define ixRTAVFS_REG154 0x009a 11589f33ac92fSHawking Zhang #define ixRTAVFS_REG155 0x009b 11590f33ac92fSHawking Zhang #define ixRTAVFS_REG156 0x009c 11591f33ac92fSHawking Zhang #define ixRTAVFS_REG157 0x009d 11592f33ac92fSHawking Zhang #define ixRTAVFS_REG158 0x009e 11593f33ac92fSHawking Zhang #define ixRTAVFS_REG159 0x009f 11594f33ac92fSHawking Zhang #define ixRTAVFS_REG160 0x00a0 11595f33ac92fSHawking Zhang #define ixRTAVFS_REG161 0x00a1 11596f33ac92fSHawking Zhang #define ixRTAVFS_REG162 0x00a2 11597f33ac92fSHawking Zhang #define ixRTAVFS_REG163 0x00a3 11598f33ac92fSHawking Zhang #define ixRTAVFS_REG164 0x00a4 11599f33ac92fSHawking Zhang #define ixRTAVFS_REG165 0x00a5 11600f33ac92fSHawking Zhang #define ixRTAVFS_REG166 0x00a6 11601f33ac92fSHawking Zhang #define ixRTAVFS_REG167 0x00a7 11602f33ac92fSHawking Zhang #define ixRTAVFS_REG168 0x00a8 11603f33ac92fSHawking Zhang #define ixRTAVFS_REG169 0x00a9 11604f33ac92fSHawking Zhang #define ixRTAVFS_REG170 0x00aa 11605f33ac92fSHawking Zhang #define ixRTAVFS_REG171 0x00ab 11606f33ac92fSHawking Zhang #define ixRTAVFS_REG172 0x00ac 11607f33ac92fSHawking Zhang #define ixRTAVFS_REG173 0x00ad 11608f33ac92fSHawking Zhang #define ixRTAVFS_REG174 0x00ae 11609f33ac92fSHawking Zhang #define ixRTAVFS_REG175 0x00af 11610f33ac92fSHawking Zhang #define ixRTAVFS_REG176 0x00b0 11611f33ac92fSHawking Zhang #define ixRTAVFS_REG177 0x00b1 11612f33ac92fSHawking Zhang #define ixRTAVFS_REG178 0x00b2 11613f33ac92fSHawking Zhang #define ixRTAVFS_REG179 0x00b3 11614f33ac92fSHawking Zhang #define ixRTAVFS_REG180 0x00b4 11615f33ac92fSHawking Zhang #define ixRTAVFS_REG181 0x00b5 11616f33ac92fSHawking Zhang #define ixRTAVFS_REG182 0x00b6 11617f33ac92fSHawking Zhang #define ixRTAVFS_REG183 0x00b7 11618f33ac92fSHawking Zhang #define ixRTAVFS_REG184 0x00b8 11619f33ac92fSHawking Zhang #define ixRTAVFS_REG185 0x00b9 11620f33ac92fSHawking Zhang #define ixRTAVFS_REG186 0x00ba 11621f33ac92fSHawking Zhang #define ixRTAVFS_REG187 0x00bb 11622f33ac92fSHawking Zhang #define ixRTAVFS_REG188 0x00bc 11623f33ac92fSHawking Zhang #define ixRTAVFS_REG189 0x00bd 11624f33ac92fSHawking Zhang #define ixRTAVFS_REG190 0x00be 11625f33ac92fSHawking Zhang #define ixRTAVFS_REG191 0x00bf 11626f33ac92fSHawking Zhang #define ixRTAVFS_REG192 0x00c0 11627f33ac92fSHawking Zhang #define ixRTAVFS_REG193 0x00c1 11628f33ac92fSHawking Zhang #define ixRTAVFS_REG194 0x00c2 11629f33ac92fSHawking Zhang 11630f33ac92fSHawking Zhang 11631f33ac92fSHawking Zhang // addressBlock: sqind 11632f33ac92fSHawking Zhang // base address: 0x0 11633f33ac92fSHawking Zhang #define ixSQ_DEBUG_STS_LOCAL 0x0008 11634f33ac92fSHawking Zhang #define ixSQ_DEBUG_CTRL_LOCAL 0x0009 11635f33ac92fSHawking Zhang #define ixSQ_WAVE_ACTIVE 0x000a 11636f33ac92fSHawking Zhang #define ixSQ_WAVE_VALID_AND_IDLE 0x000b 11637f33ac92fSHawking Zhang #define ixSQ_WAVE_MODE 0x0101 11638f33ac92fSHawking Zhang #define ixSQ_WAVE_STATUS 0x0102 11639f33ac92fSHawking Zhang #define ixSQ_WAVE_TRAPSTS 0x0103 11640f33ac92fSHawking Zhang #define ixSQ_WAVE_GPR_ALLOC 0x0105 11641f33ac92fSHawking Zhang #define ixSQ_WAVE_LDS_ALLOC 0x0106 11642f33ac92fSHawking Zhang #define ixSQ_WAVE_IB_STS 0x0107 11643f33ac92fSHawking Zhang #define ixSQ_WAVE_PC_LO 0x0108 11644f33ac92fSHawking Zhang #define ixSQ_WAVE_PC_HI 0x0109 11645f33ac92fSHawking Zhang #define ixSQ_WAVE_IB_DBG1 0x010d 11646f33ac92fSHawking Zhang #define ixSQ_WAVE_FLUSH_IB 0x010e 11647f33ac92fSHawking Zhang #define ixSQ_WAVE_FLAT_SCRATCH_LO 0x0114 11648f33ac92fSHawking Zhang #define ixSQ_WAVE_FLAT_SCRATCH_HI 0x0115 11649f33ac92fSHawking Zhang #define ixSQ_WAVE_HW_ID1 0x0117 11650f33ac92fSHawking Zhang #define ixSQ_WAVE_HW_ID2 0x0118 11651f33ac92fSHawking Zhang #define ixSQ_WAVE_POPS_PACKER 0x0119 11652f33ac92fSHawking Zhang #define ixSQ_WAVE_SCHED_MODE 0x011a 11653f33ac92fSHawking Zhang #define ixSQ_WAVE_IB_STS2 0x011c 11654f33ac92fSHawking Zhang #define ixSQ_WAVE_SHADER_CYCLES 0x011d 11655f33ac92fSHawking Zhang #define ixSQ_WAVE_TTMP0 0x026c 11656f33ac92fSHawking Zhang #define ixSQ_WAVE_TTMP1 0x026d 11657f33ac92fSHawking Zhang #define ixSQ_WAVE_TTMP3 0x026f 11658f33ac92fSHawking Zhang #define ixSQ_WAVE_TTMP4 0x0270 11659f33ac92fSHawking Zhang #define ixSQ_WAVE_TTMP5 0x0271 11660f33ac92fSHawking Zhang #define ixSQ_WAVE_TTMP6 0x0272 11661f33ac92fSHawking Zhang #define ixSQ_WAVE_TTMP7 0x0273 11662f33ac92fSHawking Zhang #define ixSQ_WAVE_TTMP8 0x0274 11663f33ac92fSHawking Zhang #define ixSQ_WAVE_TTMP9 0x0275 11664f33ac92fSHawking Zhang #define ixSQ_WAVE_TTMP10 0x0276 11665f33ac92fSHawking Zhang #define ixSQ_WAVE_TTMP11 0x0277 11666f33ac92fSHawking Zhang #define ixSQ_WAVE_TTMP12 0x0278 11667f33ac92fSHawking Zhang #define ixSQ_WAVE_TTMP13 0x0279 11668f33ac92fSHawking Zhang #define ixSQ_WAVE_TTMP14 0x027a 11669f33ac92fSHawking Zhang #define ixSQ_WAVE_TTMP15 0x027b 11670f33ac92fSHawking Zhang #define ixSQ_WAVE_M0 0x027d 11671f33ac92fSHawking Zhang #define ixSQ_WAVE_EXEC_LO 0x027e 11672f33ac92fSHawking Zhang #define ixSQ_WAVE_EXEC_HI 0x027f 11673f33ac92fSHawking Zhang 11674f33ac92fSHawking Zhang 11675f33ac92fSHawking Zhang #endif 11676