Searched refs:regGCVM_L2_CNTL3 (Results 1 – 6 of 6) sorted by relevance
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | imu_v11_0.c | 221 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL3, 0x00100003, 0xe0000000), 304 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL3, 0x00100003, 0xe0000000),
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H A D | gfxhub_v3_0_3.c | 249 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp); in gfxhub_v3_0_3_init_cache_regs() 394 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, 0); in gfxhub_v3_0_3_gart_disable()
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H A D | imu_v11_0_3.c | 85 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL3, 0x00100003, 0xe0000000),
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H A D | gfxhub_v3_0.c | 244 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp); in gfxhub_v3_0_init_cache_regs() 401 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, 0); in gfxhub_v3_0_gart_disable()
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
H A D | gc_11_0_3_offset.h | 2876 #define regGCVM_L2_CNTL3 … macro
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H A D | gc_11_0_0_offset.h | 2734 #define regGCVM_L2_CNTL3 … macro
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