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Searched refs:reg2 (Results 1 – 18 of 18) sorted by relevance

/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dnand_ecc.c68 uint8_t idx, reg1, reg2, reg3, tmp1, tmp2; in nand_calculate_ecc() local
72 reg1 = reg2 = reg3 = 0; in nand_calculate_ecc()
83 reg2 ^= ~((uint8_t) i); in nand_calculate_ecc()
89 tmp1 |= (reg2 & 0x80) >> 1; /* B7 -> B6 */ in nand_calculate_ecc()
91 tmp1 |= (reg2 & 0x40) >> 2; /* B6 -> B4 */ in nand_calculate_ecc()
93 tmp1 |= (reg2 & 0x20) >> 3; /* B5 -> B2 */ in nand_calculate_ecc()
95 tmp1 |= (reg2 & 0x10) >> 4; /* B4 -> B0 */ in nand_calculate_ecc()
98 tmp2 |= (reg2 & 0x08) << 3; /* B3 -> B6 */ in nand_calculate_ecc()
100 tmp2 |= (reg2 & 0x04) << 2; /* B2 -> B4 */ in nand_calculate_ecc()
102 tmp2 |= (reg2 & 0x02) << 1; /* B1 -> B2 */ in nand_calculate_ecc()
[all …]
/openbmc/u-boot/post/lib_powerpc/
H A Dthreex.c127 unsigned int reg2 = (reg + 2) % 32; in cpu_post_test_threex() local
137 ASM_STW(reg2, stk, 0), in cpu_post_test_threex()
140 ASM_12X(test->cmd, reg2, reg1, reg0), in cpu_post_test_threex()
141 ASM_STW(reg2, stk, 12), in cpu_post_test_threex()
142 ASM_LWZ(reg2, stk, 0), in cpu_post_test_threex()
158 ASM_STW(reg2, stk, 0), in cpu_post_test_threex()
161 ASM_12X(test->cmd, reg2, reg1, reg0) | BIT_C, in cpu_post_test_threex()
162 ASM_STW(reg2, stk, 12), in cpu_post_test_threex()
163 ASM_LWZ(reg2, stk, 0), in cpu_post_test_threex()
H A Drlwnm.c62 unsigned int reg2 = (reg + 2) % 32; in cpu_post_test_rlwnm() local
72 ASM_STW(reg2, stk, 0), in cpu_post_test_rlwnm()
75 ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me), in cpu_post_test_rlwnm()
76 ASM_STW(reg2, stk, 12), in cpu_post_test_rlwnm()
77 ASM_LWZ(reg2, stk, 0), in cpu_post_test_rlwnm()
93 ASM_STW(reg2, stk, 0), in cpu_post_test_rlwnm()
96 ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me) | in cpu_post_test_rlwnm()
98 ASM_STW(reg2, stk, 12), in cpu_post_test_rlwnm()
99 ASM_LWZ(reg2, stk, 0), in cpu_post_test_rlwnm()
H A Dthree.c157 unsigned int reg2 = (reg + 2) % 32; in cpu_post_test_three() local
167 ASM_STW(reg2, stk, 0), in cpu_post_test_three()
170 ASM_12(test->cmd, reg2, reg1, reg0), in cpu_post_test_three()
171 ASM_STW(reg2, stk, 12), in cpu_post_test_three()
172 ASM_LWZ(reg2, stk, 0), in cpu_post_test_three()
188 ASM_STW(reg2, stk, 0), in cpu_post_test_three()
191 ASM_12(test->cmd, reg2, reg1, reg0) | BIT_C, in cpu_post_test_three()
192 ASM_STW(reg2, stk, 12), in cpu_post_test_three()
193 ASM_LWZ(reg2, stk, 0), in cpu_post_test_three()
/openbmc/u-boot/drivers/ddr/imx/imx8m/
H A Dddrphy_utils.c51 unsigned int reg, reg2; in get_stream_message() local
57 reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0034); in get_stream_message()
59 reg2 = (reg2 << 16) | reg; in get_stream_message()
63 return reg2; in get_stream_message()
/openbmc/u-boot/arch/arm/mach-imx/
H A Dsip.c10 unsigned long reg1, unsigned long reg2) in call_imx_sip() argument
17 regs.regs[3] = reg2; in call_imx_sip()
/openbmc/u-boot/arch/arm/lib/
H A Dmemcpy.S20 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
21 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
24 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
25 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
36 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
37 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
44 .macro enter reg1 reg2 argument
45 stmdb sp!, {r0, \reg1, \reg2}
48 .macro exit reg1 reg2 argument
49 ldmfd sp!, {r0, \reg1, \reg2}
/openbmc/qemu/hw/rtc/
H A Daspeed_rtc.c32 uint32_t reg2 = rtc->reg[COUNTER2]; in aspeed_rtc_calc_offset() local
39 cent = (reg2 >> 16) & 0x1f; in aspeed_rtc_calc_offset()
40 year = (reg2 >> 8) & 0x7f; in aspeed_rtc_calc_offset()
41 tm.tm_mon = ((reg2 >> 0) & 0x0f) - 1; in aspeed_rtc_calc_offset()
/openbmc/phosphor-power/phosphor-regulators/test/actions/
H A Dset_device_action_tests.cpp58 Device reg2{ in TEST() local
62 idMap.addDevice(reg2); in TEST()
/openbmc/u-boot/arch/arm/include/asm/mach-imx/
H A Dsys_proto.h136 unsigned long reg1, unsigned long reg2);
/openbmc/qemu/target/i386/tcg/
H A Dtranslate.c893 TCGv reg2; member
933 .reg2 = cpu_cc_src, .use_reg2 = true }; in gen_prepare_eflags_c()
941 .reg2 = cpu_cc_src, .use_reg2 = true }; in gen_prepare_eflags_c()
1090 .reg2 = cpu_cc_src, .use_reg2 = true }; in gen_prepare_cc()
1101 .reg2 = cpu_cc_src, .use_reg2 = true }; in gen_prepare_cc()
1198 tcg_gen_negsetcond_tl(cc.cond, reg, cc.reg, cc.reg2); in gen_neg_setcc()
1218 tcg_gen_setcond_tl(cc.cond, reg, cc.reg, cc.reg2); in gen_setcc()
1236 tcg_gen_brcond_tl(cc.cond, cc.reg, cc.reg2, l1); in gen_jcc_noeob()
1257 tcg_gen_brcond_tl(cc.cond, cc.reg, cc.reg2, l1); in gen_jcc()
2011 cc.reg2 = tcg_constant_tl(cc.imm); in gen_cmovcc()
[all …]
/openbmc/u-boot/drivers/spi/
H A Dfsl_qspi.c419 u32 reg, reg2; in qspi_enable_ddr_mode() local
427 reg2 = qspi_read32(priv->flags, &regs->smpr); in qspi_enable_ddr_mode()
428 reg2 &= ~QSPI_SMPR_DDRSMP_MASK; in qspi_enable_ddr_mode()
429 reg2 |= (2 << QSPI_SMPR_DDRSMP_SHIFT); in qspi_enable_ddr_mode()
430 qspi_write32(priv->flags, &regs->smpr, reg2); in qspi_enable_ddr_mode()
/openbmc/u-boot/include/
H A Dppc_asm.tmpl164 #define EXCEPTION_PROLOG(reg1, reg2) \
185 mfspr r23,reg2; \
/openbmc/qemu/target/s390x/
H A Dioinst.c733 void ioinst_handle_schm(S390CPU *cpu, uint64_t reg1, uint64_t reg2, in ioinst_handle_schm() argument
752 if (update && (reg2 & 0x000000000000001f)) { in ioinst_handle_schm()
757 css_do_schm(mbk, update, dct, update ? reg2 : 0); in ioinst_handle_schm()
H A Ds390x-internal.h366 void ioinst_handle_schm(S390CPU *cpu, uint64_t reg1, uint64_t reg2,
/openbmc/qemu/docs/devel/
H A Dqom.rst49 int reg0, reg1, reg2;
/openbmc/qemu/target/mips/tcg/
H A Dnanomips_translate.c.inc993 uint32_t reg1, uint32_t reg2)
1009 gen_store_gpr(tmp2, reg2);
1015 uint32_t reg1, uint32_t reg2, bool eva)
1033 gen_load_gpr(tmp2, reg2);
/openbmc/qemu/target/m68k/
H A Dtranslate.c3210 static void do_exg(TCGv reg1, TCGv reg2) in do_exg() argument
3214 tcg_gen_mov_i32(reg1, reg2); in do_exg()
3215 tcg_gen_mov_i32(reg2, temp); in do_exg()