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/openbmc/qemu/target/rx/
H A Dinsns.decode24 &rr rd rs
25 &ri rd imm
86 # ABS rd
88 # ABS rs, rd
93 # ADC rs, rd
434 # NEG rd
441 # NOT rd
463 # POP rd
491 # ROLC rd
493 # RORC rd
[all …]
H A Ddisas.c349 prt("pop\tr%d", a->rd); in trans_POP()
519 if (a->rs != a->rd) { in trans_NOT_rr()
531 if (a->rs != a->rd) { in trans_NEG_rr()
647 if (a->rs != a->rd) { in trans_ABS_rr()
773 if (a->rs2 != a->rd) { in trans_SHLL_irr()
792 if (a->rs2 != a->rd) { in trans_SHAR_irr()
811 if (a->rs2 != a->rd) { in trans_SHLR_irr()
829 prt("rorc\tr%d", a->rd); in trans_ROLC()
836 prt("rorc\tr%d", a->rd); in trans_RORC()
917 prt("bra.l\tr%d", a->rd); in trans_BRA_l()
[all …]
/openbmc/linux/arch/arm/net/
H A Dbpf_jit_32.h168 #define ARM_ADD_R(rd, rn, rm) _AL3_R(ARM_INST_ADD, rd, rn, rm) argument
172 #define ARM_ADC_R(rd, rn, rm) _AL3_R(ARM_INST_ADC, rd, rn, rm) argument
175 #define ARM_AND_R(rd, rn, rm) _AL3_R(ARM_INST_AND, rd, rn, rm) argument
179 #define ARM_BIC_R(rd, rn, rm) _AL3_R(ARM_INST_BIC, rd, rn, rm) argument
189 #define ARM_EOR_R(rd, rn, rm) _AL3_R(ARM_INST_EOR, rd, rn, rm) argument
217 #define ARM_MOV_R(rd, rm) _AL3_R(ARM_INST_MOV, rd, 0, rm) argument
218 #define ARM_MOVS_R(rd, rm) _AL3_R(ARM_INST_MOVS, rd, 0, rm) argument
219 #define ARM_MOV_I(rd, imm) _AL3_I(ARM_INST_MOV, rd, 0, imm) argument
236 #define ARM_ORR_R(rd, rn, rm) _AL3_R(ARM_INST_ORR, rd, rn, rm) argument
248 #define ARM_REV(rd, rm) (ARM_INST_REV | (rd) << 12 | (rm)) argument
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/openbmc/linux/arch/arm/include/debug/
H A Dsamsung.S14 ARM_BE8(rev \rd, \rd)
15 and \rd, \rd, #S5PV210_UFSTAT_TXMASK
20 ARM_BE8(rev \rd, \rd)
29 ARM_BE8(rev \rd, \rd)
30 and \rd, \rd, #S3C2440_UFSTAT_TXMASK
39 ARM_BE8(rev \rd, \rd)
53 ARM_BE8(rev \rd, \rd)
65 ARM_BE8(rev \rd, \rd)
77 ARM_BE8(rev \rd, \rd)
83 teq \rd, #0
[all …]
H A D8250.S16 ARM_BE8(rev \rd, \rd)
17 str \rd, \rx
18 ARM_BE8(rev \rd, \rd)
22 ldr \rd, \rx
23 ARM_BE8(rev \rd, \rd)
27 strb \rd, \rx
31 ldrb \rd, \rx
37 .macro senduart,rd,rx
41 .macro busyuart,rd,rx
43 and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
[all …]
H A Dmsm.S15 ARM_BE8(rev \rd, \rd )
17 str \rd, [\rx, #0x70]
25 ldr \rd, [\rx, #0x08]
26 ARM_BE8(rev \rd, \rd )
27 tst \rd, #0x08
31 ARM_BE8(rev \rd, \rd )
32 tst \rd, #0x80
36 mov \rd, #0x300
37 ARM_BE8(rev \rd, \rd )
40 mov \rd, #0x1
[all …]
H A Dicedcc.S15 .macro senduart, rd, rx
16 mcr p14, 0, \rd, c0, c5, 0
19 .macro busyuart, rd, rx
30 mov \rd, #0x2000000
32 subs \rd, \rd, #1
42 .macro senduart, rd, rx
46 .macro busyuart, rd, rx
57 mov \rd, #0x10000000
59 subs \rd, \rd, #1
85 mov \rd, #0x2000000
[all …]
/openbmc/linux/arch/riscv/net/
H A Dbpf_jit.h233 (rd << 7) | opcode; in rv_r_insn()
932 if (rvc_enabled() && rd && rd == rs1 && rs2) in emit_add()
945 else if (rvc_enabled() && rd && rd == rs && imm && is_6b_int(imm)) in emit_addi()
961 if (rvc_enabled() && rd && rd != RV_REG_SP && is_6b_int(imm) && imm) in emit_lui()
977 if (rvc_enabled() && is_creg(rd) && rd == rs && is_6b_int(imm)) in emit_andi()
1001 if (rvc_enabled() && is_creg(rd) && rd == rs1 && is_creg(rs2)) in emit_sub()
1009 if (rvc_enabled() && is_creg(rd) && rd == rs1 && is_creg(rs2)) in emit_or()
1017 if (rvc_enabled() && is_creg(rd) && rd == rs1 && is_creg(rs2)) in emit_and()
1025 if (rvc_enabled() && is_creg(rd) && rd == rs1 && is_creg(rs2)) in emit_xor()
1056 if (rvc_enabled() && rd && rd == rs && is_6b_int(imm)) in emit_addiw()
[all …]
H A Dbpf_jit_comp32.c118 emit(rv_addi(rd, rd, lower), ctx); in emit_imm()
265 emit(rv_ori(lo(rd), lo(rd), imm), ctx); in emit_alu_i64()
281 emit(rv_xori(hi(rd), hi(rd), -1), ctx); in emit_alu_i64()
312 emit(rv_srai(hi(rd), hi(rd), 31), ctx); in emit_alu_i64()
422 emit(rv_slli(hi(rd), hi(rd), 1), ctx); in emit_alu_r64()
424 emit(rv_slli(lo(rd), lo(rd), 1), ctx); in emit_alu_r64()
917 emit(rv_slli(rd, rd, 16), ctx); in emit_rev16()
919 emit(rv_srli(rd, rd, 8), ctx); in emit_rev16()
930 emit(rv_srli(rd, rd, 8), ctx); in emit_rev32()
934 emit(rv_srli(rd, rd, 8), ctx); in emit_rev32()
[all …]
H A Dbpf_jit_comp64.c205 emit_slli(rd, rd, shift, ctx); in emit_imm()
207 emit_addi(rd, rd, lower, ctx); in emit_imm()
1133 emit_or(rd, rd, rs, ctx); in bpf_jit_emit_insn()
1145 emit(is64 ? rv_mul(rd, rd, rs) : rv_mulw(rd, rd, rs), ctx); in bpf_jit_emit_insn()
1152 emit(is64 ? rv_div(rd, rd, rs) : rv_divw(rd, rd, rs), ctx); in bpf_jit_emit_insn()
1154 emit(is64 ? rv_divu(rd, rd, rs) : rv_divuw(rd, rd, rs), ctx); in bpf_jit_emit_insn()
1161 emit(is64 ? rv_rem(rd, rd, rs) : rv_remw(rd, rd, rs), ctx); in bpf_jit_emit_insn()
1163 emit(is64 ? rv_remu(rd, rd, rs) : rv_remuw(rd, rd, rs), ctx); in bpf_jit_emit_insn()
1169 emit(is64 ? rv_sll(rd, rd, rs) : rv_sllw(rd, rd, rs), ctx); in bpf_jit_emit_insn()
1175 emit(is64 ? rv_srl(rd, rd, rs) : rv_srlw(rd, rd, rs), ctx); in bpf_jit_emit_insn()
[all …]
/openbmc/u-boot/post/lib_powerpc/
H A Dcpu_asm.h184 #define ASM_STW(rd, rs, simm) ASM_11I(OP_STW, rd, rs, simm) argument
185 #define ASM_LWZ(rd, rs, simm) ASM_11I(OP_LWZ, rd, rs, simm) argument
186 #define ASM_MFCR(rd) ASM_1(OP_MFCR, rd) argument
187 #define ASM_MTCR(rd) ASM_1(OP_MTCR, rd) argument
188 #define ASM_MFXER(rd) ASM_1(OP_MFXER, rd) argument
189 #define ASM_MTXER(rd) ASM_1(OP_MTXER, rd) argument
190 #define ASM_MFCTR(rd) ASM_1(OP_MFCTR, rd) argument
191 #define ASM_MTCTR(rd) ASM_1(OP_MTCTR, rd) argument
196 #define ASM_MFLR(rd) ASM_1(OP_MFLR, rd) argument
197 #define ASM_MTLR(rd) ASM_1(OP_MTLR, rd) argument
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/openbmc/linux/drivers/gpu/drm/msm/
H A Dmsm_rd.c106 wait_event(rd->fifo_event, circ_space(&rd->fifo) > 0 || !rd->open); in rd_write()
107 if (!rd->open) in rd_write()
195 rd->fifo.head = rd->fifo.tail = 0; in rd_open()
237 if (!rd) in rd_cleanup()
242 kfree(rd); in rd_cleanup()
249 rd = kzalloc(sizeof(*rd), GFP_KERNEL); in rd_init()
250 if (!rd) in rd_init()
254 rd->fifo.buf = rd->buf; in rd_init()
264 return rd; in rd_init()
274 if (priv->rd) in msm_rd_debugfs_init()
[all …]
/openbmc/qemu/target/avr/
H A Ddisas.c135 INSN(ADIW, "r%d:r%d, %d", a->rd + 1, a->rd, a->imm)
140 INSN(SBIW, "r%d:r%d, %d", a->rd + 1, a->rd, a->imm)
146 INSN(COM, "r%d", a->rd)
147 INSN(NEG, "r%d", a->rd)
148 INSN(INC, "r%d", a->rd)
149 INSN(DEC, "r%d", a->rd)
186 INSN(MOVW, "r%d:r%d, r%d:r%d", a->rd + 1, a->rd, a->rr + 1, a->rr)
218 INSN(PUSH, "r%d", a->rd)
219 INSN(POP, "r%d", a->rd)
228 INSN(LSR, "r%d", a->rd)
[all …]
H A Dinsn.decode26 %rd 4:5
42 &rd_rr rd rr
43 &rd_imm rd imm
45 @op_rd_rr .... .. . ..... .... &rd_rr rd=%rd rr=%rr
66 COM 1001 010 rd:5 0000
67 NEG 1001 010 rd:5 0001
68 INC 1001 010 rd:5 0011
69 DEC 1001 010 rd:5 1010
118 @io_rd_imm .... . .. ..... .... &rd_imm rd=%rd imm=%io_imm
131 LDX1 1001 000 rd:5 1100
[all …]
/openbmc/linux/drivers/powercap/
H A Dintel_rapl_common.c605 rd++; in rapl_init_domains()
927 ra.reg.val, rd->rp->name, rd->name); in rapl_check_unit_core()
941 rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit); in rapl_check_unit_core()
955 ra.reg.val, rd->rp->name, rd->name); in rapl_check_unit_atom()
969 rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit); in rapl_check_unit_atom()
1142 ra.reg.val, rd->rp->name, rd->name); in rapl_check_unit_tpmi()
1156 rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit); in rapl_check_unit_tpmi()
1319 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) { in rapl_package_register_powercap()
1343 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) { in rapl_package_register_powercap()
1499 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) { in rapl_detect_domains()
[all …]
/openbmc/linux/kernel/time/
H A Dsched_clock.c93 cyc = (rd->read_sched_clock() - rd->epoch_cyc) & in sched_clock_noinstr()
95 res = rd->epoch_ns + cyc_to_ns(cyc, rd->mult, rd->shift); in sched_clock_noinstr()
123 cd.read_data[1] = *rd; in update_clock_read_data()
144 rd = cd.read_data[0]; in update_sched_clock()
147 ns = rd.epoch_ns + cyc_to_ns((cyc - rd.epoch_cyc) & rd.sched_clock_mask, rd.mult, rd.shift); in update_sched_clock()
149 rd.epoch_ns = ns; in update_sched_clock()
150 rd.epoch_cyc = cyc; in update_sched_clock()
188 rd = cd.read_data[0]; in sched_clock_register()
193 ns = rd.epoch_ns + cyc_to_ns((cyc - rd.epoch_cyc) & rd.sched_clock_mask, rd.mult, rd.shift); in sched_clock_register()
198 rd.mult = new_mult; in sched_clock_register()
[all …]
/openbmc/linux/fs/jffs2/
H A Dwrite.c231 je32_to_cpu(rd->pino), name, name, je32_to_cpu(rd->ino), in jffs2_write_dirent()
265 rd->node_crc = cpu_to_je32(crc32(0, rd, sizeof(*rd)-8)); in jffs2_write_dirent()
502 if (!rd) { in jffs2_do_create()
512 rd->totlen = cpu_to_je32(sizeof(*rd) + qstr->len); in jffs2_do_create()
521 rd->node_crc = cpu_to_je32(crc32(0, rd, sizeof(*rd)-8)); in jffs2_do_create()
560 if (!rd) in jffs2_do_unlink()
575 rd->totlen = cpu_to_je32(sizeof(*rd) + namelen); in jffs2_do_unlink()
584 rd->node_crc = cpu_to_je32(crc32(0, rd, sizeof(*rd)-8)); in jffs2_do_unlink()
677 if (!rd) in jffs2_do_link()
692 rd->totlen = cpu_to_je32(sizeof(*rd) + namelen); in jffs2_do_link()
[all …]
/openbmc/qemu/target/sparc/
H A Dinsns.decode21 SETHI 00 rd:5 100 i:22
29 &r_r_ri rd rs1 rs2_or_imm imm:bool
33 &r_r_ri_cc rd rs1 rs2_or_imm imm:bool cc:bool
38 &r_r_r rd rs1 rs2
42 &r_r rd rs
199 &shiftr rd rs1 rs2 x:bool
206 &shifti rd rs1 i x:bool
416 &r_r_ri_asi rd=%dfp_rd asi=-1
418 &r_r_ri_asi rd=%qfp_rd asi=-1
424 &r_r_ri_asi rd=%dfp_rd imm=0
[all …]
/openbmc/u-boot/arch/arm/include/debug/
H A D8250.S15 .macro store, rd, rx:vararg
16 str \rd, \rx
19 .macro load, rd, rx:vararg
20 ldr \rd, \rx
24 strb \rd, \rx
28 ldrb \rd, \rx
34 .macro senduart,rd,rx
38 .macro busyuart,rd,rx
40 and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
45 .macro waituart,rd,rx
[all …]
/openbmc/linux/arch/parisc/net/
H A Dbpf_jit_comp64.c151 emit(hppa_ldo(lower, rd, rd), ctx); in emit_imm32()
691 emit(hppa64_depdz_sar(rd, rd), ctx); in bpf_jit_emit_insn()
693 emit(hppa_depwz_sar(rd, rd), ctx); in bpf_jit_emit_insn()
701 emit(hppa64_shrpd_sar(rd, rd), ctx); in bpf_jit_emit_insn()
703 emit(hppa_shrpw_sar(rd, rd), ctx); in bpf_jit_emit_insn()
712 emit(hppa_extrd_sar(rd, rd, 1), ctx); in bpf_jit_emit_insn()
714 emit(hppa_extrws_sar(rd, rd), ctx); in bpf_jit_emit_insn()
782 emit(hppa_ldo(imm, rd, rd), ctx); in bpf_jit_emit_insn()
785 emit(hppa_add(rd, HPPA_REG_T1, rd), ctx); in bpf_jit_emit_insn()
793 emit(hppa_ldo(-imm, rd, rd), ctx); in bpf_jit_emit_insn()
[all …]
H A Dbpf_jit_comp32.c153 emit(hppa_ldo(lower, rd, rd), ctx); in emit_imm()
465 emit_hppa_copy(lo(rd), hi(rd), ctx); in emit_alu_i64()
468 emit(hppa_shd(hi(rd), lo(rd), 32 - imm, hi(rd)), ctx); in emit_alu_i64()
477 emit(hppa_shr(hi(rd), imm, lo(rd)), ctx); in emit_alu_i64()
480 emit_hppa_copy(hi(rd), lo(rd), ctx); in emit_alu_i64()
483 emit(hppa_shrpw(hi(rd), lo(rd), imm, lo(rd)), ctx); in emit_alu_i64()
484 emit(hppa_shr(hi(rd), imm, hi(rd)), ctx); in emit_alu_i64()
495 emit_hppa_copy(hi(rd), lo(rd), ctx); in emit_alu_i64()
498 emit(hppa_shrpw(hi(rd), lo(rd), imm, lo(rd)), ctx); in emit_alu_i64()
1280 emit_rev32(lo(rd), lo(rd), ctx); in bpf_jit_emit_insn()
[all …]
/openbmc/linux/arch/loongarch/net/
H A Dbpf_jit.h91 emit_insn(ctx, lu12iw, rd, imm_31_12); in move_addr()
95 emit_insn(ctx, ori, rd, rd, imm_11_0); in move_addr()
99 emit_insn(ctx, lu32id, rd, imm_51_32); in move_addr()
103 emit_insn(ctx, lu52id, rd, rd, imm_63_52); in move_addr()
138 emit_insn(ctx, lu12iw, rd, imm_31_12); in move_imm()
143 emit_insn(ctx, ori, rd, rd, imm_11_0); in move_imm()
156 emit_insn(ctx, lu32id, rd, imm_51_32); in move_imm()
162 emit_insn(ctx, lu52id, rd, rd, imm_63_52); in move_imm()
166 emit_zext_32(ctx, rd, is32); in move_imm()
209 emit_insn(ctx, beq, rj, rd, jmp_offset); in cond_jmp_offset()
[all …]
/openbmc/qemu/target/mips/tcg/
H A Dtx79_translate.c122 if (a->rd == 0) { in trans_parallel_arith()
239 if (a->rd == 0) { in trans_parallel_compare()
421 if (a->rd == 0) { in trans_PPACW()
452 if (a->rd == 0) { in trans_PEXTLx()
501 if (a->rd == 0) { in trans_PEXTLW()
511 gen_pextw(cpu_gpr[a->rd], cpu_gpr_hi[a->rd], ax, bx); in trans_PEXTLW()
520 if (a->rd == 0) { in trans_PEXTUW()
530 gen_pextw(cpu_gpr[a->rd], cpu_gpr_hi[a->rd], ax, bx); in trans_PEXTUW()
570 tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], cpu_gpr[a->rd], 32, 32); in trans_PCPYH()
572 tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], 32, 32); in trans_PCPYH()
[all …]
/openbmc/linux/arch/sparc/include/asm/
H A Dhead_32.h13 rd %psr, %l0; b label; rd %wim, %l3; nop;
16 #define SRMMU_TFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 1, %l7;
17 #define SRMMU_DFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 0, %l7;
21 rd %psr, %l0; mov num, %l7; b bad_trap_handler; rd %wim, %l3;
38 rd %psr, %l0;
42 rd %psr,%l0; \
50 rd %psr,%l0; \
67 rd %psr, %i0; jmp %l2; rett %l2 + 4; nop;
73 mov int_level, %l7; rd %psr, %l0; b real_irq_entry; rd %wim, %l3;
79 rd %psr, %l0; rd %wim, %l3; b spill_window_entry; andcc %l0, PSR_PS, %g0;
[all …]
/openbmc/linux/drivers/media/tuners/
H A Dqt1010.c51 qt1010_i2c_oper_t rd[48] = { in qt1010_set_params() local
123 rd[2].val = reg05; in qt1010_set_params()
129 if (mod1 < 8000000) rd[6].val = 0x1d; in qt1010_set_params()
165 rd[35].val = (reg05 & 0xf0); in qt1010_set_params()
186 rd[43].val = priv->reg25_init_val; in qt1010_set_params()
195 freq, rd[2].val, rd[4].val, rd[6].val, rd[7].val, \ in qt1010_set_params()
196 rd[8].val, rd[10].val, rd[13].val, rd[14].val, \ in qt1010_set_params()
197 rd[15].val, rd[35].val, rd[40].val, rd[41].val, \ in qt1010_set_params()
198 rd[43].val, rd[45].val); in qt1010_set_params()
201 if (rd[i].oper == QT1010_WR) { in qt1010_set_params()
[all …]

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