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/openbmc/qemu/target/rx/
H A Dinsns.decode24 &rr rd rs
25 &ri rd imm
26 &rrr rd rs rs2
27 &rri rd imm rs2
28 &rm rd rs ld mi
31 &mcnd ld sz rd cd
43 @b2_rds .... .... .... rd:4 &rr rs=%b2_r_0
44 @b2_rds_li .... .... .... rd:4 &rri rs2=%b2_r_0 imm=%b2_li_8
45 @b2_rds_uimm4 .... .... imm:4 rd:4 &rri rs2=%b2_r_0
46 @b2_rs2_uimm4 .... .... imm:4 rs2:4 &rri rd=0
[all …]
H A Ddisas.c173 int ld, int mi, int rs, int rd) in prt_ldmi() argument
180 prt("%s\t%s[r%d]%s, r%d", insn, dsp, rs, sizes[mi], rd); in prt_ldmi()
182 prt("%s\tr%d, r%d", insn, rs, rd); in prt_ldmi()
186 static void prt_ir(DisasContext *ctx, const char *insn, int imm, int rd) in prt_ir() argument
189 prt("%s\t#%d, r%d", insn, imm, rd); in prt_ir()
191 prt("%s\t#0x%08x, r%d", insn, imm, rd); in prt_ir()
200 size[a->sz], a->rs, a->dsp << a->sz, a->rd); in trans_MOV_rm()
203 size[a->sz], a->rs, a->rd); in trans_MOV_rm()
213 size[a->sz], a->dsp << a->sz, a->rs, a->rd); in trans_MOV_mr()
216 size[a->sz], a->rs, a->rd); in trans_MOV_mr()
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H A Dtranslate.c434 tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); in trans_MOV_rm()
445 rx_gen_ld(a->sz, cpu_regs[a->rd], mem); in trans_MOV_mr()
454 tcg_gen_movi_i32(cpu_regs[a->rd], a->imm); in trans_MOV_ir()
465 tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); in trans_MOV_im()
476 rx_gen_ld(a->sz, cpu_regs[a->rd], mem); in trans_MOV_ar()
500 tcg_gen_ext_i32(cpu_regs[a->rd], cpu_regs[a->rs], a->sz | MO_SIGN); in trans_MOV_mm()
508 rx_gen_st(a->sz, cpu_regs[a->rd], addr); in trans_MOV_mm()
512 rx_gen_ld(a->sz, cpu_regs[a->rd], addr); in trans_MOV_mm()
518 addr = rx_index_addr(ctx, mem, a->ldd, a->sz, a->rd); in trans_MOV_mm()
532 tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); in trans_MOV_rp()
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/openbmc/u-boot/post/lib_powerpc/
H A Dcpu_asm.h113 #define ASM_1(opcode, rd) ((opcode) + \ argument
114 ((rd) << 21))
117 #define ASM_11(opcode, rd, rs) ((opcode) + \ argument
118 ((rd) << 21) + \
123 #define ASM_11X(opcode, rd, rs) ((opcode) + \ argument
125 ((rd) << 16))
126 #define ASM_11I(opcode, rd, rs, simm) ((opcode) + \ argument
127 ((rd) << 21) + \
130 #define ASM_11IF(opcode, rd, rs, simm) ((opcode) + \ argument
131 ((rd) << 21) + \
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/openbmc/qemu/target/avr/
H A Ddisas.c140 INSN(ADD, "r%d, r%d", a->rd, a->rr)
141 INSN(ADC, "r%d, r%d", a->rd, a->rr)
142 INSN(ADIW, "r%d:r%d, %d", a->rd + 1, a->rd, a->imm)
143 INSN(SUB, "r%d, r%d", a->rd, a->rr)
144 INSN(SUBI, "r%d, %d", a->rd, a->imm)
145 INSN(SBC, "r%d, r%d", a->rd, a->rr)
146 INSN(SBCI, "r%d, %d", a->rd, a->imm)
147 INSN(SBIW, "r%d:r%d, %d", a->rd + 1, a->rd, a->imm)
148 INSN(AND, "r%d, r%d", a->rd, a->rr)
149 INSN(ANDI, "r%d, %d", a->rd, a->imm)
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H A Dinsn.decode26 %rd 4:5
42 &rd_rr rd rr
43 &rd_imm rd imm
45 @op_rd_rr .... .. . ..... .... &rd_rr rd=%rd rr=%rr
46 @op_rd_imm6 .... .... .. .. .... &rd_imm rd=%rd_c imm=%imm6
47 @op_rd_imm8 .... .... .... .... &rd_imm rd=%rd_a imm=%imm8
48 @fmul .... .... . ... . ... &rd_rr rd=%rd_b rr=%rr_b
66 COM 1001 010 rd:5 0000
67 NEG 1001 010 rd:5 0001
68 INC 1001 010 rd:5 0011
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/openbmc/u-boot/arch/arm/include/debug/
H A D8250.S15 .macro store, rd, rx:vararg
16 str \rd, \rx
19 .macro load, rd, rx:vararg
20 ldr \rd, \rx
23 .macro store, rd, rx:vararg
24 strb \rd, \rx
27 .macro load, rd, rx:vararg
28 ldrb \rd, \rx
34 .macro senduart,rd,rx
35 store \rd, [\rx, #UART_TX << UART_SHIFT]
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/openbmc/qemu/target/mips/tcg/
H A Dloong_translate.c28 static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt, in gen_lext_DIV_G() argument
34 if (rd == 0) { in gen_lext_DIV_G()
53 tcg_gen_movi_tl(cpu_gpr[rd], 0); in gen_lext_DIV_G()
59 tcg_gen_mov_tl(cpu_gpr[rd], t0); in gen_lext_DIV_G()
63 tcg_gen_div_tl(cpu_gpr[rd], t0, t1); in gen_lext_DIV_G()
65 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); in gen_lext_DIV_G()
74 return gen_lext_DIV_G(s, a->rd, a->rs, a->rt, false); in trans_DIV_G()
79 return gen_lext_DIV_G(s, a->rd, a->rs, a->rt, true); in trans_DDIV_G()
82 static bool gen_lext_DIVU_G(DisasContext *s, int rd, int rs, int rt, in gen_lext_DIVU_G() argument
88 if (rd == 0) { in gen_lext_DIVU_G()
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H A Dtx79_translate.c67 gen_store_gpr(cpu_HI[1], a->rd); in trans_MFHI1()
74 gen_store_gpr(cpu_LO[1], a->rd); in trans_MFLO1()
122 if (a->rd == 0) { in trans_parallel_arith()
133 gen_logic_i64(cpu_gpr[a->rd], ax, bx); in trans_parallel_arith()
138 gen_logic_i64(cpu_gpr_hi[a->rd], ax, bx); in trans_parallel_arith()
239 if (a->rd == 0) { in trans_parallel_compare()
259 tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], t2, wlen * i, wlen); in trans_parallel_compare()
268 tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], t2, wlen * i, wlen); in trans_parallel_compare()
421 if (a->rd == 0) { in trans_PPACW()
434 tcg_gen_deposit_i64(cpu_gpr[a->rd], b0, t0, 32, 32); in trans_PPACW()
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H A Docteon.decode19 # BADDU rd, rs, rt
20 # DMUL rd, rs, rt
25 # DPOP rd, rs
26 # POP rd, rs
27 # SEQ rd, rs, rt
29 # SNE rd, rs, rt
32 @r3 ...... rs:5 rt:5 rd:5 ..... ......
40 POP 011100 rs:5 00000 rd:5 00000 10110 dw:1
41 SEQNE 011100 rs:5 rt:5 rd:5 00000 10101 ne:1
44 &lx base index rd
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H A Dtranslate_addr_const.c16 bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa) in gen_lsa() argument
21 if (rd == 0) { in gen_lsa()
30 tcg_gen_add_tl(cpu_gpr[rd], t0, t1); in gen_lsa()
31 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); in gen_lsa()
35 bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa) in gen_dlsa() argument
42 if (rd == 0) { in gen_dlsa()
51 tcg_gen_add_tl(cpu_gpr[rd], t0, t1); in gen_dlsa()
/openbmc/qemu/target/sparc/
H A Dinsns.decode21 SETHI 00 rd:5 100 i:22
38 &r_r_ri rd rs1 rs2_or_imm imm:bool
39 @n_r_ri .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri rd=0
40 @r_r_ri .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri
42 &r_r_ri_cc rd rs1 rs2_or_imm imm:bool cc:bool
43 @r_r_ri_cc .. rd:5 . cc:1 .... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc
44 @r_r_ri_cc0 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=0
45 @r_r_ri_cc1 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=1
47 &r_r_r rd rs1 rs2
48 @r_r_r .. rd:5 ...... rs1:5 . ........ rs2:5 &r_r_r
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/openbmc/qemu/tests/tcg/mips/user/ase/dsp/
H A Dtest_dsp_r1_cmp_eq_ph.c6 int rd, rs, rt; in main() local
15 : "=r"(rd) in main()
19 rd = (rd >> 24) & 0x03; in main()
20 assert(rd == result); in main()
28 : "=r"(rd) in main()
31 rd = (rd >> 24) & 0x03; in main()
32 assert(rd == result); in main()
H A Dtest_dsp_r1_cmp_le_ph.c6 int rd, rs, rt; in main() local
15 : "=r"(rd) in main()
19 rd = (rd >> 24) & 0x03; in main()
20 assert(rd == result); in main()
28 : "=r"(rd) in main()
31 rd = (rd >> 24) & 0x03; in main()
32 assert(rd == result); in main()
H A Dtest_dsp_r1_cmp_lt_ph.c6 int rd, rs, rt; in main() local
15 : "=r"(rd) in main()
19 rd = (rd >> 24) & 0x03; in main()
20 assert(rd == result); in main()
28 : "=r"(rd) in main()
31 rd = (rd >> 24) & 0x03; in main()
32 assert(rd == result); in main()
H A Dtest_dsp_r1_addq_s_ph.c6 int rd, rs, rt; in main() local
15 : "=r"(rd) in main()
18 assert(result == rd); in main()
25 : "=r"(rd) in main()
28 assert(result == rd); in main()
41 : "=r"(rd) in main()
44 assert(result == rd); in main()
57 : "=r"(rd) in main()
60 assert(result == rd); in main()
H A Dtest_dsp_r1_subq_s_w.c6 int rd, rs, rt, dsp; in main() local
18 : "=r"(rd), "=r"(dsp) in main()
23 assert(rd == result); in main()
34 : "=r"(rd), "=r"(dsp) in main()
39 assert(rd == result); in main()
50 : "=r"(rd), "=r"(dsp) in main()
55 assert(rd == result); in main()
66 : "=r"(rd), "=r"(dsp) in main()
71 assert(rd == result); in main()
H A Dtest_dsp_r1_absq_s_w.c6 int rd, rt; in main() local
13 : "=r"(rd) in main()
16 assert(rd == result); in main()
22 : "=r"(rd) in main()
25 assert(rd == result); in main()
31 : "=r"(rd) in main()
34 assert(rd == result); in main()
H A Dtest_dsp_r1_addq_s_w.c7 int rd, rs, rt; in main() local
16 : "=r"(rd) in main()
19 assert(rd == result); in main()
27 : "=r"(rd) in main()
30 assert(rd == result); in main()
38 : "=r"(rd) in main()
41 assert(rd == result); in main()
H A Dtest_dsp_r1_addq_ph.c6 int rd, rs, rt; in main() local
15 : "=r"(rd) in main()
18 assert(result == rd); in main()
25 : "=r"(rd) in main()
28 assert(result == rd); in main()
35 : "=r"(rd) in main()
38 assert(result == rd); in main()
H A Dtest_dsp_r1_precrq_rs_ph_w.c6 int rd, rs, rt; in main() local
17 : "=r"(rd) in main()
20 assert(result == rd); in main()
30 : "=r"(rd), "=r"(dsp) in main()
34 assert(result == rd); in main()
44 : "=r"(rd), "=r"(dsp) in main()
48 assert(result == rd); in main()
/openbmc/qemu/tests/tcg/loongarch64/
H A Dtest_bit.c8 uint64_t rd = 0; \
11 : "=r"(rd) \
14 return rd; \
20 uint64_t rd = 0; \
23 : "=r"(rd) \
26 return rd; \
32 uint64_t rd = 0; \
35 : "=r"(rd) \
38 return rd; \
44 uint64_t rd = 0; \
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/openbmc/qemu/target/riscv/
H A Dinsn16.decode20 %rd 7:5
56 &r rd rs1 rs2 !extern
57 &i imm rs1 rd !extern
59 &j imm rd !extern
61 &u imm rd !extern
62 &shift shamt rs1 rd !extern
63 &r2 rd rs1 !extern
70 @cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd
71 @ci ... . ..... ..... .. &i imm=%imm_ci rs1=%rd %rd
72 @cl_q ... . ..... ..... .. &i imm=%uimm_cl_q rs1=%rs1_3 rd=%rs2_3
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dcrypto_helper.c184 static inline void crypto_sha1_3reg(uint64_t *rd, uint64_t *rn, in crypto_sha1_3reg() argument
188 union CRYPTO_STATE d = { .l = { rd[0], rd[1] } }; in crypto_sha1_3reg()
205 rd[0] = d.l[0]; in crypto_sha1_3reg()
206 rd[1] = d.l[1]; in crypto_sha1_3reg()
208 clear_tail_16(rd, desc); in crypto_sha1_3reg()
243 uint64_t *rd = vd; in HELPER() local
250 rd[0] = m.l[0]; in HELPER()
251 rd[1] = m.l[1]; in HELPER()
258 uint64_t *rd = vd; in HELPER() local
260 union CRYPTO_STATE d = { .l = { rd[0], rd[1] } }; in HELPER()
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/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvd.c.inc66 tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, memop);
110 REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3);
112 TCGv_i64 dest = dest_fpr(ctx, a->rd);
119 gen_set_fpr_d(ctx, a->rd, dest);
128 REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3);
130 TCGv_i64 dest = dest_fpr(ctx, a->rd);
137 gen_set_fpr_d(ctx, a->rd, dest);
146 REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3);
148 TCGv_i64 dest = dest_fpr(ctx, a->rd);
155 gen_set_fpr_d(ctx, a->rd, dest);
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