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Searched refs:r3 (Results 1 – 25 of 183) sorted by relevance

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/openbmc/u-boot/arch/powerpc/cpu/mpc86xx/
H A Dcache.S36 mfspr r3,HID0
37 ori r3,r3,HID0_ICFI
38 mtspr HID0,r3
46 mfspr r3,HID0
47 ori r3,r3,HID0_DCFI
48 mtspr HID0,r3
56 lis r3,0
59 cmp 0,1,r3,r5
61 lwz r5,0(r3)
63 addi r3,r3,0x4
[all …]
H A Drelease.S67 addis r3, r0, L2_INIT@h
68 ori r3, r3, L2_INIT@l
70 mtspr l2cr, r3
75 mfspr r3, l2cr
76 rlwinm. r3, r3, 0, 0, 0
79 mfspr r3, l2cr
80 rlwinm r3, r3, 0, 1, 31
86 mtspr l2cr, r3
88 1: mfspr r3, l2cr
89 oris r3, r3, L2CR_L2I@h
[all …]
H A Dstart.S91 addi r3,r1,STACK_FRAME_OVERHEAD
98 addi r3,r1,STACK_FRAME_OVERHEAD
159 lis r3, L2_INIT@h
160 ori r3, r3, L2_INIT@l
161 mtspr l2cr, r3
170 lis r3, CONFIG_SYS_MONITOR_BASE_EARLY@h
171 ori r3, r3, CONFIG_SYS_MONITOR_BASE_EARLY@l
172 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
173 mtlr r3
199 lis r3,addr_trans_enabled@h
[all …]
/openbmc/u-boot/examples/standalone/
H A Dppc_longjmp.S23 lwz r1,(JB_GPR1*4)(r3)
24 lwz r2,(JB_GPR2*4)(r3)
25 lwz r0,(JB_LR*4)(r3)
26 lwz r14,((JB_GPRS+0)*4)(r3)
27 FP( lfd 14,((JB_FPRS+0*2)*4)(r3))
28 lwz r15,((JB_GPRS+1)*4)(r3)
29 FP( lfd 15,((JB_FPRS+1*2)*4)(r3))
30 lwz r16,((JB_GPRS+2)*4)(r3)
31 FP( lfd 16,((JB_FPRS+2*2)*4)(r3))
32 lwz r17,((JB_GPRS+3)*4)(r3)
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Drelease.S32 mfspr r3, SPRN_HDBCR0
33 oris r3, r3, 0x0080
34 mtspr SPRN_HDBCR0, r3
37 lis r3, HID0_EMCP@h /* enable machine check */
39 ori r3,r3,HID0_TBEN@l /* enable Timebase */
42 ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
44 mtspr SPRN_HID0,r3
47 li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
53 ori r3, r3, HID1_MBDD@l
55 mtspr SPRN_HID1,r3
[all …]
H A Dstart.S87 mr r24, r3
90 mfspr r3,SPRN_SVR
91 rlwinm r3,r3,0,0xff
93 cmpw r3,r4
98 cmpw r3,r4
110 mfspr r3,SPRN_HDBCR0
112 rlwimi r3,r4,0,0x1f8
113 mtspr SPRN_HDBCR0,r3
120 mfspr r3, SPRN_HDBCR0
121 oris r3, r3, 0x0080
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dstart.S110 mfmsr r3
111 andi. r0, r3, (MSR_IR | MSR_DR)
113 andc r3, r3, r0
115 mtspr SRR1, r3
121 stfd 1, 0(r3)
126 lfd 1, 0(r3)
173 lis r3, CONFIG_SYS_IMMR@h
174 ori r3, r3, CONFIG_SYS_IMMR@l
179 stw r3, IMMRBAR(r4)
183 lwz r6, IMMRBAR(r3)
[all …]
/openbmc/u-boot/board/freescale/mx35pdk/
H A Dlowlevel_init.S59 ldrhs r3, =CCM_MPLL_532_HZ
63 ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/
64 ldreq r3, =CCM_MPLL_399_HZ /* auto path*/
66 str r3, [r0, #CLKCTL_MPCTL]
91 mov r3, #0x2000
92 str r3, [r0, #0x0]
93 str r3, [r0, #0x8]
111 ldr r3, =ESDCTL_DELAY_LINE5
112 str r3, [r0, #0x30]
149 mov r3, #0xE
[all …]
/openbmc/u-boot/arch/arm/mach-orion5x/
H A Dlowlevel_init.S79 ldr r3, =0xD0000000
80 add r3, r3, #0x20000
81 str r2, [r3, #0x80]
84 add r3, r2, #0x01000
88 str r0, [r3, #0x480]
91 add r3, r2, #0x31000
95 str r0, [r3, #0xd00]
98 add r3, r2, #0x01000
102 str r0, [r3, #0x504]
103 str r0, [r3, #0x50C]
[all …]
/openbmc/u-boot/arch/powerpc/lib/
H A Dppccache.S23 dcbf r0,r3
34 dcbi r0,r3
46 dcbz r0,r3
69 andc r3,r3,r5
70 subf r4,r3,r4
76 1: dcbf 0,r3
77 addi r3,r3,L1_CACHE_BYTES
93 andc r3,r3,r5
94 subf r4,r3,r4
101 1: dcbi 0,r3
[all …]
H A Dppcstring.S12 addi r5,r3,-1
25 addi r6,r3,-1
35 addi r5,r3,-1
49 addi r5,r3,-1
51 1: lbzu r3,1(r5)
52 cmpwi 1,r3,0
54 subf. r3,r0,r3
61 addi r4,r3,-1
65 subf r3,r3,r4
72 addi r6,r3,-4
[all …]
H A D_ashldi3.S34 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
38 or r3,r3,r6 # MSW |= t1
40 or r3,r3,r7 # MSW |= t2
/openbmc/u-boot/arch/powerpc/cpu/mpc8xx/
H A Dstart.S72 lis r3, CONFIG_SYS_IMMR@h /* position IMMR */
73 mtspr 638, r3
77 li r3, MSR_KERNEL /* Set ME, RI flags */
78 mtmsr r3
79 mtspr SRR1, r3 /* Make SRR1 match MSR */
81 mfspr r3, ICR /* clear Interrupt Cause Register */
94 mfspr r3, IC_CST /* Clear error bits */
95 mfspr r3, DC_CST
97 lis r3, IDC_UNALL@h /* Unlock all */
98 mtspr IC_CST, r3
[all …]
/openbmc/u-boot/post/lib_powerpc/
H A Dasm.S25 mtlr r3
26 mr r3, r4
48 mtlr r3
49 mr r3, r4
71 mtlr r3
72 mr r3, r5
77 stw r3, 0(r4)
92 mtlr r3
93 mr r3, r5
97 stw r3, 0(r4)
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx6/
H A Dmx6_plugin.S46 ldr r3, =ROM_VERSION_OFFSET
47 ldr r4, [r3]
50 ldr r3, =0x00900b00
52 str r4, [r3, #0x5c]
54 ldr r3, =0x00900800
56 str r4, [r3, #0xc0]
64 ldr r3, =ROM_VERSION_OFFSET
65 ldr r4, [r3]
67 ldr r3, =ROM_VERSION_TO12
68 cmp r4, r3
[all …]
/openbmc/u-boot/board/freescale/mx7ulp_evk/
H A Dplugin.S10 ldr r3, =0x00000000
11 str r3, [r2, #0xdc]
14 ldr r3, =0x01000020
15 str r3, [r2, #0x40]
16 ldr r3, =0x01000000
17 str r3, [r2, #0x500]
18 ldr r3, =0x80808080
19 str r3, [r2, #0x50c]
20 ldr r3, =0x00140000
21 str r3, [r2, #0x508]
[all …]
/openbmc/u-boot/arch/nios2/cpu/
H A Dexceptions.S27 stw r3, 12(sp)
69 movhi r3, %hi(external_interrupt)
70 ori r3, r3, %lo(external_interrupt)
72 callr r3
78 ldw r3, 116(sp)
79 addi r3, r3, -4
80 stw r3, 116(sp)
85 movhi r3, %hi(OPC_TRAP)
86 ori r3, r3, %lo(OPC_TRAP)
89 bne r1, r3, 1f
[all …]
/openbmc/qemu/target/tricore/
H A Dtranslate.c445 TCGv r3, void(*op1)(TCGv, TCGv, TCGv), in gen_addsub64_h() argument
463 (*op2)(temp3, r1_high, r3); in gen_addsub64_h()
466 tcg_gen_xor_tl(temp4, r1_high, r3); in gen_addsub64_h()
490 static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) in gen_madd32_d() argument
498 tcg_gen_ext_i32_i64(t3, r3); in gen_madd32_d()
529 TCGv r3) in gen_madd64_d() argument
536 tcg_gen_muls2_tl(t1, t2, r1, r3); in gen_madd64_d()
557 TCGv r3) in gen_maddu64_d() argument
565 tcg_gen_extu_i32_i64(t3, r3); in gen_maddu64_d()
603 TCGv r3, uint32_t n, uint32_t mode) in gen_madd_h() argument
[all …]
/openbmc/u-boot/arch/arm/mach-at91/arm926ejs/
H A Dlowlevel_init.S46 ldr r3, [r0], #4
47 str r3, [r1]
76 ldr r3, [r2]
77 and r3, r4, r3
78 cmp r3, #AT91_PMC_IXR_MOSCS
94 ldr r3, [r2]
95 and r3, r4, r3
96 cmp r3, #AT91_PMC_IXR_LOCKA
114 ldr r3, [r2]
115 and r3, r4, r3
[all …]
/openbmc/u-boot/arch/arm/lib/
H A Dmemset.S21 ands r3, r0, #3 @ 1 unaligned?
29 mov r3, r1
43 stmiage ip!, {r1, r3, r8, lr} @ 64 bytes at a time.
44 stmiage ip!, {r1, r3, r8, lr}
45 stmiage ip!, {r1, r3, r8, lr}
46 stmiage ip!, {r1, r3, r8, lr}
53 stmiane ip!, {r1, r3, r8, lr}
54 stmiane ip!, {r1, r3, r8, lr}
56 stmiane ip!, {r1, r3, r8, lr}
89 stmiage ip!, {r1, r3-r8, lr}
[all …]
H A Ddebug.S56 add r3, r2, r1
58 strb r1, [r3]
64 strb r1, [r3, #-1]!
65 teq r3, r2
78 addruart_current r3, r1, r2
80 1: waituart r2, r3
81 senduart r1, r3
82 busyuart r2, r3
94 addruart_current r3, r1, r2
102 addruart r2, r3, ip
[all …]
/openbmc/u-boot/board/armltd/integrator/
H A Dlowlevel_init.S78 and r3,r1,r2
79 cmp r3,r2
83 mov r3, #CMVAL_LOCK1
84 add r3,r3,#CMVAL_LOCK2
85 str r3, [r0, #OS_LOCK]
124 ldrb r3, [r0, #5] /* number of banks */
126 mul r5, r4, r3 /* size of SDRAM (MB divided by 4) */
161 orr r3, r2, r3, ASL#16 /* OR in number of banks */
162 orr r6, r6, r3 /* OR in size and CAS latency */
188 ldmia r0!, {r3-r10} /* copy from source address [r0] */
[all …]
/openbmc/u-boot/board/nokia/rx51/
H A Dlowlevel_init.S61 ldr r3, kernaddr
65 add r2, r3, r1
72 str r5, [r3]
81 ldmdb r1!, {r3 - r10}
82 stmdb r2!, {r3 - r10}
141 adr r3, end
145 sub r4, r3, r4
149 ldmdb r3!, {r7 - r10}
174 ldmia r0!, {r3 - r10}
175 stmia r1!, {r3 - r10}
[all …]
/openbmc/u-boot/arch/arm/mach-aspeed/ast2500/
H A Dutils.S29 ldr r3, =AST_FMC_DMA_DRAM_ADDR
30 str r0, [r3]
32 ldr r3, =AST_FMC_DMA_FLASH_ADDR
33 str r1, [r3]
35 ldr r3, =AST_FMC_DMA_LENGTH
36 str r2, [r3]
/openbmc/u-boot/arch/arm/mach-aspeed/ast2400/
H A Dutils.S29 ldr r3, =AST_FMC_DMA_DRAM_ADDR
30 str r0, [r3]
32 ldr r3, =AST_FMC_DMA_FLASH_ADDR
33 str r1, [r3]
35 ldr r3, =AST_FMC_DMA_LENGTH
36 str r2, [r3]

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