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Searched refs:r2 (Results 1 – 25 of 255) sorted by relevance

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/openbmc/u-boot/arch/arm/cpu/arm920t/ep93xx/
H A Dlowlevel_init.S86 ldr r4, [r2]
105 ldr r2, =0xdeadbeef
118 cmpeq r5, r2
152 ldr r2, [r0]
155 cmp r1, r2
168 ldr r2, =0x00000001
180 ldreq r2, =0x00000001
202 ldr r2, [r0]
205 cmp r1, r2
221 mov r2, r5
[all …]
/openbmc/u-boot/arch/arm/cpu/arm926ejs/mxs/
H A Dstart.S63 mrc p15, 0, r2, c1, c0, 0
64 push {r2}
67 mrs r2, cpsr
68 push {r2}
69 bic r2, r2, #0x1f
70 orr r2, r2, #0xd3
71 msr cpsr, r2
76 pop {r2}
77 msr cpsr,r2
83 pop {r2}
[all …]
/openbmc/qemu/target/tricore/
H A Dtranslate.c212 static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2, in gen_offset_ld() argument
216 tcg_gen_addi_tl(temp, r2, con); in gen_offset_ld()
220 static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2, in gen_offset_st() argument
224 tcg_gen_addi_tl(temp, r2, con); in gen_offset_st()
261 static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, in gen_st_preincr() argument
265 tcg_gen_addi_tl(temp, r2, off); in gen_st_preincr()
267 tcg_gen_mov_tl(r2, temp); in gen_st_preincr()
270 static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, in gen_ld_preincr() argument
274 tcg_gen_addi_tl(temp, r2, off); in gen_ld_preincr()
276 tcg_gen_mov_tl(r2, temp); in gen_ld_preincr()
[all …]
H A Dop_helper.c264 target_ulong r2) in helper_add_ssov() argument
267 int64_t t2 = sextract64(r2, 0, 32); in helper_add_ssov()
272 uint64_t helper_add64_ssov(CPUTriCoreState *env, uint64_t r1, uint64_t r2) in helper_add64_ssov() argument
277 result = r1 + r2; in helper_add64_ssov()
278 ovf = (result ^ r1) & ~(r1 ^ r2); in helper_add64_ssov()
298 target_ulong r2) in helper_add_h_ssov() argument
302 ret_hw0 = sextract32(r1, 0, 16) + sextract32(r2, 0, 16); in helper_add_h_ssov()
303 ret_hw1 = sextract32(r1, 16, 16) + sextract32(r2, 16, 16); in helper_add_h_ssov()
401 target_ulong r2) in helper_add_suov() argument
404 int64_t t2 = extract64(r2, 0, 32); in helper_add_suov()
[all …]
/openbmc/qemu/tcg/
H A Dtci.c120 static void tci_args_rrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2) in tci_args_rrr() argument
124 *r2 = extract32(insn, 16, 4); in tci_args_rrr()
144 TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) in tci_args_rrrc() argument
148 *r2 = extract32(insn, 16, 4); in tci_args_rrrc()
153 TCGReg *r2, uint8_t *i3, uint8_t *i4) in tci_args_rrrbb() argument
157 *r2 = extract32(insn, 16, 4); in tci_args_rrrbb()
163 TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) in tci_args_rrrr() argument
167 *r2 = extract32(insn, 16, 4); in tci_args_rrrr()
172 TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5) in tci_args_rrrrrc() argument
176 *r2 = extract32(insn, 16, 4); in tci_args_rrrrrc()
[all …]
/openbmc/u-boot/arch/arm/mach-aspeed/ast2400/
H A Dplatform.S105 str r2, [r0]
113 mov r2, #7
114 orr r1, r1, r2, lsl #8
123 mov r2, r1, lsr #18
124 cmp r2, #0x01
140 bic r2, r1, #0xFFFFFF00
141 cmp r2, r3 @ record min
144 bic r2, r1, #0xFFFF00FF
145 cmp r3, r2, lsr #8 @ record max
153 bic r2, r1, #0xFF00FFFF
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/ls102xa/
H A Dpsci.S71 adr r2, _ls102x_psci_supported_table
72 1: ldr r3, [r2]
76 addne r2, r2, #8
80 ldr r0, [r2, #4]
114 @ r2 = target PC
126 mov r1, r2
127 mov r2, r3
136 ldr r2, [r4, #DCFG_CCSR_BRR]
137 rev r2, r2
138 lsr r2, r2, r1
[all …]
/openbmc/u-boot/arch/arm/lib/
H A Dmemset.S30 cmp r2, #16
42 2: subs r2, r2, #64
52 tst r2, #32
55 tst r2, #16
74 cmp r2, #96
80 sub r2, r2, r8
88 3: subs r2, r2, #64
94 tst r2, #32
96 tst r2, #16
102 4: tst r2, #8
[all …]
H A Drelocate.S54 mrc p15, 0, r2, c1, c0, 0 /* V bit (bit[13]) in CP15 c1 */
55 ands r2, r2, #(1 << 13)
58 ldmia r0!, {r2-r8,r10}
59 stmia r1!, {r2-r8,r10}
60 ldmia r0!, {r2-r8,r10}
61 stmia r1!, {r2-r8,r10}
88 ldr r2, _image_copy_end_ofs
89 add r2, r3 /* r2 <- Run &__image_copy_end */
93 cmp r1, r2 /* until source end address [r2] */
100 add r2, r1, r3 /* r2 <- Run &__rel_dyn_start */
[all …]
H A Ddebug.S55 printhex: adr r2, hexbuf
56 add r3, r2, r1
65 teq r3, r2
67 mov r0, r2
78 addruart_current r3, r1, r2
80 1: waituart r2, r3
82 busyuart r2, r3
94 addruart_current r3, r1, r2
102 addruart r2, r3, ip
103 str r2, [r0]
[all …]
H A Dmemcpy.S66 subs r2, r2, #4
74 1: subs r2, r2, #(28)
80 CALGN( sbcsne r4, r3, r2 ) @ C is always set here
83 CALGN( subs r2, r2, r3 ) @ C gets set
87 2: PLD( subs r2, r2, #96 )
95 subs r2, r2, #32
98 PLD( cmn r2, #96 )
101 5: ands ip, r2, #28
142 8: movs r2, r2, lsl #31
160 subs r2, r2, ip
[all …]
/openbmc/u-boot/board/armltd/integrator/
H A Dlowlevel_init.S42 mov r2,#CMMASK_LOWVEC /* Vectors at 0x00000000 for all */
45 orr r2,r2,#CMMASK_INIT_102
53 and r2,r2,#CMMASK_MAP_SIMPLE
58 and r2,r2,#CMMASK_TCRAM_DISABLE
64 and r2,r2,#CMMASK_LE
68 orr r2,r2,#CMMASK_CMxx6_COMMON
78 and r3,r1,r2
79 cmp r3,r2
87 orr r1,r1,r2
123 ldrb r2, [r0, #4] /* number of column address lines */
[all …]
/openbmc/qemu/tests/tcg/arm/system/
H A Dboot.S122 ldr r2, =0xFFF00000 /* 1MB block alignment */
123 and r2, r1, r2
124 orr r2, r2, r3 /* common bits */
125 orr r2, r2, #(1 << 15) /* AP[2] = 1 */
126 orr r2, r2, #(1 << 10) /* AP[0] = 1 => RO @ PL1 */
128 lsr r4, r2, #(20 - 2)
129 str r2, [r0, r4, lsl #0] /* write entry */
133 ldr r2, =0xFFF00000 /* 1MB block alignment */
134 and r2, r1, r2
135 orr r2, r2, r3 /* common bits */
[all …]
/openbmc/u-boot/arch/arm/mach-rmobile/
H A Dlowlevel_init.S26 mov r2, #0x0
27 str r2, [r1]
28 mov r2, #0xF0
30 str r2, [r1]
32 mov r2, #0x1
33 str r2, [r1]
39 ldr r2, [r1, #0xC]
40 str r2, [r1, #0x10]
43 ldr r2, [r0]
44 cmp r2, #0
[all …]
/openbmc/u-boot/arch/arm/mach-aspeed/ast2500/
H A Dplatform.S255 str r2, [r0]
262 mov r2, #7
263 mov r1, r2, lsl #8
272 mov r2, r1, lsr #18
273 cmp r2, #0x01
278 mov r2, #0xF
279 mov r1, r2, lsl #8
296 orr r2, r2, r7
297 orr r1, r1, r2, lsl #8
298 and r2, r6, #0xF
[all …]
/openbmc/u-boot/arch/nios2/cpu/
H A Dstart.S110 movhi r2, %hi(debug_uart_init@h)
111 ori r2, r2, %lo(debug_uart_init@h)
112 callr r2
117 movhi r2, %hi(board_init_f_alloc_reserve@h)
118 ori r2, r2, %lo(board_init_f_alloc_reserve@h)
119 callr r2
120 mov sp, r2
122 movhi r2, %hi(board_init_f_init_reserve@h)
123 ori r2, r2, %lo(board_init_f_init_reserve@h)
124 callr r2
[all …]
/openbmc/u-boot/arch/arm/cpu/arm926ejs/spear/
H A Dspr_lowlevel_init.S34 ldr r2,DDR_ACTIVE_V
35 bic r1, r1, r2
39 ldr r2,CYCLES_MASK_V
40 bic r1, r1, r2
41 ldr r2,REFRESH_CYCLES_V
42 orr r1, r1, r2, lsl #16
46 ldr r2,SREFRESH_MASK_V
47 orr r1, r1, r2
86 ldr r2,PLLFREQ_MASK_V
87 bic r1,r1,r2
[all …]
/openbmc/qemu/target/riscv/
H A Dinsn32.decode50 &r2 rd rs1
81 @r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd
295 fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2
299 fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2
302 fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2
332 fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2
341 fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2
344 fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
347 hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2
348 hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2
[all …]
/openbmc/u-boot/board/freescale/mx7ulp_evk/
H A Dplugin.S9 ldr r2, =0x403f0000
11 str r3, [r2, #0xdc]
13 ldr r2, =0x403e0000
15 str r3, [r2, #0x40]
17 str r3, [r2, #0x500]
19 str r3, [r2, #0x50c]
21 str r3, [r2, #0x508]
23 str r3, [r2, #0x510]
25 str r3, [r2, #0x514]
27 str r3, [r2, #0x500]
[all …]
/openbmc/qemu/tests/tcg/hexagon/
H A Dtest_bitcnt.S17 r2 = cl0(r0) define
20 p0 = cmp.eq(r2, #23); if (p0.new) jump:t test2
26 r2 = cl0(r1:0) define
29 p0 = cmp.eq(r2, #55); if (p0.new) jump:t test3
35 r2 = ct0(r0) define
38 p0 = cmp.eq(r2, #1); if (p0.new) jump:t pass
/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/tremor/tremor/
H A Dtremor-arm-thumb2.patch43 "umull %0,r2,r1,%0;" //qi*=labs(ilsp[j]-wi)
56 "umull %0,r2,r1,%0;\n" //qi*=labs(ilsp[j]-wi)
59 "mov r2,#0;"
63 "addne r2,r2,#8;"
67 "addne r2,r2,#4;"
71 "addne r2,r2,#2;"
75 "addne r2,r2,#1;"
79 "addne r2,r2,#1;"
80 "mov %0,%0,lsr r2;"
81 "mov %1,%1,lsr r2;"
/openbmc/qemu/pc-bios/s390-ccw/
H A Dstart.S22 larl %r2,bss_start_literal /* __bss_start might be unaligned ... */
23 lg %r2,0(%r2) /* ... so load it indirectly */
25 slgr %r3,%r2 /* get sizeof bss */
31 lgr %r1,%r2
38 larl %r2,memsetxc
39 ex %r3,0(%r2)
42 larl %r2,disabled_wait_psw
43 mvc 0x01d0(16),0(%r2)
/openbmc/u-boot/board/syteco/zmx25/
H A Dlowlevel_init.S44 ldr r2, =IMX_SDRAM_BANK0_BASE
65 str r1, [r2, #0x400]
71 ldr r3, [r2]
72 ldr r3, [r2]
79 strb r1, [r2, #0x33]
82 ldr r2, =0x81000000
83 strb r1, [r2]
/openbmc/u-boot/board/freescale/mx35pdk/
H A Dlowlevel_init.S49 mov r2, #0x00006C00
50 add r2, r2, #0x67
51 orr r1, r1, r2
54 ldr r2, =CCM_CCMR_CONFIG
55 str r2, [r0, #CLKCTL_CCMR]
57 check_soc_version r1, r2
61 ldr r2, [r0, #CLKCTL_PDR0]
62 tst r2, #CLKMODE_CONSUMER
99 mov r2, #0x00
104 mov r2, #0x00
[all …]
/openbmc/u-boot/arch/arm/mach-s5pc1xx/
H A Dreset.S15 ldr r2, [r1]
17 and r4, r2, r4
22 ldr r2, =0xC100
26 mov r2, #1
28 str r2, [r1]

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