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/openbmc/smbios-mdr/include/
H A Dcpu.hpp44 using processor = sdbusplus::server::xyz::openbmc_project::inventory::item::Cpu; typedef
294 static const std::array<std::optional<processor::Capability>, 16>
298 processor::Capability::Capable64bit,
299 processor::Capability::MultiCore,
300 processor::Capability::HardwareThread,
301 processor::Capability::ExecuteProtection,
302 processor::Capability::EnhancedVirtualization,
303 processor::Capability::PowerPerformanceControl,
314 sdbusplus::server::object_t<processor, asset, location, connector, rev,
328 sdbusplus::server::object_t<processor, asset, location, connector, rev, in Cpu()
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-multimedia/libopus/
H A Dlibopus_1.5.2.bb42 #| {standard input}:389: Error: selected processor does not support Thumb mode `smull r5,r7,r1,r4'
43 #| {standard input}:418: Error: selected processor does not support Thumb mode `smull r5,r6,r4,r1'
44 #| {standard input}:448: Error: selected processor does not support Thumb mode `smull r4,r5,r1,r0'
45 #| {standard input}:474: Error: selected processor does not support Thumb mode `smull r0,r4,r8,r1'
46 #| {standard input}:510: Error: selected processor does not support Thumb mode `smull fp,r0,r10,r1'
47 #| {standard input}:553: Error: selected processor does not support Thumb mode `smull fp,r1,r10,r3'
48 #| {standard input}:741: Error: selected processor does not support Thumb mode `smull r3,r0,r6,r10'
49 #| {standard input}:761: Error: selected processor does not support Thumb mode `smull fp,r2,r3,r9'
50 #| {standard input}:773: Error: selected processor does not support Thumb mode `smull fp,r3,r5,r8'
/openbmc/smbios-mdr/src/
H A Dcpu.cpp32 processor::socket(result); in socket()
44 processor::family("Unknown Processor Family"); in family()
52 processor::family("Unknown Processor Family"); in family()
56 processor::family(it2->second); in family()
57 processor::effectiveFamily(family2); in family()
62 processor::family(it->second); in family()
63 processor::effectiveFamily(family); in family()
103 std::vector<processor::Capability> result; in characteristics()
104 std::optional<processor::Capability> cap; in characteristics()
118 processor::characteristics(result); in characteristics()
/openbmc/openbmc/meta-openembedded/meta-oe/dynamic-layers/meta-python/recipes-dbs/mongodb/mongodb/
H A Darm64-support.patch32 @@ -309,7 +309,7 @@ if processor == 'i386' or processor == 'emscripten':
33 elif processor == 'arm':
36 -elif processor == "aarch64":
37 +elif processor == "aarch64" or processor == 'arm64':
/openbmc/qemu/docs/system/riscv/
H A Dmicroblaze-v-generic.rst3 The AMD MicroBlaze™ V processor is a soft-core RISC-V processor IP for AMD
4 adaptive SoCs and FPGAs. The MicroBlaze™ V processor is based on the 32-bit (or
6 compatible with the classic MicroBlaze™ V processor (i.e it is a drop in
7 replacement for the classic MicroBlaze™ processor in existing RTL designs).
H A Dxiangshan-kunminghu.rst6 XiangShan is an open-source high-performance RISC-V processor project.
7 The third generation processor is called Kunminghu. Kunminghu is a 64-bit
8 RV64GCBSUHV processor core. More information can be found in our Github
/openbmc/u-boot/doc/driver-model/
H A Dremoteproc-framework.txt19 on various System on Chip(SoCs). The term remote processor is used to
20 indicate that this is not the processor on which U-Boot is operating
22 the processor on which we are functional.
68 NOTE: It depends on the remote processor as to the exact behavior
72 allow us to start the processor(image from a EEPROM/OTP) etc.
79 Remote processor can operate on a certain firmware that maybe loaded
92 {.compatible = "sandbox,test-processor"},
154 compatible = "sandbox,test-processor";
159 compatible = "sandbox,test-processor";
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-devtools/breakpad/breakpad/
H A D0001-Remove-HAVE_GETCONTEXT-check-to-add-local-implementa.patch29 src/processor/minidump.cc \
30 src/processor/pathname_stripper.cc \
31 src/processor/proc_maps_linux.cc
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/
H A D0001-remoteproc-Add-Arm-remoteproc-driver.patch10 switch on or off the remote processor.
61 + processor framework.
111 + * struct arm_rproc_reset_cfg - remote processor reset configuration
123 + * struct arm_rproc_dcfg - Arm remote processor configuration
133 + * struct arm_rproc - Arm remote processor instance
163 + * @rproc: pointer to the remote processor object
187 + * @rproc: pointer to the remote processor object
237 + * @rproc: pointer to the remote processor object
290 + * @rproc: pointer to the remote processor object
307 + * @rproc: pointer to the remote processor object
[all …]
/openbmc/webui-vue/src/store/modules/HardwareStatus/
H A DProcessorStore.js14 state.processors = data.map((processor) => {
35 } = processor;
58 uri: processor['@odata.id'],
/openbmc/qemu/tests/functional/acpi-bits/bits-tests/
H A Dtestacpi.py259 # Find the ProcId defined by the processor object
60 processor = acpi.evaluate(cpupath)
61 # Find the UID defined by the processor object's _UID method
71 …e.test("{} Processor declaration ProcId = _MAT ProcId".format(cpupath), processor.ProcId == subtab…
72 …t_detail("{} ProcId ({:#02x}) != _MAT ProcId ({:#02x})".format(cpupath, processor.ProcId, subtable…
73 testsuite.print_detail("Processor Declaration: {}".format(processor))
75 …st("{} with local APIC in _MAT has local APIC in MADT".format(cpupath), processor.ProcId in procid…
76 …cessor declaration ProcId = _MAT ApicId".format(cpupath), procid_apicid[processor.ProcId] == subta…
77 … MADT ({:#02x}) != _MAT ApicId ({:#02x})".format(cpupath, procid_apicid[processor.ProcId], subtabl…
78 testsuite.print_detail("Processor Declaration: {}".format(processor))
[all …]
/openbmc/u-boot/board/freescale/ls1021atwr/
H A DREADME7 The QorIQ LS1 family, which includes the LS1021A communications processor,
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
18 optimized peripheral features ever offered in a sub-3 W processor.
20 The QorIQ LS1021A processor features an integrated LCD controller,
23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
32 - NEON Co-processor (per core)
/openbmc/u-boot/board/freescale/ls1021aqds/
H A DREADME7 The QorIQ LS1 family, which includes the LS1021A communications processor,
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
18 optimized peripheral features ever offered in a sub-3 W processor.
20 The QorIQ LS1021A processor features an integrated LCD controller,
23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
32 - NEON Co-processor (per core)
/openbmc/u-boot/drivers/remoteproc/
H A DKconfig35 bool "Support for Test processor for Sandbox"
40 Say 'y' here to add support for test processor which does dummy
44 bool "Support for TI Power processor"
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/zram/zram/
H A Dinit19 num_cpus=$(grep -c processor /proc/cpuinfo)
53 num_cpus=$(grep -c processor /proc/cpuinfo)
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc14 The LS1043A integrated multicore processor combines four ARM Cortex-A53
15 processor cores with datapath acceleration optimized for L2/3 packet
52 The QorIQ LS1088A processor is built on the Layerscape
53 architecture combining eight ARM A53 processor cores
79 - Service processor (SP) provides pre-boot initialization and secure-boot
84 The LS2080A integrated multicore processor combines eight ARM Cortex-A57
85 processor cores with high-performance data path acceleration logic and network
123 - Service processor (SP) provides pre-boot initialization and secure-boot
129 A53 processor, with 32 KB of parity protected L1-I cache,
170 The LS1046A integrated multicore processor combines four ARM Cortex-A72
[all …]
/openbmc/u-boot/doc/
H A DREADME.blackfin8 Blackfin Processors embody a new breed of 16/32-bit embedded processor, ideally
16 The Blackfin processor is wholly developed by Analog Devices Inc.
38 the Blackfin processor. You can obtain such a cross-compiler here:
H A DREADME.fsl-esdhc19 determined by ESDHC IP's endian mode or processor's endian mode.
22 by ESDHC IP's endian mode or processor's endian mode.
H A DREADME.xtensa7 Xtensa is a configurable processor architecture from Tensilica, Inc.
29 Adding support for an additional processor configuration
32 The header files for one particular processor configuration are inside
35 the name for the processor configuration, for example, arch-dc233c for
36 the Diamond DC233 processor.
73 the 'entry'. Decoding depends on the processor's endianness so uses the
/openbmc/u-boot/doc/device-tree-bindings/remoteproc/
H A Dremoteproc.txt9 - remoteproc-name: a string, used if provided to describe the processor.
12 processor has internal memory that it uses to execute code and store
/openbmc/openbmc/poky/meta/conf/machine/include/powerpc/
H A Dtune-ppce300c3.inc8 TUNEVALID[ppce300c3] = "Enable ppce300c3 specific processor optimizations"
15 TUNEVALID[ppce300c3-nf] = "Enable ppce300c3 specific processor optimizations (no fpu)"
/openbmc/qemu/hw/timer/
H A Dslavio_timer.c287 unsigned int processor = 1 << i; in slavio_timer_mem_writel() local
292 if ((val & processor) != (s->cputimer_mode & processor)) { in slavio_timer_mem_writel()
293 if (val & processor) { // counter -> user timer in slavio_timer_mem_writel()
306 s->cputimer_mode |= processor; in slavio_timer_mem_writel()
313 s->cputimer_mode &= ~processor; in slavio_timer_mem_writel()
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-kernel/cpupower/
H A Dcpupower.bb1 SUMMARY = "Shows and sets processor power related values"
3 saving related features of your processor."
/openbmc/openbmc/poky/documentation/dev-manual/
H A Dx32-psabi.rst6 x32 processor-specific Application Binary Interface (`x32
8 32-bit processor-specific ABI for Intel 64 (x86-64) architectures. An
16 provide efficient use and access of the Intel 64-bit processor
/openbmc/u-boot/board/intel/
H A DKconfig24 a 64-bit quad-core, single-thread, Intel Atom processor, along with
57 architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit
58 single-core, single-thread, Intel Pentium processor instrunction set
69 processor in a small form factor with Ethernet, micro-SD, USB 2,

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