Lines Matching refs:processor

80     The processor is PowerPC 601.
93     The processor is 40x or 44x family.
96     The processor has a unified L1 cache for instructions and data, as
98     Unused in the kernel since 39c8bf2b3cc1 ("powerpc: Retire e200 core (mpc555x processor)")
111     This is a 601 specific HWCAP, so if it is known that the processor
117     The processor is POWER4 or PPC970/FX/MP.
121     The processor is POWER5.
124     The processor is POWER5+.
127     The processor is Cell.
130     The processor implements the embedded category ("BookE") architecture.
133     The processor implements SMT.
136     The processor icache is coherent with the dcache, and instruction storage
146     The processor supports the v2.05 userlevel architecture. Processors
150     The processor is PA6T.
156     The processor is POWER6.
159     The processor supports the v2.06 userlevel architecture. Processors
166     The processor supports architected PMU events in the range 0xE0-0xFF.
169     The processor supports true little-endian mode.
172     The processor supports "PowerPC Little-Endian", that uses address
181     The processor supports the v2.07 userlevel architecture. Processors
208     The processor supports the v3.0B / v3.0C userlevel architecture. Processors
227     The processor supports the v3.1 userlevel architecture. Processors