| /openbmc/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3128.c | 32 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
46 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
50 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
63 (div->postdiv2 << PLL_POSTDIV2_SHIFT | in rkclk_set_pll()
79 u32 postdiv1, postdiv2 = 1; in pll_para_config() local
94 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); in pll_para_config()
95 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); in pll_para_config()
98 vco_khz = freq_khz * postdiv1 * postdiv2; in pll_para_config()
101 postdiv2 > max_postdiv2) { in pll_para_config()
108 div->postdiv2 = postdiv2; in pll_para_config()
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| H A D | clk_rk322x.c | 31 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
49 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
53 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
66 (div->postdiv2 << PLL_POSTDIV2_SHIFT | in rkclk_set_pll()
173 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
202 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in rkclk_pll_get_rate()
204 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
325 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
329 {.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
333 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
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| H A D | clk_rk3036.c | 34 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
52 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
57 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
68 (div->postdiv2 << PLL_POSTDIV2_SHIFT | in rkclk_set_pll()
172 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
201 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in rkclk_pll_get_rate()
203 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
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| H A D | clk_rk3399.c | 36 u32 postdiv2; member
47 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
318 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
323 div->postdiv2, vco_khz, output_khz); in rkclk_set_pll()
344 (div->postdiv2 << PLL_POSTDIV2_SHIFT) | in rkclk_set_pll()
360 u32 postdiv1, postdiv2 = 1; in pll_para_config() local
375 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); in pll_para_config()
376 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); in pll_para_config()
379 vco_khz = freq_khz * postdiv1 * postdiv2; in pll_para_config()
382 postdiv2 > max_postdiv2) { in pll_para_config()
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| H A D | clk_rv1108.c | 34 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
73 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
77 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
96 div->postdiv2 << POSTDIV2_SHIFT | in rkclk_set_pll()
120 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
133 postdiv2 = (con1 & POSTDIV2_MASK) >> POSTDIV2_SHIFT; in rkclk_pll_get_rate()
135 freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
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| H A D | clk_rk3328.c | 24 u32 postdiv2; member
35 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
242 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
247 div->postdiv2, vco_khz, output_khz); in rkclk_set_pll()
268 (div->postdiv2 << PLL_POSTDIV2_SHIFT) | in rkclk_set_pll()
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| /openbmc/linux/drivers/clk/pistachio/ |
| H A D | clk-pll.c | 241 params->postdiv2 != old_postdiv2)) in pll_gf40lp_frac_set_rate()
244 if (params->postdiv2 > params->postdiv1) in pll_gf40lp_frac_set_rate()
254 (params->postdiv2 << PLL_FRAC_CTRL2_POSTDIV2_SHIFT); in pll_gf40lp_frac_set_rate()
273 u64 val, prediv, fbdiv, frac, postdiv1, postdiv2, rate; in pll_gf40lp_frac_recalc_rate() local
282 postdiv2 = (val >> PLL_FRAC_CTRL2_POSTDIV2_SHIFT) & in pll_gf40lp_frac_recalc_rate()
387 params->postdiv2 != old_postdiv2)) in pll_gf40lp_laint_set_rate()
390 if (params->postdiv2 > params->postdiv1) in pll_gf40lp_laint_set_rate()
400 (params->postdiv2 << PLL_INT_CTRL1_POSTDIV2_SHIFT); in pll_gf40lp_laint_set_rate()
413 u32 val, prediv, fbdiv, postdiv1, postdiv2; in pll_gf40lp_laint_recalc_rate() local
421 postdiv2 = (val >> PLL_INT_CTRL1_POSTDIV2_SHIFT) & in pll_gf40lp_laint_recalc_rate()
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| H A D | clk.h | 100 unsigned long long postdiv2; member
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| /openbmc/linux/drivers/clk/visconti/ |
| H A D | pll.h | 34 .postdiv2 = _postdiv2 \
45 unsigned int postdiv2; member
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| H A D | pll.c | 49 #define PLL_CREATE_OSTDIV(table) (table->postdiv2 << 4 | table->postdiv1)
72 rate_table->postdiv2 = (postdiv >> 4) & PLL_POSTDIV_MASK; in visconti_pll_get_params()
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| /openbmc/linux/drivers/clk/rockchip/ |
| H A D | clk-pll.c | 153 rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT) in rockchip_rk3036_pll_get_params()
184 do_div(rate64, cur.postdiv2); in rockchip_rk3036_pll_recalc_rate()
202 rate->postdiv2, rate->dsmpd, rate->frac); in rockchip_rk3036_pll_set_params()
318 cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, in rockchip_rk3036_pll_init()
321 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, in rockchip_rk3036_pll_init()
325 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || in rockchip_rk3036_pll_init()
633 rate->postdiv2 = ((pllcon >> RK3399_PLLCON1_POSTDIV2_SHIFT) in rockchip_rk3399_pll_get_params()
666 do_div(rate64, cur.postdiv2); in rockchip_rk3399_pll_recalc_rate()
684 rate->postdiv2, rate->dsmpd, rate->frac); in rockchip_rk3399_pll_set_params()
802 cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, in rockchip_rk3399_pll_init()
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| H A D | clk.h | 299 .postdiv2 = _postdiv2, \
362 unsigned int postdiv2; member
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| /openbmc/linux/arch/mips/ar7/ |
| H A D | clock.c | 75 u32 postdiv2; member
272 int prediv, int postdiv, int postdiv2, int mul, u32 frequency) in tnetd7200_set_clock() argument
277 base, frequency, prediv, postdiv, postdiv2, mul); in tnetd7200_set_clock()
294 writel(DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F), &clock->postdiv2); in tnetd7200_set_clock()
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| /openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | cru_rk3036.h | 64 u32 postdiv2; member
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| H A D | cru_rk322x.h | 65 u32 postdiv2; member
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| H A D | cru_rk3128.h | 67 u32 postdiv2; member
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| H A D | cru_rv1108.h | 57 u32 postdiv2; member
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| /openbmc/linux/drivers/gpu/drm/msm/dsi/phy/ |
| H A D | dsi_phy_28nm_8960.c | 51 u8 postdiv2; member
351 cached_state->postdiv2 = in dsi_28nm_pll_save_state()
377 cached_state->postdiv2); in dsi_28nm_pll_restore_state()
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| /openbmc/linux/drivers/clk/ |
| H A D | clk-bm1880.c | 478 u32 postdiv1, postdiv2, denominator; in bm1880_pll_rate_calc() local
483 postdiv2 = (regval >> 12) & 0x7; in bm1880_pll_rate_calc()
486 denominator = refdiv * postdiv1 * postdiv2; in bm1880_pll_rate_calc()
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| /openbmc/u-boot/arch/arm/mach-rockchip/rk3036/ |
| H A D | sdram_rk3036.c | 343 (dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT | in rkdclk_init()
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