1b4cbe606SNobuhiro Iwamatsu /* SPDX-License-Identifier: GPL-2.0-only */ 2b4cbe606SNobuhiro Iwamatsu /* 3b4cbe606SNobuhiro Iwamatsu * Copyright (c) 2021 TOSHIBA CORPORATION 4b4cbe606SNobuhiro Iwamatsu * Copyright (c) 2021 Toshiba Electronic Devices & Storage Corporation 5b4cbe606SNobuhiro Iwamatsu * 6b4cbe606SNobuhiro Iwamatsu * Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> 7b4cbe606SNobuhiro Iwamatsu */ 8b4cbe606SNobuhiro Iwamatsu 9b4cbe606SNobuhiro Iwamatsu #ifndef _VISCONTI_PLL_H_ 10b4cbe606SNobuhiro Iwamatsu #define _VISCONTI_PLL_H_ 11b4cbe606SNobuhiro Iwamatsu 12b4cbe606SNobuhiro Iwamatsu #include <linux/clk-provider.h> 13b4cbe606SNobuhiro Iwamatsu #include <linux/regmap.h> 14b4cbe606SNobuhiro Iwamatsu #include <linux/spinlock.h> 15b4cbe606SNobuhiro Iwamatsu 16b4cbe606SNobuhiro Iwamatsu struct visconti_pll_provider { 17b4cbe606SNobuhiro Iwamatsu void __iomem *reg_base; 18b4cbe606SNobuhiro Iwamatsu struct device_node *node; 19*c21a0913SGustavo A. R. Silva 20*c21a0913SGustavo A. R. Silva /* Must be last */ 21*c21a0913SGustavo A. R. Silva struct clk_hw_onecell_data clk_data; 22b4cbe606SNobuhiro Iwamatsu }; 23b4cbe606SNobuhiro Iwamatsu 24b4cbe606SNobuhiro Iwamatsu #define VISCONTI_PLL_RATE(_rate, _dacen, _dsmen, \ 25b4cbe606SNobuhiro Iwamatsu _refdiv, _intin, _fracin, _postdiv1, _postdiv2) \ 26b4cbe606SNobuhiro Iwamatsu { \ 27b4cbe606SNobuhiro Iwamatsu .rate = _rate, \ 28b4cbe606SNobuhiro Iwamatsu .dacen = _dacen, \ 29b4cbe606SNobuhiro Iwamatsu .dsmen = _dsmen, \ 30b4cbe606SNobuhiro Iwamatsu .refdiv = _refdiv, \ 31b4cbe606SNobuhiro Iwamatsu .intin = _intin, \ 32b4cbe606SNobuhiro Iwamatsu .fracin = _fracin, \ 33b4cbe606SNobuhiro Iwamatsu .postdiv1 = _postdiv1, \ 34b4cbe606SNobuhiro Iwamatsu .postdiv2 = _postdiv2 \ 35b4cbe606SNobuhiro Iwamatsu } 36b4cbe606SNobuhiro Iwamatsu 37b4cbe606SNobuhiro Iwamatsu struct visconti_pll_rate_table { 38b4cbe606SNobuhiro Iwamatsu unsigned long rate; 39b4cbe606SNobuhiro Iwamatsu unsigned int dacen; 40b4cbe606SNobuhiro Iwamatsu unsigned int dsmen; 41b4cbe606SNobuhiro Iwamatsu unsigned int refdiv; 42b4cbe606SNobuhiro Iwamatsu unsigned long intin; 43b4cbe606SNobuhiro Iwamatsu unsigned long fracin; 44b4cbe606SNobuhiro Iwamatsu unsigned int postdiv1; 45b4cbe606SNobuhiro Iwamatsu unsigned int postdiv2; 46b4cbe606SNobuhiro Iwamatsu }; 47b4cbe606SNobuhiro Iwamatsu 48b4cbe606SNobuhiro Iwamatsu struct visconti_pll_info { 49b4cbe606SNobuhiro Iwamatsu unsigned int id; 50b4cbe606SNobuhiro Iwamatsu const char *name; 51b4cbe606SNobuhiro Iwamatsu const char *parent; 52b4cbe606SNobuhiro Iwamatsu unsigned long base_reg; 53b4cbe606SNobuhiro Iwamatsu const struct visconti_pll_rate_table *rate_table; 54b4cbe606SNobuhiro Iwamatsu }; 55b4cbe606SNobuhiro Iwamatsu 56b4cbe606SNobuhiro Iwamatsu struct visconti_pll_provider * __init visconti_init_pll(struct device_node *np, 57b4cbe606SNobuhiro Iwamatsu void __iomem *base, 58b4cbe606SNobuhiro Iwamatsu unsigned long nr_plls); 59b4cbe606SNobuhiro Iwamatsu void visconti_register_plls(struct visconti_pll_provider *ctx, 60b4cbe606SNobuhiro Iwamatsu const struct visconti_pll_info *list, 61b4cbe606SNobuhiro Iwamatsu unsigned int nr_plls, spinlock_t *lock); 62b4cbe606SNobuhiro Iwamatsu 63b4cbe606SNobuhiro Iwamatsu #endif /* _VISCONTI_PLL_H_ */ 64