| /openbmc/linux/drivers/clk/starfive/ |
| H A D | clk-starfive-jh7110-pll.c | 85 unsigned postdiv1 : 2; member
151 u32 postdiv1; member
165 .postdiv1 = 0,
171 .postdiv1 = 0,
177 .postdiv1 = 0,
183 .postdiv1 = 0,
189 .postdiv1 = 0,
195 .postdiv1 = 0,
201 .postdiv1 = 0,
207 .postdiv1 = 0,
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| /openbmc/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3128.c | 32 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
46 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
49 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
61 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()
79 u32 postdiv1, postdiv2 = 1; in pll_para_config() local
92 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); in pll_para_config()
93 if (postdiv1 > max_postdiv1) { in pll_para_config()
94 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); in pll_para_config()
95 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); in pll_para_config()
98 vco_khz = freq_khz * postdiv1 * postdiv2; in pll_para_config()
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| H A D | clk_rk322x.c | 31 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
49 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
52 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
64 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()
173 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
199 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rkclk_pll_get_rate()
204 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
325 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
329 {.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
333 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
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| H A D | clk_rk3399.c | 35 u32 postdiv1; member
47 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
318 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
322 pll_con, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
345 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | in rkclk_set_pll()
360 u32 postdiv1, postdiv2 = 1; in pll_para_config() local
373 postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); in pll_para_config()
374 if (postdiv1 > max_postdiv1) { in pll_para_config()
375 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); in pll_para_config()
376 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); in pll_para_config()
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| H A D | clk_rk3036.c | 34 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
52 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
56 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
66 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()
172 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
198 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rkclk_pll_get_rate()
203 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
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| H A D | clk_rv1108.c | 34 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
73 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
76 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
95 (div->postdiv1 << POSTDIV1_SHIFT | in rkclk_set_pll()
120 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
132 postdiv1 = (con1 & POSTDIV1_MASK) >> POSTDIV1_SHIFT; in rkclk_pll_get_rate()
135 freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
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| H A D | clk_rk3328.c | 23 u32 postdiv1; member
35 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
242 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
246 pll_con, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
265 (div->postdiv1 << PLL_POSTDIV1_SHIFT)); in rkclk_set_pll()
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| /openbmc/linux/drivers/clk/pistachio/ |
| H A D | clk-pll.c | 240 (params->postdiv1 != old_postdiv1 || in pll_gf40lp_frac_set_rate()
244 if (params->postdiv2 > params->postdiv1) in pll_gf40lp_frac_set_rate()
253 (params->postdiv1 << PLL_FRAC_CTRL2_POSTDIV1_SHIFT) | in pll_gf40lp_frac_set_rate()
273 u64 val, prediv, fbdiv, frac, postdiv1, postdiv2, rate; in pll_gf40lp_frac_recalc_rate() local
280 postdiv1 = (val >> PLL_FRAC_CTRL2_POSTDIV1_SHIFT) & in pll_gf40lp_frac_recalc_rate()
293 rate = do_div_round_closest(rate, (prediv * postdiv1 * postdiv2) << 24); in pll_gf40lp_frac_recalc_rate()
386 (params->postdiv1 != old_postdiv1 || in pll_gf40lp_laint_set_rate()
390 if (params->postdiv2 > params->postdiv1) in pll_gf40lp_laint_set_rate()
399 (params->postdiv1 << PLL_INT_CTRL1_POSTDIV1_SHIFT) | in pll_gf40lp_laint_set_rate()
413 u32 val, prediv, fbdiv, postdiv1, postdiv2; in pll_gf40lp_laint_recalc_rate() local
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| H A D | clk.h | 99 unsigned long long postdiv1; member
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| /openbmc/linux/drivers/clk/rockchip/ |
| H A D | clk-pll.c | 147 rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT) in rockchip_rk3036_pll_get_params()
183 do_div(rate64, cur.postdiv1); in rockchip_rk3036_pll_recalc_rate()
201 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, in rockchip_rk3036_pll_set_params()
216 HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK, in rockchip_rk3036_pll_set_params()
318 cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, in rockchip_rk3036_pll_init()
321 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, in rockchip_rk3036_pll_init()
324 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || in rockchip_rk3036_pll_init()
631 rate->postdiv1 = ((pllcon >> RK3399_PLLCON1_POSTDIV1_SHIFT) in rockchip_rk3399_pll_get_params()
665 do_div(rate64, cur.postdiv1); in rockchip_rk3399_pll_recalc_rate()
683 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, in rockchip_rk3399_pll_set_params()
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| H A D | clk.h | 297 .postdiv1 = _postdiv1, \
360 unsigned int postdiv1; member
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| /openbmc/linux/drivers/clk/visconti/ |
| H A D | pll.h | 33 .postdiv1 = _postdiv1, \
44 unsigned int postdiv1; member
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| H A D | pll.c | 49 #define PLL_CREATE_OSTDIV(table) (table->postdiv2 << 4 | table->postdiv1)
71 rate_table->postdiv1 = postdiv & PLL_POSTDIV_MASK; in visconti_pll_get_params()
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| /openbmc/linux/drivers/gpu/drm/msm/dsi/phy/ |
| H A D | dsi_phy_28nm_8960.c | 52 u8 postdiv1; member
353 cached_state->postdiv1 = in dsi_28nm_pll_save_state()
379 cached_state->postdiv1); in dsi_28nm_pll_restore_state()
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| H A D | dsi_phy_28nm.c | 65 u8 postdiv1; member
564 cached_state->postdiv1 = in dsi_28nm_pll_save_state()
591 cached_state->postdiv1); in dsi_28nm_pll_restore_state()
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| /openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | cru_rk3036.h | 63 u32 postdiv1; member
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| H A D | cru_rk322x.h | 64 u32 postdiv1; member
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| H A D | cru_rk3128.h | 66 u32 postdiv1; member
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| H A D | cru_rv1108.h | 56 u32 postdiv1; member
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| /openbmc/linux/drivers/clk/ |
| H A D | clk-bm1880.c | 478 u32 postdiv1, postdiv2, denominator; in bm1880_pll_rate_calc() local
482 postdiv1 = (regval >> 8) & 0x7; in bm1880_pll_rate_calc()
486 denominator = refdiv * postdiv1 * postdiv2; in bm1880_pll_rate_calc()
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| /openbmc/u-boot/arch/arm/mach-rockchip/rk3036/ |
| H A D | sdram_rk3036.c | 340 (dpll_init_cfg.postdiv1 << PLL_POSTDIV1_SHIFT) | in rkdclk_init()
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