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Searched refs:pll_settings (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clock_source.c193 struct pll_settings *pll_settings, in calc_fb_divider_checking_tolerance() argument
249 struct pll_settings *pll_settings, in calc_pll_dividers_in_range() argument
291 struct pll_settings *pll_settings) in calculate_pixel_clock_pll_dividers() argument
395 struct pll_settings *pll_settings) in pll_adjust_pix_clk() argument
473 struct pll_settings *pll_settings, in dce110_get_pix_clk_dividers_helper() argument
535 struct pll_settings *pll_settings, in dce112_get_pix_clk_dividers_helper() argument
567 struct pll_settings *pll_settings) in dce110_get_pix_clk_dividers() argument
600 struct pll_settings *pll_settings) in dce112_get_pix_clk_dividers() argument
844 struct pll_settings *pll_settings) in dce110_program_pix_clk() argument
918 struct pll_settings *pll_settings) in dce112_program_pix_clk() argument
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dclock_source.h106 struct pll_settings { struct
167 struct pll_settings *);
171 struct pll_settings *);
H A Dcore_types.h376 struct pll_settings pll_settings; member
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_hwseq.c462 &pipe_ctx->pll_settings); in apply_symclk_on_tx_off_wa()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_hw_sequencer.c1360 pipe_ctx->pll_settings.feedback_divider; in build_audio_output()
1370 pipe_ctx->pll_settings.ss_percentage; in build_audio_output()
1441 &pipe_ctx->pll_settings)) { in dce110_enable_stream_timing()
3084 &pipes[i].pll_settings); in dce110_enable_dp_link_output()
H A Ddce110_resource.c923 &pipe_ctx->pll_settings); in dce110_resource_build_pipe_hw_param()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_resource.c1044 &pipe_ctx->pll_settings); in build_pipe_hw_param()
H A Ddcn10_hw_sequencer.c928 &pipe_ctx->pll_settings)) { in dcn10_enable_stream_timing()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_hwseq.c1310 &pipe_ctx->pll_settings); in apply_symclk_on_tx_off_wa()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_resource.c1283 &pipe_ctx->pll_settings); in build_pipe_hw_param()
H A Ddcn20_hwseq.c728 &pipe_ctx->pll_settings)) { in dcn20_enable_stream_timing()