Home
last modified time | relevance | path

Searched refs:pll0_div (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/clk/renesas/
H A Drcar-gen2-cpg.h38 unsigned int pll0_div, u32 mode);
H A Drcar-gen2-cpg.c378 unsigned int pll0_div, u32 mode) in rcar_gen2_cpg_init() argument
383 cpg_pll0_div = pll0_div; in rcar_gen2_cpg_init()
/openbmc/u-boot/drivers/clk/renesas/
H A Drenesas-cpg-mssr.h30 unsigned int pll0_div; member
H A Dr8a7792-cpg-mssr.c219 .pll0_div = 2,
H A Dr8a7794-cpg-mssr.c248 .pll0_div = 2,
H A Dr8a7791-cpg-mssr.c267 .pll0_div = 2,
H A Dr8a7790-cpg-mssr.c271 .pll0_div = 2,
H A Dclk-rcar-gen2.c157 rate = (gen2_clk_get_rate(&parent) * mult) / info->pll0_div; in gen2_clk_get_rate()