1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
267dbebe2SMarek Vasut /*
367dbebe2SMarek Vasut * Renesas R8A7791 CPG MSSR driver
467dbebe2SMarek Vasut *
567dbebe2SMarek Vasut * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
667dbebe2SMarek Vasut *
767dbebe2SMarek Vasut * Based on the following driver from Linux kernel:
867dbebe2SMarek Vasut * r8a7791 Clock Pulse Generator / Module Standby and Software Reset
967dbebe2SMarek Vasut * Copyright (C) 2015-2017 Glider bvba
1067dbebe2SMarek Vasut * Based on clk-rcar-gen2.c
1167dbebe2SMarek Vasut * Copyright (C) 2013 Ideas On Board SPRL
1267dbebe2SMarek Vasut */
1367dbebe2SMarek Vasut
1467dbebe2SMarek Vasut #include <common.h>
1567dbebe2SMarek Vasut #include <clk-uclass.h>
1667dbebe2SMarek Vasut #include <dm.h>
1767dbebe2SMarek Vasut
1867dbebe2SMarek Vasut #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
1967dbebe2SMarek Vasut
2067dbebe2SMarek Vasut #include "renesas-cpg-mssr.h"
2167dbebe2SMarek Vasut #include "rcar-gen2-cpg.h"
2267dbebe2SMarek Vasut
2367dbebe2SMarek Vasut enum clk_ids {
2467dbebe2SMarek Vasut /* Core Clock Outputs exported to DT */
2567dbebe2SMarek Vasut LAST_DT_CORE_CLK = R8A7791_CLK_OSC,
2667dbebe2SMarek Vasut
2767dbebe2SMarek Vasut /* External Input Clocks */
2867dbebe2SMarek Vasut CLK_EXTAL,
2967dbebe2SMarek Vasut CLK_USB_EXTAL,
3067dbebe2SMarek Vasut
3167dbebe2SMarek Vasut /* Internal Core Clocks */
3267dbebe2SMarek Vasut CLK_MAIN,
3367dbebe2SMarek Vasut CLK_PLL0,
3467dbebe2SMarek Vasut CLK_PLL1,
3567dbebe2SMarek Vasut CLK_PLL3,
3667dbebe2SMarek Vasut CLK_PLL1_DIV2,
3767dbebe2SMarek Vasut
3867dbebe2SMarek Vasut /* Module Clocks */
3967dbebe2SMarek Vasut MOD_CLK_BASE
4067dbebe2SMarek Vasut };
4167dbebe2SMarek Vasut
4267dbebe2SMarek Vasut static const struct cpg_core_clk r8a7791_core_clks[] = {
4367dbebe2SMarek Vasut /* External Clock Inputs */
4467dbebe2SMarek Vasut DEF_INPUT("extal", CLK_EXTAL),
4567dbebe2SMarek Vasut DEF_INPUT("usb_extal", CLK_USB_EXTAL),
4667dbebe2SMarek Vasut
4767dbebe2SMarek Vasut /* Internal Core Clocks */
4867dbebe2SMarek Vasut DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
4967dbebe2SMarek Vasut DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
5067dbebe2SMarek Vasut DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
5167dbebe2SMarek Vasut DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
5267dbebe2SMarek Vasut
5367dbebe2SMarek Vasut DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
5467dbebe2SMarek Vasut
5567dbebe2SMarek Vasut /* Core Clock Outputs */
5667dbebe2SMarek Vasut DEF_BASE("z", R8A7791_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),
5767dbebe2SMarek Vasut DEF_BASE("lb", R8A7791_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
5867dbebe2SMarek Vasut DEF_BASE("adsp", R8A7791_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
5967dbebe2SMarek Vasut DEF_BASE("sdh", R8A7791_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
6067dbebe2SMarek Vasut DEF_BASE("sd0", R8A7791_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
6167dbebe2SMarek Vasut DEF_BASE("qspi", R8A7791_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
6267dbebe2SMarek Vasut DEF_BASE("rcan", R8A7791_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
6367dbebe2SMarek Vasut
6467dbebe2SMarek Vasut DEF_FIXED("zg", R8A7791_CLK_ZG, CLK_PLL1, 3, 1),
6567dbebe2SMarek Vasut DEF_FIXED("zx", R8A7791_CLK_ZX, CLK_PLL1, 3, 1),
6667dbebe2SMarek Vasut DEF_FIXED("zs", R8A7791_CLK_ZS, CLK_PLL1, 6, 1),
6767dbebe2SMarek Vasut DEF_FIXED("hp", R8A7791_CLK_HP, CLK_PLL1, 12, 1),
6867dbebe2SMarek Vasut DEF_FIXED("i", R8A7791_CLK_I, CLK_PLL1, 2, 1),
6967dbebe2SMarek Vasut DEF_FIXED("b", R8A7791_CLK_B, CLK_PLL1, 12, 1),
7067dbebe2SMarek Vasut DEF_FIXED("p", R8A7791_CLK_P, CLK_PLL1, 24, 1),
7167dbebe2SMarek Vasut DEF_FIXED("cl", R8A7791_CLK_CL, CLK_PLL1, 48, 1),
7267dbebe2SMarek Vasut DEF_FIXED("m2", R8A7791_CLK_M2, CLK_PLL1, 8, 1),
7367dbebe2SMarek Vasut DEF_FIXED("zb3", R8A7791_CLK_ZB3, CLK_PLL3, 4, 1),
7467dbebe2SMarek Vasut DEF_FIXED("zb3d2", R8A7791_CLK_ZB3D2, CLK_PLL3, 8, 1),
7567dbebe2SMarek Vasut DEF_FIXED("ddr", R8A7791_CLK_DDR, CLK_PLL3, 8, 1),
7667dbebe2SMarek Vasut DEF_FIXED("mp", R8A7791_CLK_MP, CLK_PLL1_DIV2, 15, 1),
7767dbebe2SMarek Vasut DEF_FIXED("cp", R8A7791_CLK_CP, CLK_EXTAL, 2, 1),
7867dbebe2SMarek Vasut DEF_FIXED("r", R8A7791_CLK_R, CLK_PLL1, 49152, 1),
7967dbebe2SMarek Vasut DEF_FIXED("osc", R8A7791_CLK_OSC, CLK_PLL1, 12288, 1),
8067dbebe2SMarek Vasut
8167dbebe2SMarek Vasut DEF_DIV6P1("sd2", R8A7791_CLK_SD2, CLK_PLL1_DIV2, 0x078),
8267dbebe2SMarek Vasut DEF_DIV6P1("sd3", R8A7791_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
8367dbebe2SMarek Vasut DEF_DIV6P1("mmc0", R8A7791_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
8467dbebe2SMarek Vasut DEF_DIV6P1("ssp", R8A7791_CLK_SSP, CLK_PLL1_DIV2, 0x248),
8567dbebe2SMarek Vasut DEF_DIV6P1("ssprs", R8A7791_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c),
8667dbebe2SMarek Vasut };
8767dbebe2SMarek Vasut
8867dbebe2SMarek Vasut static const struct mssr_mod_clk r8a7791_mod_clks[] = {
8967dbebe2SMarek Vasut DEF_MOD("msiof0", 0, R8A7791_CLK_MP),
9067dbebe2SMarek Vasut DEF_MOD("vcp0", 101, R8A7791_CLK_ZS),
9167dbebe2SMarek Vasut DEF_MOD("vpc0", 103, R8A7791_CLK_ZS),
9267dbebe2SMarek Vasut DEF_MOD("jpu", 106, R8A7791_CLK_M2),
9367dbebe2SMarek Vasut DEF_MOD("ssp1", 109, R8A7791_CLK_ZS),
9467dbebe2SMarek Vasut DEF_MOD("tmu1", 111, R8A7791_CLK_P),
9567dbebe2SMarek Vasut DEF_MOD("3dg", 112, R8A7791_CLK_ZG),
9667dbebe2SMarek Vasut DEF_MOD("2d-dmac", 115, R8A7791_CLK_ZS),
9767dbebe2SMarek Vasut DEF_MOD("fdp1-1", 118, R8A7791_CLK_ZS),
9867dbebe2SMarek Vasut DEF_MOD("fdp1-0", 119, R8A7791_CLK_ZS),
9967dbebe2SMarek Vasut DEF_MOD("tmu3", 121, R8A7791_CLK_P),
10067dbebe2SMarek Vasut DEF_MOD("tmu2", 122, R8A7791_CLK_P),
10167dbebe2SMarek Vasut DEF_MOD("cmt0", 124, R8A7791_CLK_R),
10267dbebe2SMarek Vasut DEF_MOD("tmu0", 125, R8A7791_CLK_CP),
10367dbebe2SMarek Vasut DEF_MOD("vsp1du1", 127, R8A7791_CLK_ZS),
10467dbebe2SMarek Vasut DEF_MOD("vsp1du0", 128, R8A7791_CLK_ZS),
10567dbebe2SMarek Vasut DEF_MOD("vsp1-sy", 131, R8A7791_CLK_ZS),
10667dbebe2SMarek Vasut DEF_MOD("scifa2", 202, R8A7791_CLK_MP),
10767dbebe2SMarek Vasut DEF_MOD("scifa1", 203, R8A7791_CLK_MP),
10867dbebe2SMarek Vasut DEF_MOD("scifa0", 204, R8A7791_CLK_MP),
10967dbebe2SMarek Vasut DEF_MOD("msiof2", 205, R8A7791_CLK_MP),
11067dbebe2SMarek Vasut DEF_MOD("scifb0", 206, R8A7791_CLK_MP),
11167dbebe2SMarek Vasut DEF_MOD("scifb1", 207, R8A7791_CLK_MP),
11267dbebe2SMarek Vasut DEF_MOD("msiof1", 208, R8A7791_CLK_MP),
11367dbebe2SMarek Vasut DEF_MOD("scifb2", 216, R8A7791_CLK_MP),
11467dbebe2SMarek Vasut DEF_MOD("sys-dmac1", 218, R8A7791_CLK_ZS),
11567dbebe2SMarek Vasut DEF_MOD("sys-dmac0", 219, R8A7791_CLK_ZS),
11667dbebe2SMarek Vasut DEF_MOD("tpu0", 304, R8A7791_CLK_CP),
11767dbebe2SMarek Vasut DEF_MOD("sdhi3", 311, R8A7791_CLK_SD3),
11867dbebe2SMarek Vasut DEF_MOD("sdhi2", 312, R8A7791_CLK_SD2),
11967dbebe2SMarek Vasut DEF_MOD("sdhi0", 314, R8A7791_CLK_SD0),
12067dbebe2SMarek Vasut DEF_MOD("mmcif0", 315, R8A7791_CLK_MMC0),
12167dbebe2SMarek Vasut DEF_MOD("iic0", 318, R8A7791_CLK_HP),
12267dbebe2SMarek Vasut DEF_MOD("pciec", 319, R8A7791_CLK_MP),
12367dbebe2SMarek Vasut DEF_MOD("iic1", 323, R8A7791_CLK_HP),
12467dbebe2SMarek Vasut DEF_MOD("usb3.0", 328, R8A7791_CLK_MP),
12567dbebe2SMarek Vasut DEF_MOD("cmt1", 329, R8A7791_CLK_R),
12667dbebe2SMarek Vasut DEF_MOD("usbhs-dmac0", 330, R8A7791_CLK_HP),
12767dbebe2SMarek Vasut DEF_MOD("usbhs-dmac1", 331, R8A7791_CLK_HP),
12867dbebe2SMarek Vasut DEF_MOD("irqc", 407, R8A7791_CLK_CP),
12967dbebe2SMarek Vasut DEF_MOD("intc-sys", 408, R8A7791_CLK_ZS),
13067dbebe2SMarek Vasut DEF_MOD("audio-dmac1", 501, R8A7791_CLK_HP),
13167dbebe2SMarek Vasut DEF_MOD("audio-dmac0", 502, R8A7791_CLK_HP),
13267dbebe2SMarek Vasut DEF_MOD("adsp_mod", 506, R8A7791_CLK_ADSP),
13367dbebe2SMarek Vasut DEF_MOD("thermal", 522, CLK_EXTAL),
13467dbebe2SMarek Vasut DEF_MOD("pwm", 523, R8A7791_CLK_P),
13567dbebe2SMarek Vasut DEF_MOD("usb-ehci", 703, R8A7791_CLK_MP),
13667dbebe2SMarek Vasut DEF_MOD("usbhs", 704, R8A7791_CLK_HP),
13767dbebe2SMarek Vasut DEF_MOD("hscif2", 713, R8A7791_CLK_ZS),
13867dbebe2SMarek Vasut DEF_MOD("scif5", 714, R8A7791_CLK_P),
13967dbebe2SMarek Vasut DEF_MOD("scif4", 715, R8A7791_CLK_P),
14067dbebe2SMarek Vasut DEF_MOD("hscif1", 716, R8A7791_CLK_ZS),
14167dbebe2SMarek Vasut DEF_MOD("hscif0", 717, R8A7791_CLK_ZS),
14267dbebe2SMarek Vasut DEF_MOD("scif3", 718, R8A7791_CLK_P),
14367dbebe2SMarek Vasut DEF_MOD("scif2", 719, R8A7791_CLK_P),
14467dbebe2SMarek Vasut DEF_MOD("scif1", 720, R8A7791_CLK_P),
14567dbebe2SMarek Vasut DEF_MOD("scif0", 721, R8A7791_CLK_P),
14667dbebe2SMarek Vasut DEF_MOD("du1", 723, R8A7791_CLK_ZX),
14767dbebe2SMarek Vasut DEF_MOD("du0", 724, R8A7791_CLK_ZX),
14867dbebe2SMarek Vasut DEF_MOD("lvds0", 726, R8A7791_CLK_ZX),
14967dbebe2SMarek Vasut DEF_MOD("ipmmu-sgx", 800, R8A7791_CLK_ZX),
15067dbebe2SMarek Vasut DEF_MOD("mlb", 802, R8A7791_CLK_HP),
15167dbebe2SMarek Vasut DEF_MOD("vin2", 809, R8A7791_CLK_ZG),
15267dbebe2SMarek Vasut DEF_MOD("vin1", 810, R8A7791_CLK_ZG),
15367dbebe2SMarek Vasut DEF_MOD("vin0", 811, R8A7791_CLK_ZG),
15467dbebe2SMarek Vasut DEF_MOD("etheravb", 812, R8A7791_CLK_HP),
15567dbebe2SMarek Vasut DEF_MOD("ether", 813, R8A7791_CLK_P),
15667dbebe2SMarek Vasut DEF_MOD("sata1", 814, R8A7791_CLK_ZS),
15767dbebe2SMarek Vasut DEF_MOD("sata0", 815, R8A7791_CLK_ZS),
15867dbebe2SMarek Vasut DEF_MOD("gyro-adc", 901, R8A7791_CLK_P),
15967dbebe2SMarek Vasut DEF_MOD("gpio7", 904, R8A7791_CLK_CP),
16067dbebe2SMarek Vasut DEF_MOD("gpio6", 905, R8A7791_CLK_CP),
16167dbebe2SMarek Vasut DEF_MOD("gpio5", 907, R8A7791_CLK_CP),
16267dbebe2SMarek Vasut DEF_MOD("gpio4", 908, R8A7791_CLK_CP),
16367dbebe2SMarek Vasut DEF_MOD("gpio3", 909, R8A7791_CLK_CP),
16467dbebe2SMarek Vasut DEF_MOD("gpio2", 910, R8A7791_CLK_CP),
16567dbebe2SMarek Vasut DEF_MOD("gpio1", 911, R8A7791_CLK_CP),
16667dbebe2SMarek Vasut DEF_MOD("gpio0", 912, R8A7791_CLK_CP),
16767dbebe2SMarek Vasut DEF_MOD("can1", 915, R8A7791_CLK_P),
16867dbebe2SMarek Vasut DEF_MOD("can0", 916, R8A7791_CLK_P),
16967dbebe2SMarek Vasut DEF_MOD("qspi_mod", 917, R8A7791_CLK_QSPI),
17067dbebe2SMarek Vasut DEF_MOD("i2c5", 925, R8A7791_CLK_HP),
17167dbebe2SMarek Vasut DEF_MOD("iicdvfs", 926, R8A7791_CLK_CP),
17267dbebe2SMarek Vasut DEF_MOD("i2c4", 927, R8A7791_CLK_HP),
17367dbebe2SMarek Vasut DEF_MOD("i2c3", 928, R8A7791_CLK_HP),
17467dbebe2SMarek Vasut DEF_MOD("i2c2", 929, R8A7791_CLK_HP),
17567dbebe2SMarek Vasut DEF_MOD("i2c1", 930, R8A7791_CLK_HP),
17667dbebe2SMarek Vasut DEF_MOD("i2c0", 931, R8A7791_CLK_HP),
17767dbebe2SMarek Vasut DEF_MOD("ssi-all", 1005, R8A7791_CLK_P),
17867dbebe2SMarek Vasut DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
17967dbebe2SMarek Vasut DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
18067dbebe2SMarek Vasut DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
18167dbebe2SMarek Vasut DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
18267dbebe2SMarek Vasut DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
18367dbebe2SMarek Vasut DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
18467dbebe2SMarek Vasut DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
18567dbebe2SMarek Vasut DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
18667dbebe2SMarek Vasut DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
18767dbebe2SMarek Vasut DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
18867dbebe2SMarek Vasut DEF_MOD("scu-all", 1017, R8A7791_CLK_P),
18967dbebe2SMarek Vasut DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
19067dbebe2SMarek Vasut DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
19167dbebe2SMarek Vasut DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
19267dbebe2SMarek Vasut DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
19367dbebe2SMarek Vasut DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
19467dbebe2SMarek Vasut DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
19567dbebe2SMarek Vasut DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
19667dbebe2SMarek Vasut DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
19767dbebe2SMarek Vasut DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
19867dbebe2SMarek Vasut DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
19967dbebe2SMarek Vasut DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
20067dbebe2SMarek Vasut DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
20167dbebe2SMarek Vasut DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
20267dbebe2SMarek Vasut DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
20367dbebe2SMarek Vasut DEF_MOD("scifa3", 1106, R8A7791_CLK_MP),
20467dbebe2SMarek Vasut DEF_MOD("scifa4", 1107, R8A7791_CLK_MP),
20567dbebe2SMarek Vasut DEF_MOD("scifa5", 1108, R8A7791_CLK_MP),
20667dbebe2SMarek Vasut };
20767dbebe2SMarek Vasut
20867dbebe2SMarek Vasut /*
20967dbebe2SMarek Vasut * CPG Clock Data
21067dbebe2SMarek Vasut */
21167dbebe2SMarek Vasut
21267dbebe2SMarek Vasut /*
21367dbebe2SMarek Vasut * MD EXTAL PLL0 PLL1 PLL3
21467dbebe2SMarek Vasut * 14 13 19 (MHz) *1 *1
21567dbebe2SMarek Vasut *---------------------------------------------------
21667dbebe2SMarek Vasut * 0 0 0 15 x172/2 x208/2 x106
21767dbebe2SMarek Vasut * 0 0 1 15 x172/2 x208/2 x88
21867dbebe2SMarek Vasut * 0 1 0 20 x130/2 x156/2 x80
21967dbebe2SMarek Vasut * 0 1 1 20 x130/2 x156/2 x66
22067dbebe2SMarek Vasut * 1 0 0 26 / 2 x200/2 x240/2 x122
22167dbebe2SMarek Vasut * 1 0 1 26 / 2 x200/2 x240/2 x102
22267dbebe2SMarek Vasut * 1 1 0 30 / 2 x172/2 x208/2 x106
22367dbebe2SMarek Vasut * 1 1 1 30 / 2 x172/2 x208/2 x88
22467dbebe2SMarek Vasut *
22567dbebe2SMarek Vasut * *1 : Table 7.5a indicates VCO output (PLLx = VCO/2)
22667dbebe2SMarek Vasut */
22767dbebe2SMarek Vasut #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
22867dbebe2SMarek Vasut (((md) & BIT(13)) >> 12) | \
22967dbebe2SMarek Vasut (((md) & BIT(19)) >> 19))
23067dbebe2SMarek Vasut static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = {
23167dbebe2SMarek Vasut { 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
23267dbebe2SMarek Vasut { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
23367dbebe2SMarek Vasut };
23467dbebe2SMarek Vasut
23567dbebe2SMarek Vasut static const struct mstp_stop_table r8a7791_mstp_table[] = {
23667dbebe2SMarek Vasut { 0x00640801, 0x400000, 0x00640801, 0x0 },
23767dbebe2SMarek Vasut { 0x9B6C9B5A, 0x0, 0x9B6C9B5A, 0x0 },
23867dbebe2SMarek Vasut { 0x100D21FC, 0x2000, 0x100D21FC, 0x0 },
23967dbebe2SMarek Vasut { 0xF08CD810, 0x0, 0xF08CD810, 0x0 },
24067dbebe2SMarek Vasut { 0x800001C4, 0x180, 0x800001C4, 0x0 },
24167dbebe2SMarek Vasut { 0x44C00046, 0x0, 0x44C00046, 0x0 },
24267dbebe2SMarek Vasut { 0x0, 0x0, 0x0, 0x0 }, /* SMSTP6 is not present on Gen2 */
24367dbebe2SMarek Vasut { 0x05BFE618, 0x200000, 0x05BFE618, 0x0 },
24467dbebe2SMarek Vasut { 0x40C0FE85, 0x0, 0x40C0FE85, 0x0 },
24567dbebe2SMarek Vasut { 0xFF979FFF, 0x0, 0xFF979FFF, 0x0 },
24667dbebe2SMarek Vasut { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0x0 },
24767dbebe2SMarek Vasut { 0x000001C0, 0x0, 0x000001C0, 0x0 },
24867dbebe2SMarek Vasut };
24967dbebe2SMarek Vasut
r8a7791_get_pll_config(const u32 cpg_mode)25067dbebe2SMarek Vasut static const void *r8a7791_get_pll_config(const u32 cpg_mode)
25167dbebe2SMarek Vasut {
25267dbebe2SMarek Vasut return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
25367dbebe2SMarek Vasut }
25467dbebe2SMarek Vasut
25567dbebe2SMarek Vasut static const struct cpg_mssr_info r8a7791_cpg_mssr_info = {
25667dbebe2SMarek Vasut .core_clk = r8a7791_core_clks,
25767dbebe2SMarek Vasut .core_clk_size = ARRAY_SIZE(r8a7791_core_clks),
25867dbebe2SMarek Vasut .mod_clk = r8a7791_mod_clks,
25967dbebe2SMarek Vasut .mod_clk_size = ARRAY_SIZE(r8a7791_mod_clks),
26067dbebe2SMarek Vasut .mstp_table = r8a7791_mstp_table,
26167dbebe2SMarek Vasut .mstp_table_size = ARRAY_SIZE(r8a7791_mstp_table),
26267dbebe2SMarek Vasut .reset_node = "renesas,r8a7791-rst",
26367dbebe2SMarek Vasut .extal_usb_node = "usb_extal",
26467dbebe2SMarek Vasut .mod_clk_base = MOD_CLK_BASE,
26567dbebe2SMarek Vasut .clk_extal_id = CLK_EXTAL,
26667dbebe2SMarek Vasut .clk_extal_usb_id = CLK_USB_EXTAL,
26767dbebe2SMarek Vasut .pll0_div = 2,
26867dbebe2SMarek Vasut .get_pll_config = r8a7791_get_pll_config,
26967dbebe2SMarek Vasut };
27067dbebe2SMarek Vasut
27167dbebe2SMarek Vasut static const struct udevice_id r8a7791_clk_ids[] = {
27267dbebe2SMarek Vasut {
27367dbebe2SMarek Vasut .compatible = "renesas,r8a7791-cpg-mssr",
27467dbebe2SMarek Vasut .data = (ulong)&r8a7791_cpg_mssr_info
27567dbebe2SMarek Vasut },
27667dbebe2SMarek Vasut {
27767dbebe2SMarek Vasut .compatible = "renesas,r8a7793-cpg-mssr",
27867dbebe2SMarek Vasut .data = (ulong)&r8a7791_cpg_mssr_info
27967dbebe2SMarek Vasut },
28067dbebe2SMarek Vasut { }
28167dbebe2SMarek Vasut };
28267dbebe2SMarek Vasut
28367dbebe2SMarek Vasut U_BOOT_DRIVER(clk_r8a7791) = {
28467dbebe2SMarek Vasut .name = "clk_r8a7791",
28567dbebe2SMarek Vasut .id = UCLASS_CLK,
28667dbebe2SMarek Vasut .of_match = r8a7791_clk_ids,
28767dbebe2SMarek Vasut .priv_auto_alloc_size = sizeof(struct gen2_clk_priv),
28867dbebe2SMarek Vasut .ops = &gen2_clk_ops,
28967dbebe2SMarek Vasut .probe = gen2_clk_probe,
29067dbebe2SMarek Vasut .remove = gen2_clk_remove,
29167dbebe2SMarek Vasut };
292