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Searched refs:pir (Results 1 – 25 of 42) sorted by relevance

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/openbmc/qemu/include/hw/ppc/
H A Dpnv_chip.h106 #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) argument
107 #define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) argument
140 #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) argument
141 #define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) argument
142 #define PNV10_PIR2THREAD(pir) (((pir) & 0x7f)) argument
161 uint32_t *pir, uint32_t *tir);
H A Dpnv_core.h61 uint32_t pir; member
H A Dopenpic.h156 uint32_t pir; /* Processor initialization register */ member
H A Dppc.h7 PowerPCCPU *ppc_get_vcpu_by_pir(int pir);
H A Dpnv.h61 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
/openbmc/u-boot/drivers/ram/stm32mp1/
H A Dstm32mp1_ddr.c266 void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir) in stm32mp1_ddrphy_init() argument
268 pir |= DDRPHYC_PIR_INIT; in stm32mp1_ddrphy_init()
269 writel(pir, &phy->pir); in stm32mp1_ddrphy_init()
271 (u32)&phy->pir, pir, readl(&phy->pir)); in stm32mp1_ddrphy_init()
367 u32 pir; in stm32mp1_ddr_init() local
448 pir = DDRPHYC_PIR_DLLSRST | DDRPHYC_PIR_DLLLOCK | DDRPHYC_PIR_ZCAL | in stm32mp1_ddr_init()
452 pir |= DDRPHYC_PIR_DRAMRST; /* only for DDR3 */ in stm32mp1_ddr_init()
454 stm32mp1_ddrphy_init(priv->phy, pir); in stm32mp1_ddr_init()
H A Dstm32mp1_ddr.h176 void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir);
/openbmc/qemu/tests/qtest/
H A Dpnv-xive2-test.c67 static void set_tima8(QTestState *qts, uint32_t pir, uint32_t offset, in set_tima8() argument
72 ic_addr = XIVE_IC_TM_INDIRECT + (pir << XIVE_PAGE_SHIFT); in set_tima8()
76 static void set_tima32(QTestState *qts, uint32_t pir, uint32_t offset, in set_tima32() argument
81 ic_addr = XIVE_IC_TM_INDIRECT + (pir << XIVE_PAGE_SHIFT); in set_tima32()
85 static uint8_t get_tima8(QTestState *qts, uint32_t pir, uint32_t offset) in get_tima8() argument
89 ic_addr = XIVE_IC_TM_INDIRECT + (pir << XIVE_PAGE_SHIFT); in get_tima8()
93 static uint16_t get_tima16(QTestState *qts, uint32_t pir, uint32_t offset) in get_tima16() argument
97 ic_addr = XIVE_IC_TM_INDIRECT + (pir << XIVE_PAGE_SHIFT); in get_tima16()
101 static uint32_t get_tima32(QTestState *qts, uint32_t pir, uint32_t offset) in get_tima32() argument
105 ic_addr = XIVE_IC_TM_INDIRECT + (pir << XIVE_PAGE_SHIFT); in get_tima32()
/openbmc/qemu/hw/ppc/
H A Dppce500_spin.c46 uint32_t pir; member
68 stl_p(&info->pir, i); in spin_reset()
82 stl_p(&curspin->pir, env->spr[SPR_BOOKE_PIR]); in spin_kick()
H A Dpnv.c151 uint32_t pir, tir; in pnv_dt_core() local
162 pnv_cc->get_pir_tir(chip, pc->hwid, 0, &pir, &tir); in pnv_dt_core()
167 nodename = g_strdup_printf("%s@%x", dc->fw_name, pir); in pnv_dt_core()
174 _FDT((fdt_setprop_cell(fdt, offset, "reg", pir))); in pnv_dt_core()
175 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pir))); in pnv_dt_core()
249 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL); in pnv_dt_core()
250 servers_prop[i * 2] = cpu_to_be32(pir); in pnv_dt_core()
252 pnv_cc->get_pir_tir(chip, pc->hwid + 1, i, &pir, NULL); in pnv_dt_core()
253 servers_prop[i * 2 + 1] = cpu_to_be32(pir); in pnv_dt_core()
261 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL); in pnv_dt_core()
[all …]
H A Dpnv_core.c309 uint32_t pir, tir; in pnv_core_cpu_realize() local
325 pcc->get_pir_tir(pc->chip, core_hwid, thread_index, &pir, &tir); in pnv_core_cpu_realize()
326 pir_spr->default_value = pir; in pnv_core_cpu_realize()
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dmp.c48 out_be32(&pic->pir, 1 << nr); in cpu_reset()
50 (void)in_be32(&pic->pir); in cpu_reset()
51 out_be32(&pic->pir, 0x0); in cpu_reset()
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun8i_a23.c231 writel(0x00000003, &mctl_phy->pir); in mctl_init()
239 writel(0x000005f3, &mctl_phy->pir); in mctl_init()
247 writel(0x5f3, &mctl_phy->pir); in mctl_init()
H A Ddram_sun6i.c159 setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); in mctl_channel_init()
160 writel(MCTL_PIR_STEP1, &mctl_phy->pir); in mctl_channel_init()
190 setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); in mctl_channel_init()
191 writel(MCTL_PIR_STEP2, &mctl_phy->pir); in mctl_channel_init()
H A Ddram_sunxi_dw.c23 writel(val | PIR_INIT, &mctl_ctl->pir); in mctl_phy_init()
286 writel(PIR_CLRSR, &mctl_ctl->pir); in mctl_h3_zq_calibration_quirk()
313 writel(PIR_CLRSR, &mctl_ctl->pir); in mctl_h3_zq_calibration_quirk()
319 writel(PIR_CLRSR, &mctl_ctl->pir); in mctl_h3_zq_calibration_quirk()
H A Ddram_sun9i.c750 clrsetbits_le32(&mctl_phy->pir, MCTL_PIR_MASK, 0x20df3); in mctl_channel_init()
752 clrsetbits_le32(&mctl_phy->pir, MCTL_PIR_MASK, 0x2c573); in mctl_channel_init()
757 while ((readl(&mctl_phy->pir) & MCTL_PIR_INIT) != MCTL_PIR_INIT) { in mctl_channel_init()
/openbmc/qemu/hw/intc/
H A Dpnv_xive2.c420 int pir = pnv_xive2_get_current_pir(xive); in pnv_xive2_inject_notify() local
421 int thread_nr = PNV10_PIR2THREAD(pir); in pnv_xive2_inject_notify()
422 int thread_topo_id = PNV10_PIR2CHIP(pir); in pnv_xive2_inject_notify()
635 int pir = ppc_cpu_pir(cpu); in pnv_xive2_is_cpu_enabled() local
636 uint32_t fc = PNV10_PIR2FUSEDCORE(pir); in pnv_xive2_is_cpu_enabled()
638 uint32_t bit = pir & 0x3f; in pnv_xive2_is_cpu_enabled()
793 int pir = ppc_cpu_pir(cpu); in pnv_xive2_tm_get_xive() local
798 xive2_error(xive, "IC: CPU %x is not enabled", pir); in pnv_xive2_tm_get_xive()
2166 static XiveTCTX *pnv_xive2_get_indirect_tctx(PnvXive2 *xive, uint32_t pir) in pnv_xive2_get_indirect_tctx() argument
2171 cpu = pnv_chip_find_cpu(chip, pir); in pnv_xive2_get_indirect_tctx()
[all …]
H A Dpnv_xive.c465 int pir = ppc_cpu_pir(cpu); in pnv_xive_is_cpu_enabled() local
466 uint32_t fc = PNV9_PIR2FUSEDCORE(pir); in pnv_xive_is_cpu_enabled()
468 uint32_t bit = pir & 0x3f; in pnv_xive_is_cpu_enabled()
548 int pir = ppc_cpu_pir(cpu); in pnv_xive_tm_get_xive() local
553 xive_error(xive, "IC: CPU %x is not enabled", pir); in pnv_xive_tm_get_xive()
1578 int pir; in pnv_xive_get_indirect_tctx() local
1585 pir = (chip->chip_id << 8) | GETFIELD(PC_TCTXT_INDIR_THRDID, tctxt_indir); in pnv_xive_get_indirect_tctx()
1586 cpu = pnv_chip_find_cpu(chip, pir); in pnv_xive_get_indirect_tctx()
1588 xive_error(xive, "IC: invalid PIR %x for indirect access", pir); in pnv_xive_get_indirect_tctx()
1594 xive_error(xive, "IC: CPU %x is not enabled", pir); in pnv_xive_get_indirect_tctx()
H A Dopenpic.c596 if ((val & (1 << idx)) && !(opp->pir & (1 << idx))) { in openpic_gbl_write()
600 } else if (!(val & (1 << idx)) && (opp->pir & (1 << idx))) { in openpic_gbl_write()
606 opp->pir = val; in openpic_gbl_write()
1265 opp->pir = 0; in openpic_reset()
1474 VMSTATE_UINT32(pir, OpenPICState),
/openbmc/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3188.c159 setbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set()
168 clrbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set()
300 setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST in phy_init()
328 setbits_le32(&publ->pir, in memory_init()
436 setbits_le32(&publ->pir, PIR_CLRSR); in data_training()
439 setbits_le32(&publ->pir, in data_training()
H A Dsdram_rk3288.c158 setbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set()
167 clrbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set()
358 setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST in phy_init()
386 setbits_le32(&publ->pir, in memory_init()
494 setbits_le32(&publ->pir, PIR_CLRSR); in data_training()
497 setbits_le32(&publ->pir, in data_training()
/openbmc/qemu/target/ppc/
H A Dtcg-excp_helper.c688 int pir = rb & DBELL_PIRTAG_MASK; in helper_msgsnd() local
700 if ((rb & DBELL_BRDCAST_MASK) || (cenv->spr[SPR_BOOKE_PIR] == pir)) { in helper_msgsnd()
768 int pir = rb & DBELL_PROCIDTAG_MASK; in helper_book3s_msgsnd() local
784 cpu = ppc_get_vcpu_by_pir(pir); in helper_book3s_msgsnd()
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddram_sun8i_a33.h66 u32 pir; /* 0x00 */ member
H A Ddram_sunxi_dw.h82 u32 pir; /* 0x00 PHY initialization register */ member
H A Ddram_sun8i_a83t.h66 u32 pir; /* 0x00 */ member

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