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Searched refs:pin (Results 1 – 25 of 484) sorted by relevance

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/openbmc/u-boot/board/sunxi/
H A Dgmac.c11 int pin; local
37 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) {
39 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
43 if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
46 sunxi_gpio_set_cfgpin(pin, SUN7I_GPA_GMAC);
47 sunxi_gpio_set_drv(pin, 3);
51 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
52 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
53 sunxi_gpio_set_drv(pin, 3);
55 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
[all …]
H A Dboard.c334 unsigned int pin; in nand_pinmux_setup() local
336 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++) in nand_pinmux_setup()
337 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); in nand_pinmux_setup()
340 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++) in nand_pinmux_setup()
341 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); in nand_pinmux_setup()
376 unsigned int pin; in mmc_pinmux_setup() local
382 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { in mmc_pinmux_setup()
383 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0); in mmc_pinmux_setup()
384 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); in mmc_pinmux_setup()
385 sunxi_gpio_set_drv(pin, 2); in mmc_pinmux_setup()
[all …]
/openbmc/u-boot/drivers/gpio/
H A Dkw_gpio.c24 void __set_direction(unsigned pin, int input) in __set_direction() argument
28 u = readl(GPIO_IO_CONF(pin)); in __set_direction()
30 u |= 1 << (pin & 31); in __set_direction()
32 u &= ~(1 << (pin & 31)); in __set_direction()
33 writel(u, GPIO_IO_CONF(pin)); in __set_direction()
35 u = readl(GPIO_IO_CONF(pin)); in __set_direction()
38 static void __set_level(unsigned pin, int high) in __set_level() argument
42 u = readl(GPIO_OUT(pin)); in __set_level()
44 u |= 1 << (pin & 31); in __set_level()
46 u &= ~(1 << (pin & 31)); in __set_level()
[all …]
H A Dat91_gpio.c58 int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup) in at91_set_pio_pullup() argument
62 if (at91_port && (pin < GPIO_PER_BANK)) in at91_set_pio_pullup()
63 at91_set_port_pullup(at91_port, pin, use_pullup); in at91_set_pio_pullup()
71 int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup) in at91_set_pio_periph() argument
76 if (at91_port && (pin < GPIO_PER_BANK)) { in at91_set_pio_periph()
77 mask = 1 << pin; in at91_set_pio_periph()
79 at91_set_pio_pullup(port, pin, use_pullup); in at91_set_pio_periph()
89 int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup) in at91_set_a_periph() argument
94 if (at91_port && (pin < GPIO_PER_BANK)) { in at91_set_a_periph()
95 mask = 1 << pin; in at91_set_a_periph()
[all …]
H A Daxp_gpio.c19 static int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val);
21 static u8 axp_get_gpio_ctrl_reg(unsigned pin) in axp_get_gpio_ctrl_reg() argument
23 switch (pin) { in axp_get_gpio_ctrl_reg()
36 static int axp_gpio_direction_input(struct udevice *dev, unsigned pin) in axp_gpio_direction_input() argument
40 switch (pin) { in axp_gpio_direction_input()
46 reg = axp_get_gpio_ctrl_reg(pin); in axp_gpio_direction_input()
54 static int axp_gpio_direction_output(struct udevice *dev, unsigned pin, in axp_gpio_direction_output() argument
60 switch (pin) { in axp_gpio_direction_output()
69 return axp_gpio_set_value(dev, pin, val); in axp_gpio_direction_output()
72 reg = axp_get_gpio_ctrl_reg(pin); in axp_gpio_direction_output()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsama5d3_lcd.dtsi42 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
43 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
44 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
45 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
46 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
47 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
48 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
49 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
50 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
51 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
[all …]
H A Dat91sam9x5_lcd.dtsi42 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
43 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
44 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
45 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
46 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
47 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
48 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
49 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
50 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
51 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
[all …]
/openbmc/u-boot/arch/arm/mach-kirkwood/include/mach/
H A Dgpio.h18 #define GPIO_OFF(pin) (((pin) >> 5) ? 0x0040 : 0x0000) argument
19 #define GPIO_OUT(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x00) argument
20 #define GPIO_IO_CONF(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x04) argument
21 #define GPIO_BLINK_EN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x08) argument
22 #define GPIO_IN_POL(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x0c) argument
23 #define GPIO_DATA_IN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x10) argument
24 #define GPIO_EDGE_CAUSE(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x14) argument
25 #define GPIO_EDGE_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x18) argument
26 #define GPIO_LEVEL_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x1c) argument
32 void kw_gpio_set_valid(unsigned pin, int mode);
[all …]
/openbmc/u-boot/arch/arm/cpu/arm920t/imx/
H A Dgeneric.c20 unsigned int pin = gpio_mode & GPIO_PIN_MASK; in imx_gpio_mode() local
27 PUEN(port) |= (1<<pin); in imx_gpio_mode()
29 PUEN(port) &= ~(1<<pin); in imx_gpio_mode()
33 DDIR(port) |= 1<<pin; in imx_gpio_mode()
35 DDIR(port) &= ~(1<<pin); in imx_gpio_mode()
39 GPR(port) |= (1<<pin); in imx_gpio_mode()
41 GPR(port) &= ~(1<<pin); in imx_gpio_mode()
45 GIUS(port) |= (1<<pin); in imx_gpio_mode()
47 GIUS(port) &= ~(1<<pin); in imx_gpio_mode()
53 if(pin<16) { in imx_gpio_mode()
[all …]
/openbmc/u-boot/board/micronas/vct/
H A Dgpio.c16 #define GPIO_MODULE(pin) ((pin) >> 5) argument
22 #define MASK(pin) (1 << ((pin) & 0x1F)) argument
39 int vct_gpio_dir(int pin, int dir) in vct_gpio_dir() argument
43 gpio_base = BASE_ADDR(GPIO_MODULE(pin)); in vct_gpio_dir()
46 clrsetbits(GPIO_SWPORTA_DDR(gpio_base), MASK(pin), 0); in vct_gpio_dir()
48 clrsetbits(GPIO_SWPORTA_DDR(gpio_base), 0, MASK(pin)); in vct_gpio_dir()
53 void vct_gpio_set(int pin, int val) in vct_gpio_set() argument
57 gpio_base = BASE_ADDR(GPIO_MODULE(pin)); in vct_gpio_set()
60 clrsetbits(GPIO_SWPORTA_DR(gpio_base), MASK(pin), 0); in vct_gpio_set()
62 clrsetbits(GPIO_SWPORTA_DR(gpio_base), 0, MASK(pin)); in vct_gpio_set()
[all …]
H A Dtop.c26 static TOP_PINMUX_t top_read_pin(int pin) in top_read_pin() argument
30 switch (pin) { in top_read_pin()
57 ((pin - 10) * 4)); in top_read_pin()
60 reg.reg = reg_read(TOP_BASE + (pin * 4)); in top_read_pin()
67 static void top_write_pin(int pin, TOP_PINMUX_t reg) in top_write_pin() argument
70 switch (pin) { in top_write_pin()
91 ((pin - 10) * 4), reg.reg); in top_write_pin()
94 reg_write(TOP_BASE + (pin * 4), reg.reg); in top_write_pin()
99 int top_set_pin(int pin, int func) in top_set_pin() argument
104 if ((pin < 0) || (pin > 170) || (func < 0) || (func > 3)) in top_set_pin()
[all …]
/openbmc/qemu/tests/qtest/
H A Dstm32l4x5_gpio-test.c86 static inline void *test_data(uint32_t gpio_addr, uint8_t pin) in test_data() argument
88 return (void *)(uintptr_t)((gpio_addr & GPIO_ADDR_MASK) | (pin & PIN_MASK)); in test_data()
105 unsigned int pin, uint32_t value) in gpio_set_bit() argument
107 uint32_t mask = 0xFFFFFFFF & ~(0x1 << pin); in gpio_set_bit()
108 gpio_writel(gpio, reg, (gpio_readl(gpio, reg) & mask) | value << pin); in gpio_set_bit()
112 unsigned int pin, uint32_t value) in gpio_set_2bits() argument
114 uint32_t offset = 2 * pin; in gpio_set_2bits()
279 unsigned int pin = test_pin(data); in test_gpio_output_mode() local
286 gpio_set_bit(gpio, ODR, pin, 1); in test_gpio_output_mode()
288 g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin)); in test_gpio_output_mode()
[all …]
/openbmc/u-boot/board/LaCie/common/
H A Dcpld-gpio-bus.c19 int pin; in cpld_gpio_bus_set_addr() local
21 for (pin = 0; pin < bus->num_addr; pin++) in cpld_gpio_bus_set_addr()
22 kw_gpio_set_value(bus->addr[pin], (addr >> pin) & 1); in cpld_gpio_bus_set_addr()
27 int pin; in cpld_gpio_bus_set_data() local
29 for (pin = 0; pin < bus->num_data; pin++) in cpld_gpio_bus_set_data()
30 kw_gpio_set_value(bus->data[pin], (data >> pin) & 1); in cpld_gpio_bus_set_data()
/openbmc/u-boot/arch/arm/mach-tegra/
H A Dpinmux-common.c12 #define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PMUX_PINGRP_COUNT)) argument
95 #define REG(pin) _R(0x3000 + ((pin) * 4)) argument
97 #define MUX_REG(pin) REG(pin) argument
98 #define MUX_SHIFT(pin) 0 argument
100 #define PULL_REG(pin) REG(pin) argument
101 #define PULL_SHIFT(pin) 2 argument
103 #define TRI_REG(pin) REG(pin) argument
104 #define TRI_SHIFT(pin) 4 argument
157 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func) in pinmux_set_func() argument
159 u32 *reg = MUX_REG(pin); in pinmux_set_func()
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Diopin_8xx.h19 u_char pin:5; /* port pin (0-31) */ member
35 setbits_be16(datp, 1 << (15 - iopin->pin)); in iopin_set_high()
39 setbits_be32(datp, 1 << (31 - iopin->pin)); in iopin_set_high()
43 setbits_be16(datp, 1 << (15 - iopin->pin)); in iopin_set_high()
47 setbits_be16(datp, 1 << (15 - iopin->pin)); in iopin_set_high()
58 clrbits_be16(datp, 1 << (15 - iopin->pin)); in iopin_set_low()
62 clrbits_be32(datp, 1 << (31 - iopin->pin)); in iopin_set_low()
66 clrbits_be16(datp, 1 << (15 - iopin->pin)); in iopin_set_low()
70 clrbits_be16(datp, 1 << (15 - iopin->pin)); in iopin_set_low()
81 return (in_be16(datp) >> (15 - iopin->pin)) & 1; in iopin_is_high()
[all …]
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Dpinmux.c20 void sunxi_gpio_set_cfgpin(u32 pin, u32 val) in sunxi_gpio_set_cfgpin() argument
22 u32 bank = GPIO_BANK(pin); in sunxi_gpio_set_cfgpin()
25 sunxi_gpio_set_cfgbank(pio, pin, val); in sunxi_gpio_set_cfgpin()
40 int sunxi_gpio_get_cfgpin(u32 pin) in sunxi_gpio_get_cfgpin() argument
42 u32 bank = GPIO_BANK(pin); in sunxi_gpio_get_cfgpin()
45 return sunxi_gpio_get_cfgbank(pio, pin); in sunxi_gpio_get_cfgpin()
48 int sunxi_gpio_set_drv(u32 pin, u32 val) in sunxi_gpio_set_drv() argument
50 u32 bank = GPIO_BANK(pin); in sunxi_gpio_set_drv()
51 u32 index = GPIO_DRV_INDEX(pin); in sunxi_gpio_set_drv()
52 u32 offset = GPIO_DRV_OFFSET(pin); in sunxi_gpio_set_drv()
[all …]
/openbmc/u-boot/drivers/pinctrl/mscc/
H A DKconfig10 bool "Microsemi ocelot family pin control driver"
12 Support pin multiplexing and pin configuration control on
19 bool "Microsemi luton family pin control driver"
21 Support pin multiplexing and pin configuration control on
28 bool "Microsemi jr2 family pin control driver"
30 Support pin multiplexing and pin configuration control on
37 bool "Microsemi servalt family pin control driver"
39 Support pin multiplexing and pin configuration control on
46 bool "Microsemi serval family pin control driver"
48 Support pin multiplexing and pin configuration control on
/openbmc/u-boot/drivers/pinctrl/rockchip/
H A Dpinctrl-rk322x.c18 .pin = 26,
25 .pin = 21,
32 .pin = 27,
39 .pin = 30,
46 .pin = 28,
53 .pin = 12,
60 .pin = 26,
67 .pin = 11,
74 .pin = 1,
81 .pin = 2,
[all …]
H A Dpinctrl-rk3128.c17 .pin = 20,
23 .pin = 21,
29 .pin = 22,
35 .pin = 23,
41 .pin = 24,
52 .pin = 10,
59 .pin = 27,
66 .pin = 13,
73 .pin = 5,
80 .pin = 14,
[all …]
H A Dpinctrl-rockchip-core.c19 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) in rockchip_verify_config() argument
29 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) { in rockchip_verify_config()
30 debug("pin conf pin %d >= %d\n", pin, in rockchip_verify_config()
38 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, in rockchip_get_recalced_mux() argument
49 data->pin == pin) in rockchip_get_recalced_mux()
61 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, in rockchip_get_mux_route() argument
72 data->pin == pin && data->func == mux) in rockchip_get_mux_route()
85 static int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask) in rockchip_get_mux_data() argument
90 if ((pin % 8) >= 4) in rockchip_get_mux_data()
92 *bit = (pin % 4) * 4; in rockchip_get_mux_data()
[all …]
/openbmc/u-boot/arch/mips/mach-jz47xx/jz4780/
H A Dgpio.c12 int pin = gpio % 32; in jz47xx_gpio_get_value() local
14 return readl(gpio_regs + GPIO_PXPIN(port)) & BIT(pin); in jz47xx_gpio_get_value()
21 int pin = gpio % 32; in jz47xx_gpio_direction_input() local
23 writel(BIT(pin), gpio_regs + GPIO_PXINTC(port)); in jz47xx_gpio_direction_input()
24 writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port)); in jz47xx_gpio_direction_input()
25 writel(BIT(pin), gpio_regs + GPIO_PXPAT1S(port)); in jz47xx_gpio_direction_input()
32 int pin = gpio % 32; in jz47xx_gpio_direction_output() local
34 writel(BIT(pin), gpio_regs + GPIO_PXINTC(port)); in jz47xx_gpio_direction_output()
35 writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port)); in jz47xx_gpio_direction_output()
36 writel(BIT(pin), gpio_regs + GPIO_PXPAT1C(port)); in jz47xx_gpio_direction_output()
[all …]
/openbmc/u-boot/drivers/pinctrl/renesas/
H A DKconfig4 bool "Renesas pin control drivers"
10 bool "Renesas RCar Gen2 R8A7790 pin control driver"
13 Support pin multiplexing control on Renesas RCar Gen3 R8A7790 SoCs.
16 the GPIO definitions and pin control functions for each available
20 bool "Renesas RCar Gen2 R8A7791 pin control driver"
23 Support pin multiplexing control on Renesas RCar Gen3 R8A7791 SoCs.
26 the GPIO definitions and pin control functions for each available
30 bool "Renesas RCar Gen2 R8A7792 pin control driver"
33 Support pin multiplexing control on Renesas RCar Gen3 R8A7792 SoCs.
36 the GPIO definitions and pin control functions for each available
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dgpio.h80 #define GPIO_BANK(pin) ((pin) >> 5) argument
81 #define GPIO_NUM(pin) ((pin) & 0x1f) argument
83 #define GPIO_CFG_INDEX(pin) (((pin) & 0x1f) >> 3) argument
84 #define GPIO_CFG_OFFSET(pin) ((((pin) & 0x1f) & 0x7) << 2) argument
86 #define GPIO_DRV_INDEX(pin) (((pin) & 0x1f) >> 4) argument
87 #define GPIO_DRV_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1) argument
89 #define GPIO_PULL_INDEX(pin) (((pin) & 0x1f) >> 4) argument
90 #define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1) argument
233 void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
235 int sunxi_gpio_get_cfgpin(u32 pin);
[all …]
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91_pio.h130 int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup);
131 int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup);
132 int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup);
133 int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on);
134 int at91_set_pio_output(unsigned port, unsigned pin, int value);
135 int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup);
136 int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup);
137 int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on);
138 int at91_set_pio_value(unsigned port, unsigned pin, int value);
139 int at91_get_pio_value(unsigned port, unsigned pin);
[all …]
/openbmc/u-boot/drivers/misc/
H A Dali512x.c328 void ali512x_cio_function(int pin, int special, int inv, int input) in ali512x_cio_function() argument
334 if (pin >= 10 && pin <= 17) { in ali512x_cio_function()
335 addr = 0xe0+(pin&7); in ali512x_cio_function()
336 } else if (pin >= 20 && pin <= 25) { in ali512x_cio_function()
337 addr = 0xe8+(pin&7); in ali512x_cio_function()
338 } else if (pin >= 30 && pin <= 37) { in ali512x_cio_function()
339 addr = 0xf5+(pin&7); in ali512x_cio_function()
366 void ali512x_cio_out(int pin, int value) in ali512x_cio_out() argument
372 reg = pin/10; in ali512x_cio_out()
373 bit = 1 << (pin%10); in ali512x_cio_out()
[all …]

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