1*e7ae4cf2SDavid Wu // SPDX-License-Identifier: GPL-2.0+
2*e7ae4cf2SDavid Wu /*
3*e7ae4cf2SDavid Wu * (C) Copyright 2019 Rockchip Electronics Co., Ltd
4*e7ae4cf2SDavid Wu */
5*e7ae4cf2SDavid Wu
6*e7ae4cf2SDavid Wu #include <common.h>
7*e7ae4cf2SDavid Wu #include <dm.h>
8*e7ae4cf2SDavid Wu #include <dm/pinctrl.h>
9*e7ae4cf2SDavid Wu #include <regmap.h>
10*e7ae4cf2SDavid Wu #include <syscon.h>
11*e7ae4cf2SDavid Wu
12*e7ae4cf2SDavid Wu #include "pinctrl-rockchip.h"
13*e7ae4cf2SDavid Wu
14*e7ae4cf2SDavid Wu static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
15*e7ae4cf2SDavid Wu {
16*e7ae4cf2SDavid Wu .num = 2,
17*e7ae4cf2SDavid Wu .pin = 20,
18*e7ae4cf2SDavid Wu .reg = 0xe8,
19*e7ae4cf2SDavid Wu .bit = 0,
20*e7ae4cf2SDavid Wu .mask = 0x7
21*e7ae4cf2SDavid Wu }, {
22*e7ae4cf2SDavid Wu .num = 2,
23*e7ae4cf2SDavid Wu .pin = 21,
24*e7ae4cf2SDavid Wu .reg = 0xe8,
25*e7ae4cf2SDavid Wu .bit = 4,
26*e7ae4cf2SDavid Wu .mask = 0x7
27*e7ae4cf2SDavid Wu }, {
28*e7ae4cf2SDavid Wu .num = 2,
29*e7ae4cf2SDavid Wu .pin = 22,
30*e7ae4cf2SDavid Wu .reg = 0xe8,
31*e7ae4cf2SDavid Wu .bit = 8,
32*e7ae4cf2SDavid Wu .mask = 0x7
33*e7ae4cf2SDavid Wu }, {
34*e7ae4cf2SDavid Wu .num = 2,
35*e7ae4cf2SDavid Wu .pin = 23,
36*e7ae4cf2SDavid Wu .reg = 0xe8,
37*e7ae4cf2SDavid Wu .bit = 12,
38*e7ae4cf2SDavid Wu .mask = 0x7
39*e7ae4cf2SDavid Wu }, {
40*e7ae4cf2SDavid Wu .num = 2,
41*e7ae4cf2SDavid Wu .pin = 24,
42*e7ae4cf2SDavid Wu .reg = 0xd4,
43*e7ae4cf2SDavid Wu .bit = 12,
44*e7ae4cf2SDavid Wu .mask = 0x7
45*e7ae4cf2SDavid Wu },
46*e7ae4cf2SDavid Wu };
47*e7ae4cf2SDavid Wu
48*e7ae4cf2SDavid Wu static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
49*e7ae4cf2SDavid Wu {
50*e7ae4cf2SDavid Wu /* spi-0 */
51*e7ae4cf2SDavid Wu .bank_num = 1,
52*e7ae4cf2SDavid Wu .pin = 10,
53*e7ae4cf2SDavid Wu .func = 1,
54*e7ae4cf2SDavid Wu .route_offset = 0x144,
55*e7ae4cf2SDavid Wu .route_val = BIT(16 + 3) | BIT(16 + 4),
56*e7ae4cf2SDavid Wu }, {
57*e7ae4cf2SDavid Wu /* spi-1 */
58*e7ae4cf2SDavid Wu .bank_num = 1,
59*e7ae4cf2SDavid Wu .pin = 27,
60*e7ae4cf2SDavid Wu .func = 3,
61*e7ae4cf2SDavid Wu .route_offset = 0x144,
62*e7ae4cf2SDavid Wu .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
63*e7ae4cf2SDavid Wu }, {
64*e7ae4cf2SDavid Wu /* spi-2 */
65*e7ae4cf2SDavid Wu .bank_num = 0,
66*e7ae4cf2SDavid Wu .pin = 13,
67*e7ae4cf2SDavid Wu .func = 2,
68*e7ae4cf2SDavid Wu .route_offset = 0x144,
69*e7ae4cf2SDavid Wu .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
70*e7ae4cf2SDavid Wu }, {
71*e7ae4cf2SDavid Wu /* i2s-0 */
72*e7ae4cf2SDavid Wu .bank_num = 1,
73*e7ae4cf2SDavid Wu .pin = 5,
74*e7ae4cf2SDavid Wu .func = 1,
75*e7ae4cf2SDavid Wu .route_offset = 0x144,
76*e7ae4cf2SDavid Wu .route_val = BIT(16 + 5),
77*e7ae4cf2SDavid Wu }, {
78*e7ae4cf2SDavid Wu /* i2s-1 */
79*e7ae4cf2SDavid Wu .bank_num = 0,
80*e7ae4cf2SDavid Wu .pin = 14,
81*e7ae4cf2SDavid Wu .func = 1,
82*e7ae4cf2SDavid Wu .route_offset = 0x144,
83*e7ae4cf2SDavid Wu .route_val = BIT(16 + 5) | BIT(5),
84*e7ae4cf2SDavid Wu }, {
85*e7ae4cf2SDavid Wu /* emmc-0 */
86*e7ae4cf2SDavid Wu .bank_num = 1,
87*e7ae4cf2SDavid Wu .pin = 22,
88*e7ae4cf2SDavid Wu .func = 2,
89*e7ae4cf2SDavid Wu .route_offset = 0x144,
90*e7ae4cf2SDavid Wu .route_val = BIT(16 + 6),
91*e7ae4cf2SDavid Wu }, {
92*e7ae4cf2SDavid Wu /* emmc-1 */
93*e7ae4cf2SDavid Wu .bank_num = 2,
94*e7ae4cf2SDavid Wu .pin = 4,
95*e7ae4cf2SDavid Wu .func = 2,
96*e7ae4cf2SDavid Wu .route_offset = 0x144,
97*e7ae4cf2SDavid Wu .route_val = BIT(16 + 6) | BIT(6),
98*e7ae4cf2SDavid Wu },
99*e7ae4cf2SDavid Wu };
100*e7ae4cf2SDavid Wu
101*e7ae4cf2SDavid Wu #define RK3128_PULL_OFFSET 0x118
102*e7ae4cf2SDavid Wu #define RK3128_PULL_PINS_PER_REG 16
103*e7ae4cf2SDavid Wu #define RK3128_PULL_BANK_STRIDE 8
104*e7ae4cf2SDavid Wu
rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)105*e7ae4cf2SDavid Wu static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
106*e7ae4cf2SDavid Wu int pin_num, struct regmap **regmap,
107*e7ae4cf2SDavid Wu int *reg, u8 *bit)
108*e7ae4cf2SDavid Wu {
109*e7ae4cf2SDavid Wu struct rockchip_pinctrl_priv *priv = bank->priv;
110*e7ae4cf2SDavid Wu
111*e7ae4cf2SDavid Wu *regmap = priv->regmap_base;
112*e7ae4cf2SDavid Wu *reg = RK3128_PULL_OFFSET;
113*e7ae4cf2SDavid Wu *reg += bank->bank_num * RK3128_PULL_BANK_STRIDE;
114*e7ae4cf2SDavid Wu *reg += ((pin_num / RK3128_PULL_PINS_PER_REG) * 4);
115*e7ae4cf2SDavid Wu
116*e7ae4cf2SDavid Wu *bit = pin_num % RK3128_PULL_PINS_PER_REG;
117*e7ae4cf2SDavid Wu }
118*e7ae4cf2SDavid Wu
119*e7ae4cf2SDavid Wu static struct rockchip_pin_bank rk3128_pin_banks[] = {
120*e7ae4cf2SDavid Wu PIN_BANK(0, 32, "gpio0"),
121*e7ae4cf2SDavid Wu PIN_BANK(1, 32, "gpio1"),
122*e7ae4cf2SDavid Wu PIN_BANK(2, 32, "gpio2"),
123*e7ae4cf2SDavid Wu PIN_BANK(3, 32, "gpio3"),
124*e7ae4cf2SDavid Wu };
125*e7ae4cf2SDavid Wu
126*e7ae4cf2SDavid Wu static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
127*e7ae4cf2SDavid Wu .pin_banks = rk3128_pin_banks,
128*e7ae4cf2SDavid Wu .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
129*e7ae4cf2SDavid Wu .label = "RK3128-GPIO",
130*e7ae4cf2SDavid Wu .type = RK3128,
131*e7ae4cf2SDavid Wu .grf_mux_offset = 0xa8,
132*e7ae4cf2SDavid Wu .iomux_recalced = rk3128_mux_recalced_data,
133*e7ae4cf2SDavid Wu .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
134*e7ae4cf2SDavid Wu .iomux_routes = rk3128_mux_route_data,
135*e7ae4cf2SDavid Wu .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
136*e7ae4cf2SDavid Wu .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
137*e7ae4cf2SDavid Wu };
138*e7ae4cf2SDavid Wu
139*e7ae4cf2SDavid Wu static const struct udevice_id rk3128_pinctrl_ids[] = {
140*e7ae4cf2SDavid Wu { .compatible = "rockchip,rk3128-pinctrl",
141*e7ae4cf2SDavid Wu .data = (ulong)&rk3128_pin_ctrl },
142*e7ae4cf2SDavid Wu { }
143*e7ae4cf2SDavid Wu };
144*e7ae4cf2SDavid Wu
145*e7ae4cf2SDavid Wu U_BOOT_DRIVER(pinctrl_rk3128) = {
146*e7ae4cf2SDavid Wu .name = "pinctrl_rk3128",
147*e7ae4cf2SDavid Wu .id = UCLASS_PINCTRL,
148*e7ae4cf2SDavid Wu .of_match = rk3128_pinctrl_ids,
149*e7ae4cf2SDavid Wu .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
150*e7ae4cf2SDavid Wu .ops = &rockchip_pinctrl_ops,
151*e7ae4cf2SDavid Wu #if !CONFIG_IS_ENABLED(OF_PLATDATA)
152*e7ae4cf2SDavid Wu .bind = dm_scan_fdt_dev,
153*e7ae4cf2SDavid Wu #endif
154*e7ae4cf2SDavid Wu .probe = rockchip_pinctrl_probe,
155*e7ae4cf2SDavid Wu };
156