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Searched refs:phases (Results 1 – 25 of 158) sorted by relevance

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/openbmc/qemu/hw/core/
H A Dresettable.c134 !!rc->phases.enter); in resettable_phase_enter()
135 if (rc->phases.enter) { in resettable_phase_enter()
136 rc->phases.enter(obj, type); in resettable_phase_enter()
160 trace_resettable_phase_hold_exec(obj, obj_typename, !!rc->phases.hold); in resettable_phase_hold()
161 if (rc->phases.hold) { in resettable_phase_hold()
162 rc->phases.hold(obj, type); in resettable_phase_hold()
183 trace_resettable_phase_exit_exec(obj, obj_typename, !!rc->phases.exit); in resettable_phase_exit()
184 if (rc->phases.exit) { in resettable_phase_exit()
185 rc->phases.exit(obj, type); in resettable_phase_exit()
255 *parent_phases = rc->phases; in resettable_class_set_parent_phases()
[all …]
/openbmc/qemu/scripts/coccinelle/
H A Dreset-type.cocci22 // either by directly assigning it to phases.hold or by calling
32 rc->phases.hold = holdfn;
65 rc->phases.exit = exitfn;
104 - rc->phases.phase(obj)@p
105 + rc->phases.phase(obj, RESET_TYPE_COLD)
114 - rc->phases.hold(obj)@p
115 + rc->phases.hold(obj, type)
121 - rc->phases.exit(obj)@p
122 + rc->phases.exit(obj, type)
/openbmc/phosphor-power/phosphor-regulators/docs/config_file/
H A Dlog_phase_fault.md9 A regulator may contain one or more redundant phases:
11 - An "N+2" regulator has two redundant phases
23 | n | Regulator has lost all redundant phases. The regulator is now at redundancy level N. …
H A Dphase_fault_detection.md8 one or more phases that perform the actual voltage regulation.
10 A regulator may have redundant phases. If a redundant phase fails, the regulator
/openbmc/linux/drivers/hwmon/pmbus/
H A Dmp2975.c232 return max_t(int, DIV_ROUND_CLOSEST(ret, data->info.phases[page]), in mp2975_read_phase()
356 ret = mp2975_data2reg_linear11(ret * info->phases[page] * 1000); in mp2973_read_word_data()
499 for (i = 0 ; i < info->phases[0]; i++) in mp2975_set_phase_rail1()
528 info->phases[0] = ret & GENMASK(3, 0); in mp2975_identify_multiphase()
538 if (info->phases[0] > data->max_phases[0]) in mp2975_identify_multiphase()
543 num_phases2 = min(data->max_phases[0] - info->phases[0], in mp2975_identify_multiphase()
545 if (info->phases[1] && info->phases[1] <= num_phases2) in mp2975_identify_multiphase()
596 if (info->phases[1]) in mp2975_identify_rails_vid()
624 if (info->phases[1]) in mp2973_identify_rails_vid()
934 data->info.phases[1] = ret; in mp2975_probe()
H A Dtps53679.c83 info->phases[0] = (ret & 0x07) + 1; in tps53679_identify_phases()
180 info->phases[0] = phases_a; in tps53676_identify()
183 info->phases[1] = phases_b; in tps53676_identify()
262 info->phases[0] = 6; in tps53679_probe()
H A Dmp2856.c272 data->info.phases[0] = (ret > data->max_phases[0]) ? in mp2856_identify_multiphase_rail1()
275 for (i = 0 ; i < data->info.phases[0]; i++) in mp2856_identify_multiphase_rail1()
292 data->info.phases[1] = (ret > data->max_phases[1]) ? in mp2856_identify_multiphase_rail2()
295 for (i = 0 ; i < data->info.phases[0]; i++) in mp2856_identify_multiphase_rail2()
H A Dpim4328.c187 info->phases[0] = 2; in pim4328_probe()
194 info->phases[0] = 2; in pim4328_probe()
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dhwmgr_ppt.h41 uint8_t phases; member
68 uint8_t phases; member
/openbmc/qemu/docs/devel/
H A Dreset.rst116 of an object is split into three well defined phases.
119 startup), all first phases of all objects are executed, then all second phases
120 and then all third phases.
122 The three phases are:
137 count is used to ensure phases are executed only when required. *enter* and
138 *hold* phases are executed only when asserting reset for the first time
159 phase of the reset; they are name ``phases.enter()``, ``phases.hold()`` and
160 ``phases.exit()``. They all take the object as parameter. The *enter* method
225 In the above example, we override all three phases. It is possible to override
234 phases which does nothing but call the parent class's implementation of the
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/openbmc/qemu/hw/sensor/
H A Disl_pmbus_vr.c250 rc->phases.exit = isl_pmbus_vr_exit_reset; in isl69260_class_init()
259 rc->phases.exit = raa228000_exit_reset; in raa228000_class_init()
268 rc->phases.exit = isl_pmbus_vr_exit_reset; in raa229004_class_init()
277 rc->phases.exit = isl69259_exit_reset; in isl69259_class_init()
/openbmc/linux/drivers/mmc/host/
H A Dsdhci-of-aspeed.c200 const struct mmc_clk_phase *phases, in aspeed_sdhci_phases_to_taps() argument
203 taps->valid = phases->valid; in aspeed_sdhci_phases_to_taps()
205 if (!phases->valid) in aspeed_sdhci_phases_to_taps()
208 taps->in = aspeed_sdhci_phase_to_tap(dev, rate, phases->in_deg); in aspeed_sdhci_phases_to_taps()
209 taps->out = aspeed_sdhci_phase_to_tap(dev, rate, phases->out_deg); in aspeed_sdhci_phases_to_taps()
/openbmc/linux/drivers/gpu/drm/i915/gem/
H A Di915_gem_pm.c133 struct list_head *phases[] = { in i915_gem_suspend_late() local
167 for (phase = phases; *phase; phase++) { in i915_gem_suspend_late()
/openbmc/linux/Documentation/hwmon/
H A Dmp2888.rst46 - 'n' is number of configured phases (from 1 to 10);
48 - indexes 2 ... 1 + n for phases.
H A Dpmbus-core.rst178 support multiple phases, the phase parameter can be ignored. If the chip
179 supports multiple phases, a phase value of 0xff indicates all phases.
219 If the chip does not support multiple phases, the phase parameter is
220 ignored. Otherwise, a phase value of 0xff selects all phases.
229 not support multiple phases, the phase parameter is ignored. Otherwise, a phase
230 value of 0xff selects all phases.
H A Dmp2975.rst60 - 'k' is number of configured phases (from 1 to 8);
63 - indexes 2*n+1 ... 2*n + k for phases.
/openbmc/linux/tools/power/pm-graph/
H A Dbootgraph.py223 phases = ['kernel', 'user'] variable in Data
257 for p in data.phases:
281 for phase in self.phases:
384 for p in data.phases:
546 for p in data.phases:
557 for p in data.phases:
569 for phase in data.phases:
626 for phase in data.phases:
673 for p in data.phases:
/openbmc/linux/drivers/nfc/pn544/
H A Dpn544.c335 u8 phases = 0; in pn544_hci_start_poll() local
366 phases |= 1; /* Type A */ in pn544_hci_start_poll()
368 phases |= (1 << 2); /* Type F 212 */ in pn544_hci_start_poll()
369 phases |= (1 << 3); /* Type F 424 */ in pn544_hci_start_poll()
372 phases |= (1 << 5); /* NFC active */ in pn544_hci_start_poll()
375 PN544_PL_RDPHASES, &phases, 1); in pn544_hci_start_poll()
/openbmc/linux/Documentation/driver-api/pm/
H A Ddevices.rst134 they are called in phases for every device, respecting the parent-child
269 Suspending or resuming the system is done in several phases. Different phases
274 callbacks. The various phases always run after tasks have been frozen and
275 before they are unfrozen. Furthermore, the ``*_noirq`` phases run at a time
279 All phases use PM domain, bus, type, class or driver callbacks (that is, methods
316 the phases are: ``prepare``, ``suspend``, ``suspend_late``, ``suspend_noirq``.
323 suspend-related phases, during the ``prepare`` phase the device
342 ``suspend_noirq`` phases as well as all of the corresponding phases of
389 "quiesce device" and "save device state" phases, in which cases
406 At the end of these phases, drivers should have stopped all I/O transactions
[all …]
/openbmc/qemu/hw/usb/
H A Dxlnx-versal-usb2-ctrl-regs.c210 rc->phases.enter = usb2_ctrl_regs_reset_init; in usb2_ctrl_regs_class_init()
211 rc->phases.hold = usb2_ctrl_regs_reset_hold; in usb2_ctrl_regs_class_init()
/openbmc/qemu/hw/arm/
H A Dstellaris.c1428 rc->phases.enter = stellaris_i2c_reset_enter; in type_init()
1429 rc->phases.hold = stellaris_i2c_reset_hold; in type_init()
1430 rc->phases.exit = stellaris_i2c_reset_exit; in type_init()
1447 rc->phases.hold = stellaris_adc_reset_hold; in stellaris_adc_class_init()
1465 rc->phases.enter = stellaris_sys_reset_enter; in stellaris_sys_class_init()
1466 rc->phases.hold = stellaris_sys_reset_hold; in stellaris_sys_class_init()
1467 rc->phases.exit = stellaris_sys_reset_exit; in stellaris_sys_class_init()
/openbmc/qemu/hw/misc/
H A Dxlnx-zynqmp-crf.c248 rc->phases.enter = crf_reset_enter; in crf_class_init()
249 rc->phases.hold = crf_reset_hold; in crf_class_init()
H A Dxlnx-versal-xramc.c235 rc->phases.enter = xram_ctrl_reset_enter; in xram_ctrl_class_init()
236 rc->phases.hold = xram_ctrl_reset_hold; in xram_ctrl_class_init()
H A Dxlnx-zynqmp-apu-ctrl.c234 rc->phases.enter = zynqmp_apu_reset_enter; in zynqmp_apu_class_init()
235 rc->phases.hold = zynqmp_apu_reset_hold; in zynqmp_apu_class_init()
/openbmc/qemu/hw/adc/
H A Dnpcm7xx_adc.c282 rc->phases.enter = npcm7xx_adc_enter_reset; in npcm7xx_adc_class_init()
283 rc->phases.hold = npcm7xx_adc_hold_reset; in npcm7xx_adc_class_init()

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