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Searched refs:phase (Results 1 – 25 of 157) sorted by relevance

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/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_read_leveling.c91 u32 delay, phase, pup, cs; in ddr3_read_leveling_hw() local
108 phase = (reg >> REG_PHY_PHASE_OFFS) & in ddr3_read_leveling_hw()
111 dram_info->rl_val[cs][pup][P] = phase; in ddr3_read_leveling_hw()
112 if (phase > dram_info->rl_max_phase) in ddr3_read_leveling_hw()
113 dram_info->rl_max_phase = phase; in ddr3_read_leveling_hw()
114 if (phase < dram_info->rl_min_phase) in ddr3_read_leveling_hw()
115 dram_info->rl_min_phase = phase; in ddr3_read_leveling_hw()
181 u32 reg, cs, ecc, pup_num, phase, delay, pup; in ddr3_read_leveling_sw() local
290 phase = dram_info->rl_val[cs][pup][P]; in ddr3_read_leveling_sw()
292 ddr3_write_pup_reg(PUP_RL_MODE, cs, pup_num, phase, in ddr3_read_leveling_sw()
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H A Dddr3_write_leveling.c66 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
117 phase = in ddr3_write_leveling_hw()
121 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_hw()
186 u32 cs, cnt, pup_num, sum, phase, delay, max_pup_num, pup, sdram_offset; in ddr3_wl_supplement() local
343 phase = in ddr3_wl_supplement()
351 [P] = phase; in ddr3_wl_supplement()
361 phase, delay); in ddr3_wl_supplement()
364 phase = in ddr3_wl_supplement()
373 if ((phase == 0) in ddr3_wl_supplement()
374 || ((phase == 1) in ddr3_wl_supplement()
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H A Dddr3_hw_training.c547 void ddr3_write_pup_reg(u32 mode, u32 cs, u32 pup, u32 phase, u32 delay) in ddr3_write_pup_reg() argument
557 reg |= (phase << REG_PHY_PHASE_OFFS) | delay; in ddr3_write_pup_reg()
1048 u32 pup, reg, phase; in ddr3_get_min_max_rl_phase() local
1055 phase = ((reg >> 8) & 0x7); in ddr3_get_min_max_rl_phase()
1057 if (phase < *min) in ddr3_get_min_max_rl_phase()
1058 *min = phase; in ddr3_get_min_max_rl_phase()
1060 if (phase > *max) in ddr3_get_min_max_rl_phase()
1061 *max = phase; in ddr3_get_min_max_rl_phase()
/openbmc/qemu/tests/tcg/multiarch/gdbstub/
H A Dlate-attach.py11 phase = gdb.parse_and_eval("phase").string()
14 phase = "start"
16 if phase == "start":
19 phase = gdb.parse_and_eval("phase").string()
20 report(phase == "sigwait", "{} == \"sigwait\"".format(phase))
/openbmc/phosphor-power/phosphor-regulators/docs/
H A Dphase_fault_monitoring.md5 Some voltage regulators contain redundant phases. If a redundant phase fails,
7 lost, and the regulator may fail if another phase fails.
9 Voltage regulators can be monitored for redundant phase faults. If a fault is
13 application checks for redundant phase faults every 15 seconds.
15 A phase fault must be detected two consecutive times (15 seconds apart) before
19 A phase fault error will only be logged for a regulator once per system boot.
21 ## How phase fault detection is defined
32 If a different type of error occurs while detecting phase faults in a regulator:
/openbmc/phosphor-power/phosphor-regulators/docs/config_file/
H A Dlog_phase_fault.md5 Logs a redundant phase fault error for a voltage regulator. This action should
12 - An "N+1" regulator has one redundant phase
14 A phase fault occurs when a phase stops functioning properly. The redundancy
17 The phase fault type indicates the level of redundancy remaining **after** the
22 | n+1 | An "N+2" regulator has lost one redundant phase. The regulator is now at redundancy level …
H A Dphase_fault_detection.md5 Specifies how to detect and log redundant phase faults in a voltage regulator.
7 A voltage regulator is sometimes called a "phase controller" because it controls
10 A regulator may have redundant phases. If a redundant phase fails, the regulator
11 will continue to provide the desired output voltage. However, a phase fault
14 The technique used to detect a phase fault varies depending on the regulator
18 Phase fault detection is performed every 15 seconds. A phase fault must be
32 - Use the [log_phase_fault](log_phase_fault.md) action to log a phase fault
50 … array of strings | One or more comment lines describing the phase fault detection. …
63 "comments": ["Detect phase fault using I/O expander"],
72 "Detect N phase fault using I/O expander.",
/openbmc/qemu/tests/qtest/migration/
H A Dprecopy-tests.c670 const char *uri, const char *phase) in test_cancel_src_after_failed() argument
682 migration_event_wait(from, phase); in test_cancel_src_after_failed()
697 const char *uri, const char *phase) in test_cancel_src_after_cancelled() argument
708 migration_event_wait(from, phase); in test_cancel_src_after_cancelled()
721 const char *uri, const char *phase) in test_cancel_src_after_complete() argument
730 migration_event_wait(from, phase); in test_cancel_src_after_complete()
742 const char *uri, const char *phase) in test_cancel_src_after_none() argument
763 const char *uri, const char *phase) in test_cancel_src_pre_switchover() argument
778 migration_event_wait(from, phase); in test_cancel_src_pre_switchover()
792 g_autofree char *phase = g_path_get_basename(test_path); in test_cancel_src_after_status() local
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/openbmc/openbmc/poky/meta/recipes-connectivity/openssl/openssl/
H A D0001-Added-handshake-history-reporting-when-test-fails.patch69 +const char *handshake_connect_phase_name(connect_phase_t phase)
72 + (int)phase);
88 + connect_phase_t phase,
106 + new_entry->phase = phase;
126 -/* The status for each connection phase. */
181 + phase, status, server.status, client.status,
192 + phase, status, server.status, client.status,
235 +/* The status for each connection phase. */
259 + connect_phase_t phase;
298 +const char *handshake_connect_phase_name(connect_phase_t phase);
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/openbmc/u-boot/arch/arm/dts/
H A Dast2600a1-evb.dts11 timing-phase = <0x000700bf>;
15 timing-phase = <0x01084747>;
/openbmc/qemu/tests/tcg/multiarch/
H A Dlate-attach.c11 static const char *phase = "start"; variable
22 phase = "sigwait"; in main()
/openbmc/u-boot/drivers/usb/emul/
H A Dsandbox_flash.c58 enum cmd_phase phase; member
292 priv->phase = priv->transfer_len ? PHASE_DATA : PHASE_STATUS; in handle_ufi_command()
305 dev->name, pipe, ep, len, priv->phase); in sandbox_flash_bulk()
308 switch (priv->phase) { in sandbox_flash_bulk()
331 switch (priv->phase) { in sandbox_flash_bulk()
343 priv->phase = PHASE_STATUS; in sandbox_flash_bulk()
348 priv->phase = PHASE_STATUS; in sandbox_flash_bulk()
356 priv->phase = PHASE_START; in sandbox_flash_bulk()
/openbmc/qemu/docs/devel/
H A Dreset.rst109 Multi-phase mechanism
114 The resettable interface uses a multi-phase system to relieve objects and
124 1. The **enter** phase is executed when the object enters reset. It resets only
129 2. The **hold** phase is executed for entry into reset, once every object in the
130 group which is being reset has had its *enter* phase executed. At this point
133 3. The **exit** phase is executed when the object leaves the reset state.
142 The *exit* phase is executed only when the last reset operation ends. Therefore
148 the 'exit' phase and this sequencing makes sure no outstanding DMA request
164 phase of the reset; they are name ``phases.enter()``, ``phases.hold()`` and
181 /* call parent class enter phase */
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/openbmc/qemu/scripts/coccinelle/
H A Dreset-type.cocci1 // Convert device code using three-phase reset to add a ResetType
16 // implementations of the hold and exit phase methods" it includes
101 identifier phase;
104 - rc->phases.phase(obj)@p
105 + rc->phases.phase(obj, RESET_TYPE_COLD)
/openbmc/u-boot/include/
H A Dsym53c8xx.h525 #define WHEN(phase) (0x00030000 | (phase)) argument
526 #define IF(phase) (0x00020000 | (phase)) argument
/openbmc/qemu/docs/devel/migration/
H A Dvfio.rst10 Migration of VFIO devices consists of two phases: the optional pre-copy phase,
11 and the stop-and-copy phase. The pre-copy phase is iterative and allows to
13 transferred. The iterative pre-copy phase of migration allows for the guest to
65 vendor driver during iterative pre-copy phase.
142 phase. So, a page marked as dirty will be copied to the destination in both
143 phases. Copying dirty pages in pre-copy phase helps QEMU to predict if it can
144 achieve its downtime tolerances. If QEMU during pre-copy phase keeps finding
145 dirty pages continuously, then it understands that even in stop-and-copy phase,
149 which disables querying the dirty bitmap during pre-copy phase. If it is set to
150 off, all dirty pages will be copied to the destination in stop-and-copy phase
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/openbmc/u-boot/lib/efi_selftest/
H A Defi_selftest.c187 void efi_st_do_tests(const u16 *testname, unsigned int phase, in efi_st_do_tests() argument
199 if (test->phase != phase) in efi_st_do_tests()
H A Defi_selftest_exception.c47 .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
H A Defi_selftest_watchdog.c217 .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
225 .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
H A Defi_selftest_unaligned.c64 .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
H A Defi_selftest_rtc.c64 .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
/openbmc/u-boot/drivers/nvme/
H A Dnvme.c163 u16 phase = nvmeq->cq_phase; in nvme_submit_sync_cmd() local
175 if ((status & 0x01) == phase) in nvme_submit_sync_cmd()
185 status, phase, head); in nvme_submit_sync_cmd()
189 phase = !phase; in nvme_submit_sync_cmd()
193 nvmeq->cq_phase = phase; in nvme_submit_sync_cmd()
203 phase = !phase; in nvme_submit_sync_cmd()
207 nvmeq->cq_phase = phase; in nvme_submit_sync_cmd()
/openbmc/u-boot/arch/x86/include/asm/fsp/
H A Dfsp_api.h58 enum fsp_phase phase; member
/openbmc/qemu/hw/m68k/
H A Dnext-cube.c54 int8_t phase; member
940 if (rtc->phase < 8) { in next_rtc_data_in_irq()
943 if (rtc->phase == 7 && !next_rtc_cmd_is_write(rtc->command)) { in next_rtc_data_in_irq()
985 if (rtc->phase >= 8 && rtc->phase < 16) { in next_rtc_data_in_irq()
991 if (rtc->retval & (0x80 >> (rtc->phase - 8))) { in next_rtc_data_in_irq()
999 rtc->phase++; in next_rtc_data_in_irq()
1000 if (rtc->phase == 16 && next_rtc_cmd_is_write(rtc->command)) { in next_rtc_data_in_irq()
1021 rtc->phase = 0; in next_rtc_cmd_reset_irq()
1056 VMSTATE_INT8(phase, NeXTRTC),
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun4i.c133 static void mctl_enable_dll0(u32 phase) in mctl_enable_dll0() argument
138 ((phase >> 16) & 0x3f) << 6); in mctl_enable_dll0()
163 static void mctl_enable_dllx(u32 phase) in mctl_enable_dllx() argument
172 (phase & 0xf) << 14); in mctl_enable_dllx()
175 phase >>= 4; in mctl_enable_dllx()

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